OV - exec - Loop 670

0x4337a4 LDUR	X10, [X29, #472]

0x4337a8 ADD	X27, X27, #1

0x4337ac CMP	X27, X10

0x4337b0 B.GE	4339d0

0x4337b4 LDUR	X10, [X29, #440]

0x4337b8 LDR	X18, [X10, X27,LSL #3]

0x4337bc ADD	X17, X18, #1

0x4337c0 LDR	X0, [X11, X18,LSL #3]

0x4337c4 LDR	X10, [X11, X17,LSL #3]

0x4337c8 CMP	X0, X10

0x4337cc B.GE	4338e0

0x4337d0 LDUR	X10, [X29, #424]

0x4337d4 LDR	X3, [X19]

0x4337d8 ORN	X4, XZR, X18

0x4337dc LDR	X1, [X10]

0x4337e0 LDUR	X10, [X29, #480]

0x4337e4 LDR	X2, [X10]

0x4337e8 LDUR	X10, [X29, #432]

0x4337ec LDR	X5, [X10]

0x4337f0 LDUR	X10, [X29, #488]

0x4337f4 LDR	X6, [X10]

0x4337f8 LDUR	X10, [X29, #496]

0x4337fc LDR	X7, [X10]

0x433800 B	433814

  (674) 0x433804 LDR	X10, [X11, X17,LSL #3]

  (674) 0x433808 ADD	X0, X0, #1

  (674) 0x43380c CMP	X0, X10

  (674) 0x433810 B.GE	4338e0

  (674) 0x433814 LDR	X26, [X12, X0,LSL #3]

  (674) 0x433818 LDR	X20, [X21]

  (674) 0x43381c LDR	X10, [X13, X26,LSL #3]

  (674) 0x433820 SUB	X20, X20, #1

  (674) 0x433824 CMP	X10, X20

  (674) 0x433828 B.NE	433804

  (674) 0x43382c ADD	X30, X26, #1

  (674) 0x433830 LDR	X20, [X2, X30,LSL #3]

  (674) 0x433834 CMP	X20, #1

  (674) 0x433838 B.LT	433884

  (674) 0x43383c LDR	X10, [X1, X26,LSL #3]

  (674) 0x433840 ADD	X25, X20, X10

  (674) 0x433844 B	433854

    (676) 0x433848 ADD	X10, X10, #1

    (676) 0x43384c CMP	X10, X25

    (676) 0x433850 B.GE	433884

    (676) 0x433854 LDR	X20, [X21]

    (676) 0x433858 ADD	X20, X3, X20,LSL #3

    (676) 0x43385c LDUR	X28, [X20, #504]

    (676) 0x433860 LDR	X28, [X28, X10,LSL #3]

    (676) 0x433864 LDR	X24, [X22, X28,LSL #3]

    (676) 0x433868 CMP	X24, X4

    (676) 0x43386c B.EQ	433848

    (676) 0x433870 LDR	X20, [X20]

    (676) 0x433874 STR	X28, [X20, X8,LSL #3]

    (676) 0x433878 ADD	X8, X8, #1

    (676) 0x43387c STR	X4, [X22, X28,LSL #3]

    (676) 0x433880 B	433848

  (674) 0x433884 LDR	X20, [X6, X30,LSL #3]

  (674) 0x433888 CMP	X20, #1

  (674) 0x43388c B.LT	433804

  (674) 0x433890 LDR	X10, [X5, X26,LSL #3]

  (674) 0x433894 ADD	X25, X20, X10

  (674) 0x433898 B	4338ac

    (675) 0x4338a0 ADD	X10, X10, #1

    (675) 0x4338a4 CMP	X10, X25

    (675) 0x4338a8 B.GE	433804

    (675) 0x4338ac LDR	X20, [X21]

    (675) 0x4338b0 ADD	X20, X7, X20,LSL #3

    (675) 0x4338b4 LDUR	X24, [X20, #504]

    (675) 0x4338b8 LDR	X26, [X24, X10,LSL #3]

    (675) 0x4338bc LDR	X24, [X23, X26,LSL #3]

    (675) 0x4338c0 CMP	X24, X4

    (675) 0x4338c4 B.EQ	4338a0

    (675) 0x4338c8 LDR	X20, [X20]

    (675) 0x4338cc STR	X26, [X20, X9,LSL #3]

    (675) 0x4338d0 ADD	X9, X9, #1

    (675) 0x4338d4 STR	X4, [X23, X26,LSL #3]

    (675) 0x4338d8 B	4338a0

0x4338e0 LDR	X0, [X14, X18,LSL #3]

0x4338e4 LDR	X4, [X14, X17,LSL #3]

0x4338e8 CMP	X0, X4

0x4338ec B.GE	4337a4

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1104

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	3.00
Front-end cycles	3.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.08
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.92
P7 cycles	0.92
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	6.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	3.00
Front-end cycles	3.50
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	1.08
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.92
P7 cycles	0.92
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	6.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source file and lines	par_multi_interp.c:1072-1104
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1104.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 3.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.08	1.08	1.00	1.00	0.92	0.92	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00
cycles	2.00	2.00	1.08	1.08	1.00	1.00	0.92	0.92	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.50
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4337a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X27, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 4339d0 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x920>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X10, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X17, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X0, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X0, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 4338e0 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x830>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X3, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ORN X4, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X2, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X5, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 433814 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x764>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X4, [X14, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X0, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 4337a4 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x6f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.10
Source file and lines	par_multi_interp.c:1072-1104
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1104.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 3.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.08	1.08	1.00	1.00	0.92	0.92	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00
cycles	2.00	2.00	1.08	1.08	1.00	1.00	0.92	0.92	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.50
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4337a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X27, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X27, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 4339d0 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x920>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X18, [X10, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X17, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X0, [X11, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X0, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 4338e0 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x830>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X3, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ORN X4, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X2, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X5, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X6, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDUR X10, [X29, #496]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 433814 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x764>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X4, [X14, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X0, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 4337a4 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x6f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code