OV - exec - Loop 3576

  (3575) 0x49f620 STR	D0, [X13, X20,LSL #3]

  (3575) 0x49f624 ORR	X20, XZR, X0

  (3575) 0x49f628 CMP	X0, X19

  (3575) 0x49f62c B.EQ	4a00dc

  (3575) 0x49f630 LDR	D0, [X8, X20,LSL #3]

  (3575) 0x49f634 ADD	X0, X20, #1

  (3575) 0x49f638 ORR	X5, XZR, X16

  (3575) 0x49f63c LDR	X16, [X9, X0,LSL #3]

  (3575) 0x49f640 SUBS	X2, X16, X5

  (3575) 0x49f644 B.LE	49f620

  (3575) 0x49f648 CMP	X2, #2

  (3575) 0x49f64c B.CS	49f660

  (3575) 0x49f650 ORR	X1, XZR, X5

  (3575) 0x49f654 B	49f6b4

0x49f660 AND	X3, X2, #8127

0x49f664 MOVI	D1, #0

0x49f668 ADD	X4, X14, X5,LSL #3

0x49f66c ADD	X1, X5, X3

0x49f670 ADD	X5, X15, X5,LSL #3

0x49f674 ORR	X6, XZR, X3

0x49f678 HINT	#0

0x49f67c HINT	#0

  (3574) 0x49f680 LDP	X7, X21, [X5, #1016]

  (3574) 0x49f684 LDP	D2, D3, [X4, #1016]

  (3574) 0x49f688 SUBS	X6, X6, #2

  (3574) 0x49f68c ADD	X4, X4, #16

  (3574) 0x49f690 ADD	X5, X5, #16

  (3574) 0x49f694 LDR	D4, [X11, X7,LSL #3]

  (3574) 0x49f698 LDR	D5, [X11, X21,LSL #3]

  (3574) 0x49f69c FMSUB	D0, D4, D2, D0

  (3574) 0x49f6a0 FMSUB	D1, D5, D3, D1

  (3574) 0x49f6a4 B.NE	49f680

0x49f6a8 FADD	D0, D1, D0

0x49f6ac CMP	X2, X3

0x49f6b0 B.EQ	49f620

  (3575) 0x49f6b4 SUB	W2, W16, W1

  (3575) 0x49f6b8 ORR	X3, XZR, X1

  (3575) 0x49f6bc ANDS	X2, X2, #4160

  (3575) 0x49f6c0 B.EQ	49f6e0

    (3578) 0x49f6c4 LDR	X4, [X12, X3,LSL #3]

    (3578) 0x49f6c8 LDR	D1, [X10, X3,LSL #3]

    (3578) 0x49f6cc ADD	X3, X3, #1

    (3578) 0x49f6d0 SUBS	X2, X2, #1

    (3578) 0x49f6d4 LDR	D2, [X11, X4,LSL #3]

    (3578) 0x49f6d8 FMSUB	D0, D2, D1, D0

    (3578) 0x49f6dc B.NE	49f6c4

  (3575) 0x49f6e0 SUB	X1, X1, X16

  (3575) 0x49f6e4 CMN	X1, #4

  (3575) 0x49f6e8 B.HI	49f620

  (3575) 0x49f6ec SUB	X1, X16, X3

  (3575) 0x49f6f0 ADD	X2, X17, X3,LSL #3

  (3575) 0x49f6f4 ADD	X3, X18, X3,LSL #3

  (3575) 0x49f6f8 HINT	#0

  (3575) 0x49f6fc HINT	#0

    (3577) 0x49f700 LDP	X4, X5, [X2, #1008]

    (3577) 0x49f704 LDP	D2, D3, [X3, #1008]

    (3577) 0x49f708 SUBS	X1, X1, #4

    (3577) 0x49f70c LDR	D4, [X11, X5,LSL #3]

    (3577) 0x49f710 LDR	D1, [X11, X4,LSL #3]

    (3577) 0x49f714 LDP	X4, X5, [X2], #32

    (3577) 0x49f718 FMUL	D3, D4, D3

    (3577) 0x49f71c LDR	D4, [X11, X4,LSL #3]

    (3577) 0x49f720 FMADD	D1, D1, D2, D3

    (3577) 0x49f724 LDP	D2, D3, [X3], #32

    (3577) 0x49f728 FMADD	D1, D4, D2, D1

    (3577) 0x49f72c LDR	D2, [X11, X5,LSL #3]

    (3577) 0x49f730 FMADD	D1, D2, D3, D1

    (3577) 0x49f734 FSUB	D0, D0, S1

    (3577) 0x49f738 B.NE	49f700

  (3575) 0x49f73c B	49f620

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 307 - 314

--------------------------------------------------------------------------------

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18
Source	csr_matvec.c:310-310
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.13
CQA cycles if no scalar integer	1.13
CQA cycles if FP arith vectorized	0.88
CQA cycles if fully vectorized	0.56
Front-end cycles	1.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.08
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.92
P7 cycles	0.92
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	9.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.89
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.29
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18
Source	csr_matvec.c:310-310
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.13
CQA cycles if no scalar integer	1.13
CQA cycles if FP arith vectorized	0.88
CQA cycles if fully vectorized	0.56
Front-end cycles	1.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.08
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.92
P7 cycles	0.92
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	9.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.89
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18
Source file and lines	csr_matvec.c:307-314
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:307-314.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:310.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.13 to 0.56 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop does not load or store any data.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.08	1.08	1.00	1.00	0.92	0.92	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	1.08	1.08	1.00	1.00	0.92	0.92	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.13
Overall L1	1.13

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.13 cycles.

ASM code

In the binary file, the address of the loop is: 49f660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
AND X3, X2, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X4, X14, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X5, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X15, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X6, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X2, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 49f620 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18+0x730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18
Source file and lines	csr_matvec.c:307-314
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:307-314.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:310.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.13 to 0.56 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop does not load or store any data.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.08	1.08	1.00	1.00	0.92	0.92	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	1.08	1.08	1.00	1.00	0.92	0.92	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.13
Overall L1	1.13

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.13 cycles.

ASM code

In the binary file, the address of the loop is: 49f660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
AND X3, X2, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X4, X14, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X5, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X15, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X6, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X2, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 49f620 <hypre_CSRMatrixMatvecOutOfPlace.omp_outlined.18+0x730>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code