OV - exec - Loop 2873

  (2872) 0x483b88 LDUR	X8, [X29, #432]

  (2872) 0x483b8c ORR	X19, XZR, X2

  (2872) 0x483b90 ORR	X22, XZR, X1

  (2872) 0x483b94 CMP	X26, X8

  (2872) 0x483b98 B.GE	483e80

  (2872) 0x483b9c LDUR	X8, [X29, #424]

  (2872) 0x483ba0 LDR	X8, [X8]

  (2872) 0x483ba4 CBZ	X8, 483bc4

  (2872) 0x483ba8 LDUR	X8, [X29, #408]

  (2872) 0x483bac ADD	X1, X22, #1

  (2872) 0x483bb0 STR	X22, [X0, X26,LSL #3]

  (2872) 0x483bb4 LDR	D0, [X8]

  (2872) 0x483bb8 LDP	X8, X9, [SP, #104]

  (2872) 0x483bbc STR	X26, [X8, X22,LSL #3]

  (2872) 0x483bc0 STR	D0, [X9, X22,LSL #3]

  (2872) 0x483bc4 LDUR	X8, [X29, #416]

  (2872) 0x483bc8 LDR	X8, [X8]

  (2872) 0x483bcc CBZ	X8, 483d20

  (2872) 0x483bd0 LDR	X8, [SP, #96]

  (2872) 0x483bd4 ADD	X3, X8, X26,LSL #3

  (2872) 0x483bd8 LDP	X4, X8, [X3]

  (2872) 0x483bdc CMP	X4, X8

  (2872) 0x483be0 B.GE	483d20

  (2872) 0x483be4 LDP	X9, X8, [SP, #48]

  (2872) 0x483be8 ORR	X2, XZR, X19

  (2872) 0x483bec LDR	X5, [X9]

  (2872) 0x483bf0 LDR	X6, [X8]

  (2872) 0x483bf4 B	483c10

    (2877) 0x483c00 LDR	X8, [X3, #8]

    (2877) 0x483c04 ADD	X4, X4, #1

    (2877) 0x483c08 CMP	X4, X8

    (2877) 0x483c0c B.GE	483d24

    (2877) 0x483c10 LDP	X8, X9, [X29, #984]

    (2877) 0x483c14 LDR	X30, [X9, X4,LSL #3]

    (2877) 0x483c18 LDR	D0, [X8, X4,LSL #3]

    (2877) 0x483c1c ADD	X7, X30, #1

    (2877) 0x483c20 LDR	X8, [X13, X30,LSL #3]

    (2877) 0x483c24 LDR	X23, [X13, X7,LSL #3]

    (2877) 0x483c28 CMP	X8, X23

    (2877) 0x483c2c B.GE	483ca4

    (2877) 0x483c30 LDUR	X9, [X29, #440]

    (2877) 0x483c34 LDP	X10, X11, [X29, #1000]

    (2877) 0x483c38 LDR	X9, [X9]

    (2877) 0x483c3c LDR	X10, [X10]

    (2877) 0x483c40 LDR	X27, [X11]

    (2877) 0x483c44 B	483c64

      (2879) 0x483c48 LDR	D1, [X9, X8,LSL #3]

      (2879) 0x483c4c LDR	D2, [X10, X11,LSL #3]

      (2879) 0x483c50 FMADD	D1, D1, D0, D2

      (2879) 0x483c54 STR	D1, [X10, X11,LSL #3]

      (2879) 0x483c58 ADD	X8, X8, #1

      (2879) 0x483c5c CMP	X8, X23

      (2879) 0x483c60 B.GE	483ca4

      (2879) 0x483c64 LDR	X11, [X20]

      (2879) 0x483c68 LDR	X12, [X5, X8,LSL #3]

      (2879) 0x483c6c ADD	X24, X12, X11

      (2879) 0x483c70 LDR	X11, [X0, X24,LSL #3]

      (2879) 0x483c74 CMP	X11, X19

      (2879) 0x483c78 B.GE	483c48

      (2879) 0x483c7c STR	X2, [X0, X24,LSL #3]

      (2879) 0x483c80 LDR	D1, [X9, X8,LSL #3]

      (2879) 0x483c84 LDR	X11, [X20]

      (2879) 0x483c88 SUB	X11, X24, X11

      (2879) 0x483c8c STR	X11, [X27, X2,LSL #3]

      (2879) 0x483c90 FMUL	D1, D1, D0

      (2879) 0x483c94 LDR	X23, [X13, X7,LSL #3]

      (2879) 0x483c98 STR	D1, [X10, X2,LSL #3]

      (2879) 0x483c9c ADD	X2, X2, #1

      (2879) 0x483ca0 B	483c58

    (2877) 0x483ca4 LDR	X8, [X14, X30,LSL #3]

    (2877) 0x483ca8 LDR	X23, [X14, X7,LSL #3]

    (2877) 0x483cac CMP	X8, X23

    (2877) 0x483cb0 B.GE	483c00

    (2877) 0x483cb4 LDUR	X9, [X29, #448]

    (2877) 0x483cb8 LDR	X10, [X25]

    (2877) 0x483cbc LDR	X27, [X21]

    (2877) 0x483cc0 LDR	X9, [X9]

    (2877) 0x483cc4 B	483ce4

      (2878) 0x483cc8 LDR	D1, [X9, X8,LSL #3]

      (2878) 0x483ccc LDR	D2, [X10, X11,LSL #3]

      (2878) 0x483cd0 FMADD	D1, D1, D0, D2

      (2878) 0x483cd4 STR	D1, [X10, X11,LSL #3]

      (2878) 0x483cd8 ADD	X8, X8, #1

      (2878) 0x483cdc CMP	X8, X23

      (2878) 0x483ce0 B.GE	483c00

      (2878) 0x483ce4 LDR	X24, [X6, X8,LSL #3]

      (2878) 0x483ce8 LDR	X11, [X0, X24,LSL #3]

      (2878) 0x483cec CMP	X11, X22

      (2878) 0x483cf0 B.GE	483cc8

      (2878) 0x483cf4 LDR	D1, [X9, X8,LSL #3]

      (2878) 0x483cf8 STR	X1, [X0, X24,LSL #3]

      (2878) 0x483cfc STR	X24, [X27, X1,LSL #3]

      (2878) 0x483d00 LDR	X23, [X14, X7,LSL #3]

      (2878) 0x483d04 FMUL	D1, D1, D0

      (2878) 0x483d08 STR	D1, [X10, X1,LSL #3]

      (2878) 0x483d0c ADD	X1, X1, #1

      (2878) 0x483d10 B	483cd8

  (2872) 0x483d20 ORR	X2, XZR, X19

  (2872) 0x483d24 LDR	X3, [X15, X26,LSL #3]

  (2872) 0x483d28 ADD	X26, X26, #1

  (2872) 0x483d2c LDR	X8, [X15, X26,LSL #3]

  (2872) 0x483d30 CMP	X3, X8

  (2872) 0x483d34 B.GE	483b88

0x483d38 LDP	X9, X8, [SP, #64]

0x483d3c LDR	X4, [X9]

0x483d40 LDR	X5, [X8]

0x483d44 LDP	X9, X8, [SP, #80]

0x483d48 LDR	X6, [X9]

0x483d4c LDR	X7, [X8]

0x483d50 B	483d70

0x483d60 LDR	X8, [X15, X26,LSL #3]

0x483d64 ADD	X3, X3, #1

0x483d68 CMP	X3, X8

0x483d6c B.GE	483b88

0x483d70 LDR	X8, [X16, X3,LSL #3]

0x483d74 LDR	D0, [X17, X3,LSL #3]

0x483d78 ADD	X30, X8, #1

0x483d7c LDR	X9, [X18, X8,LSL #3]

0x483d80 LDR	X27, [X18, X30,LSL #3]

0x483d84 CMP	X9, X27

0x483d88 B.GE	483dec

0x483d8c LDUR	X10, [X29, #464]

0x483d90 LDR	X23, [X25]

0x483d94 LDR	X24, [X21]

0x483d98 LDR	X10, [X10]

0x483d9c B	483dbc

  (2876) 0x483da0 LDR	D1, [X10, X9,LSL #3]

  (2876) 0x483da4 LDR	D2, [X23, X12,LSL #3]

  (2876) 0x483da8 FMADD	D1, D1, D0, D2

  (2876) 0x483dac STR	D1, [X23, X12,LSL #3]

  (2876) 0x483db0 ADD	X9, X9, #1

  (2876) 0x483db4 CMP	X9, X27

  (2876) 0x483db8 B.GE	483dec

  (2876) 0x483dbc LDR	X11, [X4, X9,LSL #3]

  (2876) 0x483dc0 LDR	X12, [X0, X11,LSL #3]

  (2876) 0x483dc4 CMP	X12, X22

  (2876) 0x483dc8 B.GE	483da0

  (2876) 0x483dcc LDR	D1, [X10, X9,LSL #3]

  (2876) 0x483dd0 STR	X1, [X0, X11,LSL #3]

  (2876) 0x483dd4 STR	X11, [X24, X1,LSL #3]

  (2876) 0x483dd8 LDR	X27, [X18, X30,LSL #3]

  (2876) 0x483ddc FMUL	D1, D1, D0

  (2876) 0x483de0 STR	D1, [X23, X1,LSL #3]

  (2876) 0x483de4 ADD	X1, X1, #1

  (2876) 0x483de8 B	483db0

0x483dec LDR	X9, [X28]

0x483df0 CBZ	X9, 483d60

0x483df4 LDR	X8, [X5, X8,LSL #3]

0x483df8 LDR	X23, [X5, X30,LSL #3]

0x483dfc CMP	X8, X23

0x483e00 B.GE	483d60

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 970

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	P12, P13, P14,
Function	hypre_ParMatmul.omp_outlined.7
Source	par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	3.00
Front-end cycles	3.63
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	0.92
P3 cycles	0.92
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	6.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	29.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	P12, P13, P14,
Function	hypre_ParMatmul.omp_outlined.7
Source	par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	3.00
Front-end cycles	3.63
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	0.92
P3 cycles	0.92
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	6.00
P13 cycles	6.00
P14 cycles	6.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	29.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul.omp_outlined.7
Source file and lines	par_csr_matop.c:865-970
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-970.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 2.67 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 3.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	0.92	0.92	0.83	0.83	0.75	0.75	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00
cycles	3.00	3.00	0.92	0.92	0.83	0.83	0.75	0.75	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.63
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

27% of peak load performance is reached (26.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 483d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X4, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X9, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X6, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 483d70 <hypre_ParMatmul.omp_outlined.7+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X3, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 483b88 <hypre_ParMatmul.omp_outlined.7+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D0, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X30, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X9, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X27, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
CMP X9, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 483dec <hypre_ParMatmul.omp_outlined.7+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X23, [X25]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X24, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
B 483dbc <hypre_ParMatmul.omp_outlined.7+0x42c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CBZ X9, 483d60 <hypre_ParMatmul.omp_outlined.7+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X23, [X5, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X8, X23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 483d60 <hypre_ParMatmul.omp_outlined.7+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul.omp_outlined.7
Source file and lines	par_csr_matop.c:865-970
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-970.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 2.67 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 3.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	0.92	0.92	0.83	0.83	0.75	0.75	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00
cycles	3.00	3.00	0.92	0.92	0.83	0.83	0.75	0.75	0.00	0.00	0.00	0.00	6.00	6.00	6.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.63
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

27% of peak load performance is reached (26.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 483d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X4, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X9, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X6, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 483d70 <hypre_ParMatmul.omp_outlined.7+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X3, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 483b88 <hypre_ParMatmul.omp_outlined.7+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D0, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X30, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X9, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X27, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
CMP X9, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 483dec <hypre_ParMatmul.omp_outlined.7+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X23, [X25]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X24, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
B 483dbc <hypre_ParMatmul.omp_outlined.7+0x42c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CBZ X9, 483d60 <hypre_ParMatmul.omp_outlined.7+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X23, [X5, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X8, X23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 483d60 <hypre_ParMatmul.omp_outlined.7+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code