OV - exec - Loop 2667

	Loop Id: 2667	Module: exec	Source: ams.c:3662-3682	Coverage: 1.66%

  (2666) 0x4795d4 ADRP	X0,

  (2666) 0x4795d8 ADD	X0, X0, #920

  (2666) 0x4795dc ORR	W1, WZR, W20

  (2666) 0x4795e0 BL	40f910

  (2666) 0x4795e4 LDP	X20, X19, [SP, #160]

  (2666) 0x4795e8 LDP	X22, X21, [SP, #144]

  (2666) 0x4795ec LDP	X24, X23, [SP, #128]

  (2666) 0x4795f0 LDP	X26, X25, [SP, #112]

  (2666) 0x4795f4 LDP	X28, X27, [SP, #96]

  (2666) 0x4795f8 LDP	X29, X30, [SP, #80]

  (2666) 0x4795fc ADD	SP, SP, #176

  (2666) 0x479600 RET

  (2666) 0x479604 LDP	X16, X17, [X29, #112]

  (2666) 0x479608 LDP	X8, X0, [X29, #144]

  (2666) 0x47960c LDP	X18, X4, [X29, #128]

  (2666) 0x479610 ADD	X1, X1, #1

  (2666) 0x479614 LDP	X14, X15, [X29, #96]

  (2666) 0x479618 LDR	X10, [X24]

  (2666) 0x47961c ADD	X6, X10, #16

  (2666) 0x479620 LDR	X13, [X21]

  (2666) 0x479624 LDR	X16, [X16]

  (2666) 0x479628 LDR	X17, [X17]

  (2666) 0x47962c LDR	X11, [X23]

  (2666) 0x479630 LDR	X12, [X22]

  (2666) 0x479634 LDR	X14, [X14]

  (2666) 0x479638 LDR	X15, [X15]

  (2666) 0x47963c LDR	X18, [X18]

  (2666) 0x479640 LDR	X0, [X0]

  (2666) 0x479644 LDR	X4, [X4]

  (2666) 0x479648 ADD	X5, X13, #16

  (2666) 0x47964c ADD	X2, X13, #8

  (2666) 0x479650 ADD	X3, X10, #8

  (2666) 0x479654 ADD	X7, X16, #8

  (2666) 0x479658 STP	X5, X6, [SP, #32]

  (2666) 0x47965c ADD	X21, X17, #8

  (2666) 0x479660 ADD	X6, X17, #16

  (2666) 0x479664 ADD	X5, X16, #16

  (2666) 0x479668 STP	X5, X6, [SP, #16]

  (2666) 0x47966c B	4796a8

0x479680 LDR	D1, [X8]

0x479684 FMUL	D0, D1, D0

0x479688 LDR	D1, [X0, X9,LSL #3]

0x47968c FDIV	D0, D0, D1

0x479690 LDR	D1, [X4, X9,LSL #3]

0x479694 FADD	D0, D1, D0

0x479698 STR	D0, [X4, X9,LSL #3]

  (2666) 0x47969c ORR	X9, XZR, X24

  (2666) 0x4796a0 CMP	X24, X1

  (2666) 0x4796a4 B.EQ	4795d4

  (2666) 0x4796a8 LDR	X5, [X11, X9,LSL #3]

  (2666) 0x4796ac LDR	D1, [X19]

  (2666) 0x4796b0 LDR	D0, [X10, X5,LSL #3]

  (2666) 0x4796b4 FCMP	D0, D1

  (2666) 0x4796b8 B.EQ	4796e0

0x4796bc LDR	D0, [X12, X9,LSL #3]

0x4796c0 ADD	X24, X9, #1

0x4796c4 LDR	X25, [X11, X24,LSL #3]

0x4796c8 SUBS	X27, X25, X5

0x4796cc B.LE	4797c0

0x4796d0 CMP	X27, #2

0x4796d4 B.CS	4796e8

0x4796d8 ORR	X26, XZR, X5

0x4796dc B	479734

  (2666) 0x4796e0 ADD	X24, X9, #1

  (2666) 0x4796e4 B	47969c

0x4796e8 AND	X6, X27, #8127

0x4796ec MOVI	D1, #0

0x4796f0 ADD	X30, X2, X5,LSL #3

0x4796f4 ADD	X26, X5, X6

0x4796f8 ADD	X5, X3, X5,LSL #3

0x4796fc ORR	X28, XZR, X6

  (2671) 0x479700 LDP	X22, X23, [X30, #1016]

  (2671) 0x479704 LDP	D2, D3, [X5, #1016]

  (2671) 0x479708 SUBS	X28, X28, #2

  (2671) 0x47970c ADD	X30, X30, #16

  (2671) 0x479710 ADD	X5, X5, #16

  (2671) 0x479714 LDR	D4, [X14, X22,LSL #3]

  (2671) 0x479718 LDR	D5, [X14, X23,LSL #3]

  (2671) 0x47971c FMSUB	D0, D4, D2, D0

  (2671) 0x479720 FMSUB	D1, D5, D3, D1

  (2671) 0x479724 B.NE	479700

0x479728 FADD	D0, D1, D0

0x47972c CMP	X27, X6

0x479730 B.EQ	4797c0

0x479734 SUB	W5, W25, W26

0x479738 ORR	X27, XZR, X26

0x47973c ANDS	X5, X5, #4160

0x479740 B.EQ	479760

  (2673) 0x479744 LDR	X6, [X13, X27,LSL #3]

  (2673) 0x479748 LDR	D1, [X10, X27,LSL #3]

  (2673) 0x47974c ADD	X27, X27, #1

  (2673) 0x479750 SUBS	X5, X5, #1

  (2673) 0x479754 LDR	D2, [X14, X6,LSL #3]

  (2673) 0x479758 FMSUB	D0, D2, D1, D0

  (2673) 0x47975c B.NE	479744

0x479760 SUB	X5, X26, X25

0x479764 CMN	X5, #4

0x479768 B.HI	4797c0

0x47976c LDP	X5, X6, [SP, #32]

0x479770 SUB	X25, X25, X27

0x479774 ADD	X26, X6, X27,LSL #3

0x479778 ADD	X27, X5, X27,LSL #3

0x47977c HINT	#0

  (2672) 0x479780 LDP	X5, X6, [X27, #1008]

  (2672) 0x479784 LDP	D2, D3, [X26, #1008]

  (2672) 0x479788 SUBS	X25, X25, #4

  (2672) 0x47978c LDR	D4, [X14, X6,LSL #3]

  (2672) 0x479790 LDR	D1, [X14, X5,LSL #3]

  (2672) 0x479794 LDP	X5, X6, [X27], #32

  (2672) 0x479798 FMUL	D3, D4, D3

  (2672) 0x47979c LDR	D4, [X14, X5,LSL #3]

  (2672) 0x4797a0 FMADD	D1, D1, D2, D3

  (2672) 0x4797a4 LDP	D2, D3, [X26], #32

  (2672) 0x4797a8 FMADD	D1, D4, D2, D1

  (2672) 0x4797ac LDR	D2, [X14, X6,LSL #3]

  (2672) 0x4797b0 FMADD	D1, D2, D3, D1

  (2672) 0x4797b4 FSUB	D0, D0, S1

  (2672) 0x4797b8 B.NE	479780

0x4797bc HINT	#0

0x4797c0 LDR	X5, [X15, X9,LSL #3]

0x4797c4 LDR	X25, [X15, X24,LSL #3]

0x4797c8 SUBS	X27, X25, X5

0x4797cc B.LE	479680

0x4797d0 CMP	X27, #2

0x4797d4 B.CS	4797e0

0x4797d8 ORR	X26, XZR, X5

0x4797dc B	479834

0x4797e0 AND	X28, X27, #8127

0x4797e4 MOVI	D1, #0

0x4797e8 ADD	X30, X7, X5,LSL #3

0x4797ec ADD	X26, X5, X28

0x4797f0 ADD	X5, X21, X5,LSL #3

0x4797f4 ORR	X6, XZR, X28

0x4797f8 HINT	#0

0x4797fc HINT	#0

  (2668) 0x479800 LDP	X22, X23, [X30, #1016]

  (2668) 0x479804 LDP	D2, D3, [X5, #1016]

  (2668) 0x479808 SUBS	X6, X6, #2

  (2668) 0x47980c ADD	X30, X30, #16

  (2668) 0x479810 ADD	X5, X5, #16

  (2668) 0x479814 LDR	D4, [X18, X22,LSL #3]

  (2668) 0x479818 LDR	D5, [X18, X23,LSL #3]

  (2668) 0x47981c FMSUB	D0, D4, D2, D0

  (2668) 0x479820 FMSUB	D1, D5, D3, D1

  (2668) 0x479824 B.NE	479800

0x479828 FADD	D0, D1, D0

0x47982c CMP	X27, X28

0x479830 B.EQ	479680

0x479834 SUB	W5, W25, W26

0x479838 ORR	X27, XZR, X26

0x47983c ANDS	X5, X5, #4160

0x479840 B.EQ	479860

  (2670) 0x479844 LDR	X6, [X16, X27,LSL #3]

  (2670) 0x479848 LDR	D1, [X17, X27,LSL #3]

  (2670) 0x47984c ADD	X27, X27, #1

  (2670) 0x479850 SUBS	X5, X5, #1

  (2670) 0x479854 LDR	D2, [X18, X6,LSL #3]

  (2670) 0x479858 FMSUB	D0, D2, D1, D0

  (2670) 0x47985c B.NE	479844

0x479860 SUB	X5, X26, X25

0x479864 CMN	X5, #4

0x479868 B.HI	479680

0x47986c LDP	X5, X6, [SP, #16]

0x479870 SUB	X25, X25, X27

0x479874 ADD	X26, X6, X27,LSL #3

0x479878 ADD	X27, X5, X27,LSL #3

0x47987c HINT	#0

  (2669) 0x479880 LDP	X5, X6, [X27, #1008]

  (2669) 0x479884 LDP	D2, D3, [X26, #1008]

  (2669) 0x479888 SUBS	X25, X25, #4

  (2669) 0x47988c LDR	D4, [X18, X6,LSL #3]

  (2669) 0x479890 LDR	D1, [X18, X5,LSL #3]

  (2669) 0x479894 LDP	X5, X6, [X27], #32

  (2669) 0x479898 FMUL	D3, D4, D3

  (2669) 0x47989c LDR	D4, [X18, X5,LSL #3]

  (2669) 0x4798a0 FMADD	D1, D1, D2, D3

  (2669) 0x4798a4 LDP	D2, D3, [X26], #32

  (2669) 0x4798a8 FMADD	D1, D4, D2, D1

  (2669) 0x4798ac LDR	D2, [X18, X6,LSL #3]

  (2669) 0x4798b0 FMADD	D1, D2, D3, D1

  (2669) 0x4798b4 FSUB	D0, D0, S1

  (2669) 0x4798b8 B.NE	479880

0x4798bc B	479680

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

3663: #endif

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.87
CQA speedup if FP arith vectorized	1.44
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads.omp_outlined.28
Source	ams.c:3671-3672,ams.c:3677-3677,ams.c:3682-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.13
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	5.63
CQA cycles if fully vectorized	4.06
Front-end cycles	8.13
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	5.83
P3 cycles	5.83
P4 cycles	5.83
P5 cycles	5.83
P6 cycles	5.83
P7 cycles	5.83
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	3.50
P13 cycles	3.17
P14 cycles	3.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	65.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.62
Nb FLOP add-sub	3.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.82
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.87
CQA speedup if FP arith vectorized	1.44
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRRelaxThreads.omp_outlined.28
Source	ams.c:3671-3672,ams.c:3677-3677,ams.c:3682-3682
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.13
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	5.63
CQA cycles if fully vectorized	4.06
Front-end cycles	8.13
P0 cycles	6.50
P1 cycles	6.50
P2 cycles	5.83
P3 cycles	5.83
P4 cycles	5.83
P5 cycles	5.83
P6 cycles	5.83
P7 cycles	5.83
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	3.50
P13 cycles	3.17
P14 cycles	3.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	65.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.62
Nb FLOP add-sub	3.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.82
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRRelaxThreads.omp_outlined.28
Source file and lines	ams.c:3662-3682
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3671-3672,3677,3682.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.13 to 2.83 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.13 to 4.06 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 5 FP arithmetical operations:

3: addition or subtraction
1: multiply
1: divide

The binary loop is loading 88 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	70
loop length	280
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.50	6.50	5.83	5.83	5.83	5.83	5.83	5.83	2.00	2.00	2.00	2.00	3.50	3.17	3.33	0.00	0.00
cycles	6.50	6.50	5.83	5.83	5.83	5.83	5.83	5.83	2.00	2.00	2.00	2.00	3.50	3.17	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	8.13
Overall L1	8.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.13 cycles. At this rate:

11% of peak load performance is reached (10.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (0.98 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 479680

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR D1, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FDIV D0, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR D1, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X24, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X11, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUBS X27, X25, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 4797c0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 4796e8 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 479734 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X6, X27, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X30, X2, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X5, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X3, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X27, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4797c0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W25, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X27, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X5, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 479760 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X26, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMN X5, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 4797c0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X6, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X25, X25, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X6, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X27, X5, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X5, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X15, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUBS X27, X25, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 479680 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 4797e0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 479834 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X28, X27, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X30, X7, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X5, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X21, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X6, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X27, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 479680 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W25, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X27, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X5, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 479860 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X26, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMN X5, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 479680 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X6, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X25, X25, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X6, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X27, X5, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
B 479680 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParCSRRelaxThreads.omp_outlined.28
Source file and lines	ams.c:3662-3682
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.13 to 2.83 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 8.13 to 4.06 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 5 FP arithmetical operations:

3: addition or subtraction
1: multiply
1: divide

The binary loop is loading 88 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	70
loop length	280
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.50	6.50	5.83	5.83	5.83	5.83	5.83	5.83	2.00	2.00	2.00	2.00	3.50	3.17	3.33	0.00	0.00
cycles	6.50	6.50	5.83	5.83	5.83	5.83	5.83	5.83	2.00	2.00	2.00	2.00	3.50	3.17	3.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	8.13
Overall L1	8.13

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.13 cycles. At this rate:

11% of peak load performance is reached (10.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (0.98 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 479680

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR D1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR D1, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FDIV D0, D0, D1	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR D1, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X24, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X11, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUBS X27, X25, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 4797c0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 4796e8 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 479734 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X6, X27, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X30, X2, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X5, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X3, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X27, X6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4797c0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W25, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X27, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X5, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 479760 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X26, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMN X5, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 4797c0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X6, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X25, X25, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X6, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X27, X5, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X5, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X15, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUBS X27, X25, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 479680 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X27, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 4797e0 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 479834 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X28, X27, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X30, X7, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X5, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X21, X5,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X6, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
FADD D0, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X27, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 479680 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W25, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X27, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X5, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 479860 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X26, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMN X5, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 479680 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X6, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X25, X25, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X6, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X27, X5, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
B 479680 <hypre_ParCSRRelaxThreads.omp_outlined.28+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code