OV - exec - Loop 2207

	Loop Id: 2207	Module: exec	Source: par_strength.c:2011-2048	Coverage: 0.14%

0x469740 LDR	X7, [X9, X0,LSL #3]

0x469744 ADD	X2, X2, #1

0x469748 CMP	X2, X7

0x46974c B.GE	46988c

0x469750 LDR	X19, [X10, X2,LSL #3]

0x469754 LDR	X7, [X11, X19,LSL #3]

0x469758 CMP	X7, #1

0x46975c B.LT	469788

0x469760 LDR	X7, [X3, X19,LSL #3]

0x469764 LDR	X20, [X24, X7,LSL #3]

0x469768 CMP	X20, X17

0x46976c B.GE	469788

0x469770 LDUR	X20, [X29, #480]

0x469774 STR	X20, [X24, X7,LSL #3]

0x469778 STR	X7, [X4, X20,LSL #3]

0x46977c LDUR	X7, [X29, #480]

0x469780 ADD	X7, X7, #1

0x469784 STUR	X7, [X29, #480]

0x469788 ADD	X7, X19, #1

0x46978c LDR	X20, [X9, X19,LSL #3]

0x469790 LDR	X23, [X9, X7,LSL #3]

0x469794 CMP	X20, X23

0x469798 B.GE	469820

0x46979c LDUR	X21, [X29, #456]

0x4697a0 LDUR	X26, [X29, #440]

0x4697a4 LDR	X21, [X21]

0x4697a8 LDR	X26, [X26]

0x4697ac B	4697cc

  (2209) 0x4697c0 ADD	X20, X20, #1

  (2209) 0x4697c4 CMP	X20, X23

  (2209) 0x4697c8 B.GE	469820

  (2209) 0x4697cc LDR	X27, [X10, X20,LSL #3]

  (2209) 0x4697d0 LDR	X28, [X11, X27,LSL #3]

  (2209) 0x4697d4 CMP	X28, #1

  (2209) 0x4697d8 B.LT	4697c0

  (2209) 0x4697dc LDR	X27, [X21, X27,LSL #3]

  (2209) 0x4697e0 CMP	X27, X22

  (2209) 0x4697e4 B.EQ	4697c0

  (2209) 0x4697e8 LDR	X28, [X24, X27,LSL #3]

  (2209) 0x4697ec CMP	X28, X17

  (2209) 0x4697f0 B.GE	4697c0

  (2209) 0x4697f4 LDUR	X23, [X29, #480]

  (2209) 0x4697f8 STR	X23, [X24, X27,LSL #3]

  (2209) 0x4697fc STR	X27, [X26, X23,LSL #3]

  (2209) 0x469800 LDUR	X23, [X29, #480]

  (2209) 0x469804 ADD	X23, X23, #1

  (2209) 0x469808 STUR	X23, [X29, #480]

  (2209) 0x46980c LDR	X23, [X9, X7,LSL #3]

  (2209) 0x469810 B	4697c0

0x469820 LDR	X19, [X12, X19,LSL #3]

0x469824 LDR	X21, [X12, X7,LSL #3]

0x469828 CMP	X19, X21

0x46982c B.GE	469740

0x469830 LDUR	X20, [X29, #464]

0x469834 LDR	X23, [X30]

0x469838 LDR	X20, [X20]

0x46983c B	46984c

  (2208) 0x469840 ADD	X19, X19, #1

  (2208) 0x469844 CMP	X19, X21

  (2208) 0x469848 B.GE	469740

  (2208) 0x46984c LDR	X26, [X5, X19,LSL #3]

  (2208) 0x469850 LDR	X27, [X6, X26,LSL #3]

  (2208) 0x469854 CMP	X27, #1

  (2208) 0x469858 B.LT	469840

  (2208) 0x46985c LDR	X26, [X20, X26,LSL #3]

  (2208) 0x469860 LDR	X27, [X25, X26,LSL #3]

  (2208) 0x469864 CMP	X27, X18

  (2208) 0x469868 B.GE	469840

  (2208) 0x46986c LDUR	X21, [X29, #472]

  (2208) 0x469870 STR	X21, [X25, X26,LSL #3]

  (2208) 0x469874 STR	X26, [X23, X21,LSL #3]

  (2208) 0x469878 LDUR	X21, [X29, #472]

  (2208) 0x46987c ADD	X21, X21, #1

  (2208) 0x469880 STUR	X21, [X29, #472]

  (2208) 0x469884 LDR	X21, [X12, X7,LSL #3]

  (2208) 0x469888 B	469840

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2011 - 2048

--------------------------------------------------------------------------------

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P12,
Function	hypre_BoomerAMGCreate2ndS.omp_outlined.16
Source	par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.17
CQA cycles if no scalar integer	7.17
CQA cycles if FP arith vectorized	7.17
CQA cycles if fully vectorized	3.58
Front-end cycles	4.50
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	1.42
P3 cycles	1.42
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	7.17
P13 cycles	6.83
P14 cycles	7.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.44
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P12,
Function	hypre_BoomerAMGCreate2ndS.omp_outlined.16
Source	par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.17
CQA cycles if no scalar integer	7.17
CQA cycles if FP arith vectorized	7.17
CQA cycles if fully vectorized	3.58
Front-end cycles	4.50
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	1.42
P3 cycles	1.42
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	7.17
P13 cycles	6.83
P14 cycles	7.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	36.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.44
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreate2ndS.omp_outlined.16
Source file and lines	par_strength.c:2011-2048
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2048.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2021,2024,2038.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.17 to 3.58 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	1.42	1.42	1.33	1.33	1.25	1.25	0.00	0.00	0.00	0.00	7.17	6.83	7.00	1.50	1.50
cycles	3.50	3.50	1.42	1.42	1.33	1.33	1.25	1.25	0.00	0.00	0.00	0.00	7.17	6.83	7.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	7.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.17 cycles. At this rate:

20% of peak load performance is reached (20.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 469750

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X7, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X2, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46988c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xe4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 469788 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X3, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469788 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X20, [X29, #480]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [X4, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X7, [X29, #480]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STUR X7, [X29, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X20, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X20, X23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469820 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xde0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X21, [X29, #456]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X26, [X29, #440]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X26]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4697cc <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [X12, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X12, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X19, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 469740 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X20, [X29, #464]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X20, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46984c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xe0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGCreate2ndS.omp_outlined.16
Source file and lines	par_strength.c:2011-2048
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.17 to 3.58 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 144 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	1.42	1.42	1.33	1.33	1.25	1.25	0.00	0.00	0.00	0.00	7.17	6.83	7.00	1.50	1.50
cycles	3.50	3.50	1.42	1.42	1.33	1.33	1.25	1.25	0.00	0.00	0.00	0.00	7.17	6.83	7.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	7.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.17 cycles. At this rate:

20% of peak load performance is reached (20.09 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 469750

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X7, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X2, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46988c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xe4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X7, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 469788 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [X3, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469788 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X20, [X29, #480]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [X4, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X7, [X29, #480]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STUR X7, [X29, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X20, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X20, X23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 469820 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xde0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X21, [X29, #456]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X26, [X29, #440]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X26]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4697cc <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [X12, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X12, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X19, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 469740 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X20, [X29, #464]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X20, [X20]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46984c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xe0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code