OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR.omp

	Function: hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage (incl. loops): 0.27% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

3323:       		           not_found = 0;

3324:       		           break;

3325:       	                }

3326:       	             }

3327:       	             if (not_found)

3328:       	             {

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

[...]

3417: 	                }

3418: 	                not_found = 1;

3419: 	             }

3420: 	             else  /* insert into diag */

3421: 	             {

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x496c90 SUB	SP, SP, #352

0x496c94 STP	X29, X30, [SP, #256]

0x496c98 STP	X28, X27, [SP, #272]

0x496c9c STP	X26, X25, [SP, #288]

0x496ca0 STP	X24, X23, [SP, #304]

0x496ca4 STP	X22, X21, [SP, #320]

0x496ca8 STP	X20, X19, [SP, #336]

0x496cac ADD	X29, SP, #256

0x496cb0 ORR	X28, XZR, X7

0x496cb4 STUR	X6, [X29, #400]

0x496cb8 ORR	X24, XZR, X5

0x496cbc ORR	X21, XZR, X4

0x496cc0 ORR	X23, XZR, X3

0x496cc4 ORR	X26, XZR, X2

0x496cc8 ORR	X25, XZR, X0

0x496ccc BL	4a89f0

0x496cd0 ORR	X27, XZR, X0

0x496cd4 BL	4a8a10

0x496cd8 LDR	X8, [X26]

0x496cdc ORR	X22, XZR, X0

0x496ce0 SDIV	X10, X8, X27

0x496ce4 ADD	X13, X10, #1

0x496ce8 MSUB	X11, X10, X27, X8

0x496cec ADD	X8, X0, #1

0x496cf0 MADD	X12, X10, X8, X11

0x496cf4 MADD	X8, X13, X8, XZR

0x496cf8 MADD	X9, X10, X0, X11

0x496cfc MADD	X14, X13, X0, XZR

0x496d00 CMP	X0, X11

0x496d04 CSEL	X15, X12, X8, #10

0x496d08 LDR	X12, [X23]

0x496d0c CSEL	X16, X9, X14, #10

0x496d10 ADD	X8, X12, X0,LSL #3

0x496d14 STR	XZR, [X8]

0x496d18 CMP	X16, X15

0x496d1c B.GE	496dd8

0x496d20 CMP	X22, X11

0x496d24 LDR	X9, [X21]

0x496d28 CSEL	X11, X22, X11, #11

0x496d2c MADD	X10, X22, X10, X11

0x496d30 SUB	X11, X15, X10

0x496d34 CMP	X11, #14

0x496d38 B.CC	496db4

0x496d3c ADD	X10, X12, X22,LSL #3

0x496d40 ADD	X12, X9, X15,LSL #3

0x496d44 ADD	X13, X9, X16,LSL #3

0x496d48 ADD	X10, X10, #8

0x496d4c CMP	X8, X12

0x496d50 CCMP	X13, X10, #2, #3

0x496d54 B.CC	496db4

0x496d58 AND	X12, X11, #8062

0x496d5c ADD	X13, X13, #16

0x496d60 MOVI	V0.2D, #0

0x496d64 MOVI	V1.2D, #0

0x496d68 ADD	X10, X16, X12

0x496d6c ORR	X14, XZR, X12

0x496d70 HINT	#0

0x496d74 HINT	#0

0x496d78 HINT	#0

0x496d7c HINT	#0

(3370) 0x496d80 LDP	Q2, Q3, [X13, #2032]

(3370) 0x496d84 ADD	X13, X13, #32

(3370) 0x496d88 SUBS	X14, X14, #4

(3370) 0x496d8c ADD	V1.2D, V1.2D, V3.2D

(3370) 0x496d90 ADD	V0.2D, V0.2D, V2.2D

(3370) 0x496d94 B.NE	496d80

0x496d98 ADD	V0.2D, V1.2D, V0.2D

0x496d9c ADDP	D0, V0.2D

0x496da0 FMOV	X13, D0

0x496da4 STR	D0, [X8]

0x496da8 CMP	X11, X12

0x496dac B.NE	496dc0

0x496db0 B	496dd8

0x496db4 ORR	X13, XZR, XZR

0x496db8 ORR	X10, XZR, X16

0x496dbc HINT	#0

(3369) 0x496dc0 LDR	X11, [X9, X10,LSL #3]

(3369) 0x496dc4 ADD	X10, X10, #1

(3369) 0x496dc8 ADD	X13, X13, X11

(3369) 0x496dcc STR	X13, [X8]

(3369) 0x496dd0 CMP	X10, X15

(3369) 0x496dd4 B.LT	496dc0

0x496dd8 LDR	W25, [X25]

0x496ddc ADRP	X0,

0x496de0 ADD	X0, X0, #3752

0x496de4 ORR	X19, XZR, X16

0x496de8 STUR	X15, [X29, #416]

0x496dec ORR	W1, WZR, W25

0x496df0 BL	40f440

0x496df4 CBNZ	X22, 496e40

0x496df8 LDR	X8, [X24]

0x496dfc CMP	X8, #1

0x496e00 B.LT	496e40

0x496e04 LDR	X8, [X23]

0x496e08 ORR	X10, XZR, XZR

0x496e0c LDR	X9, [X8], #8

0x496e10 HINT	#0

0x496e14 HINT	#0

0x496e18 HINT	#0

0x496e1c HINT	#0

(3368) 0x496e20 LDR	X11, [X8, X10,LSL #3]

(3368) 0x496e24 ADD	X9, X11, X9

(3368) 0x496e28 ADD	X11, X10, #1

(3368) 0x496e2c STR	X9, [X8, X10,LSL #3]

(3368) 0x496e30 ORR	X10, XZR, X11

(3368) 0x496e34 LDR	X12, [X24]

(3368) 0x496e38 CMP	X11, X12

(3368) 0x496e3c B.LT	496e20

0x496e40 ADRP	X0,

0x496e44 ADD	X0, X0, #3776

0x496e48 ORR	W1, WZR, W25

0x496e4c BL	40f440

0x496e50 CBZ	X22, 496e64

0x496e54 LDR	X8, [X23]

0x496e58 ADD	X8, X8, X22,LSL #3

0x496e5c LDUR	X24, [X8, #504]

0x496e60 B	496e68

0x496e64 ORR	X24, XZR, XZR

0x496e68 LDUR	X23, [X29, #400]

0x496e6c LDUR	X7, [X29, #416]

0x496e70 ORR	X30, XZR, X19

0x496e74 CMP	X19, X7

0x496e78 B.GE	497620

0x496e7c LDP	X26, X8, [X29, #248]

0x496e80 LDP	X4, X19, [X29, #264]

0x496e84 MOVN	X27, #0

0x496e88 STUR	X21, [X29, #392]

0x496e8c STR	X28, [SP, #88]

0x496e90 STP	X8, XZR, [X29, #952]

0x496e94 LDR	X8, [X29, #240]

0x496e98 STP	X26, X4, [SP, #120]

0x496e9c STR	X8, [SP, #64]

0x496ea0 LDR	X8, [X29, #232]

0x496ea4 STR	X8, [SP, #56]

0x496ea8 LDR	X8, [X29, #224]

0x496eac STR	X8, [SP, #16]

0x496eb0 LDR	X8, [X29, #216]

0x496eb4 STR	X8, [SP, #8]

0x496eb8 LDR	X8, [X29, #208]

0x496ebc STR	X8, [SP, #48]

0x496ec0 LDR	X8, [X29, #200]

0x496ec4 STR	X8, [SP, #40]

0x496ec8 LDP	X8, X9, [X29, #184]

0x496ecc STP	X8, X9, [X29, #984]

0x496ed0 LDR	X8, [X29, #176]

0x496ed4 STR	X8, [SP, #32]

0x496ed8 LDR	X8, [X29, #168]

0x496edc STR	X8, [SP, #24]

0x496ee0 LDP	X8, X9, [X29, #152]

0x496ee4 STR	X8, [SP, #80]

0x496ee8 LDP	X8, X5, [X29, #136]

0x496eec STUR	X9, [X29, #456]

0x496ef0 STUR	X8, [X29, #432]

0x496ef4 LDR	X8, [X29, #128]

0x496ef8 STUR	X5, [X29, #488]

0x496efc STR	X8, [SP, #104]

0x496f00 LDR	X8, [X29, #120]

0x496f04 STR	X8, [SP, #96]

0x496f08 LDP	X8, X9, [X29, #104]

0x496f0c STR	X8, [SP, #112]

0x496f10 LDR	X8, [X29, #96]

0x496f14 STUR	X9, [X29, #408]

0x496f18 STUR	X8, [X29, #464]

0x496f1c B	496f50

      (3354) 0x496f20 ORR	X21, XZR, X9

      (3354) 0x496f24 ORR	X26, XZR, X8

      (3354) 0x496f28 LDUR	X8, [X29, #456]

      (3354) 0x496f2c LDR	X8, [X8]

      (3354) 0x496f30 LDP	X9, X8, [X8, #56]

      (3354) 0x496f34 STR	X21, [X9, X6,LSL #3]

      (3354) 0x496f38 STR	X26, [X8, X6,LSL #3]

      (3354) 0x496f3c LDUR	X21, [X29, #392]

      (3354) 0x496f40 LDP	X26, X4, [SP, #120]

      (3354) 0x496f44 ADD	X30, X30, #1

      (3354) 0x496f48 CMP	X30, X7

      (3354) 0x496f4c B.GE	497620

      (3354) 0x496f50 LDR	X8, [X23]

      (3354) 0x496f54 LDUR	X9, [X29, #464]

      (3354) 0x496f58 LDR	X25, [X8, X30,LSL #3]

      (3354) 0x496f5c LDR	X8, [X21]

      (3354) 0x496f60 LDR	X9, [X9]

      (3354) 0x496f64 LDR	X20, [X8, X30,LSL #3]

      (3354) 0x496f68 LDR	X8, [X28]

      (3354) 0x496f6c ADD	X8, X8, X9,LSL #3

      (3354) 0x496f70 LDR	X9, [X8]

      (3354) 0x496f74 SUBS	X6, X25, X9

      (3354) 0x496f78 B.LT	49700c

      (3354) 0x496f7c LDR	X8, [X8, #8]

      (3354) 0x496f80 CMP	X25, X8

      (3354) 0x496f84 B.GE	49700c

      (3354) 0x496f88 LDR	X8, [SP, #112]

      (3354) 0x496f8c STUR	X6, [X29, #496]

      (3354) 0x496f90 LDR	X8, [X8]

      (3354) 0x496f94 CBZ	X8, 497134

    (3361) 0x496f98 LDUR	X8, [X29, #408]

    (3361) 0x496f9c STUR	X30, [X29, #424]

    (3361) 0x496fa0 LDR	X8, [X8]

    (3361) 0x496fa4 LDR	X21, [X8, X6,LSL #3]

    (3361) 0x496fa8 LDR	X8, [SP, #96]

    (3361) 0x496fac LDR	X8, [X8]

    (3361) 0x496fb0 LDR	X23, [X8, X6,LSL #3]

    (3361) 0x496fb4 LDR	X8, [SP, #104]

    (3361) 0x496fb8 LDR	X8, [X8]

    (3361) 0x496fbc LDR	X16, [X8, X6,LSL #3]

    (3361) 0x496fc0 LDUR	X8, [X29, #432]

    (3361) 0x496fc4 LDR	X8, [X8]

    (3361) 0x496fc8 LDR	X26, [X8, X6,LSL #3]

    (3361) 0x496fcc SUB	X8, X16, X26

    (3361) 0x496fd0 SUBS	X25, X20, X8

    (3361) 0x496fd4 B.LE	497274

    (3361) 0x496fd8 MOVZ	W1, #8

    (3361) 0x496fdc ORR	X0, XZR, X25

    (3361) 0x496fe0 STUR	X16, [X29, #448]

    (3361) 0x496fe4 BL	4a6c90

    (3361) 0x496fe8 MOVZ	W1, #8

    (3361) 0x496fec ORR	X28, XZR, X0

    (3361) 0x496ff0 ORR	X0, XZR, X25

    (3361) 0x496ff4 BL	4a6c90

    (3361) 0x496ff8 LDUR	X16, [X29, #448]

    (3361) 0x496ffc ORR	X1, XZR, X28

    (3361) 0x497000 LDR	X28, [SP, #88]

    (3361) 0x497004 LDP	X5, X6, [X29, #1000]

    (3361) 0x497008 B	49727c

      (3354) 0x49700c LDUR	X8, [X29, #456]

      (3354) 0x497010 LDR	X12, [X26]

      (3354) 0x497014 ADD	X24, X20, X24

      (3354) 0x497018 LDR	X8, [X8]

      (3354) 0x49701c CMP	X8, #0

      (3354) 0x497020 CCMP	X12, #1, #8, #1

      (3354) 0x497024 B.LT	496f44

      (3354) 0x497028 LDUR	X10, [X29, #440]

      (3354) 0x49702c ORR	X8, XZR, XZR

      (3354) 0x497030 ORR	X9, XZR, XZR

      (3354) 0x497034 LDR	X10, [X10]

      (3354) 0x497038 B	497054

0x49703c HINT	#0

        (3355) 0x497040 LDR	X12, [X26]

        (3355) 0x497044 ADD	X8, X11, X8

        (3355) 0x497048 ADD	X9, X9, #2

        (3355) 0x49704c CMP	X9, X12

        (3355) 0x497050 B.GE	496f44

        (3355) 0x497054 ADD	X13, X10, X9,LSL #3

        (3355) 0x497058 LDP	X13, X11, [X13]

        (3355) 0x49705c CMP	X13, X25

        (3355) 0x497060 CCMP	X20, #1, #8, #0

        (3355) 0x497064 B.LT	497044

        (3355) 0x497068 LDR	X13, [X4]

        (3355) 0x49706c LDR	X14, [X5]

        (3355) 0x497070 AND	X15, X11, #8063

        (3355) 0x497074 ORR	X12, XZR, XZR

        (3355) 0x497078 ADD	X16, X13, X8,LSL #3

        (3355) 0x49707c ADD	X16, X16, #8

        (3355) 0x497080 B	497090

          (3356) 0x497084 ADD	X12, X12, #1

          (3356) 0x497088 CMP	X12, X20

          (3356) 0x49708c B.EQ	497040

          (3356) 0x497090 CMP	X11, #1

          (3356) 0x497094 B.LT	497084

          (3356) 0x497098 LDR	X17, [X19]

          (3356) 0x49709c ORR	X18, XZR, X8

          (3356) 0x4970a0 B.NE	4970cc

          (3356) 0x4970a4 TBZ	W11, #0, 497084

          (3356) 0x4970a8 LDR	X0, [X13, X18,LSL #3]

          (3356) 0x4970ac LDR	X1, [X14, X12,LSL #3]

          (3356) 0x4970b0 CMP	X0, X1

          (3356) 0x4970b4 B.NE	497084

          (3356) 0x4970b8 STR	X27, [X13, X18,LSL #3]

          (3356) 0x4970bc LDR	X18, [X17, X22,LSL #3]

          (3356) 0x4970c0 ADD	X18, X18, #1

          (3356) 0x4970c4 STR	X18, [X17, X22,LSL #3]

          (3356) 0x4970c8 B	497084

          (3356) 0x4970cc ORR	X0, XZR, X15

          (3356) 0x4970d0 ORR	X1, XZR, X16

          (3356) 0x4970d4 ORR	X18, XZR, X8

          (3356) 0x4970d8 B	4970f0

0x4970dc HINT	#0

            (3357) 0x4970e0 ADD	X18, X18, #2

            (3357) 0x4970e4 ADD	X1, X1, #16

            (3357) 0x4970e8 SUBS	X0, X0, #2

            (3357) 0x4970ec B.EQ	4970a4

            (3357) 0x4970f0 LDUR	X2, [X1, #504]

            (3357) 0x4970f4 LDR	X3, [X14, X12,LSL #3]

            (3357) 0x4970f8 CMP	X2, X3

            (3357) 0x4970fc B.NE	497110

            (3357) 0x497100 STUR	X27, [X1, #504]

            (3357) 0x497104 LDR	X2, [X17, X22,LSL #3]

            (3357) 0x497108 ADD	X2, X2, #1

            (3357) 0x49710c STR	X2, [X17, X22,LSL #3]

            (3357) 0x497110 LDR	X2, [X1]

            (3357) 0x497114 LDR	X3, [X14, X12,LSL #3]

            (3357) 0x497118 CMP	X2, X3

            (3357) 0x49711c B.NE	4970e0

            (3357) 0x497120 STR	X27, [X1]

            (3357) 0x497124 LDR	X2, [X17, X22,LSL #3]

            (3357) 0x497128 ADD	X2, X2, #1

            (3357) 0x49712c STR	X2, [X17, X22,LSL #3]

            (3357) 0x497130 B	4970e0

      (3354) 0x497134 LDUR	X8, [X29, #456]

      (3354) 0x497138 UBFM	X12, X6, #61, #60

      (3354) 0x49713c LDR	X8, [X8]

      (3354) 0x497140 LDP	X10, X9, [X8, #56]

      (3354) 0x497144 LDR	X8, [X9, X12]

      (3354) 0x497148 LDR	X9, [X10, X12]

      (3354) 0x49714c CMP	X20, #1

      (3354) 0x497150 B.LT	496f20

      (3354) 0x497154 LDP	X11, X13, [SP, #24]

      (3354) 0x497158 LDP	X16, X18, [SP, #56]

      (3354) 0x49715c LDR	X17, [SP, #80]

      (3354) 0x497160 ADD	X14, X12, #8

      (3354) 0x497164 ORR	X10, XZR, XZR

      (3354) 0x497168 ORR	X26, XZR, X8

      (3354) 0x49716c ORR	X21, XZR, X9

      (3354) 0x497170 LDP	X0, X1, [SP, #40]

      (3354) 0x497174 LDR	X15, [X5]

      (3354) 0x497178 LDR	X11, [X11]

      (3354) 0x49717c LDR	X13, [X13]

      (3354) 0x497180 LDR	X16, [X16]

      (3354) 0x497184 LDR	X17, [X17]

      (3354) 0x497188 LDR	X18, [X18]

      (3354) 0x49718c LDR	X0, [X0]

      (3354) 0x497190 LDR	X1, [X1]

      (3354) 0x497194 LDR	X12, [X11, X14]

      (3354) 0x497198 LDR	X14, [X13, X14]

      (3354) 0x49719c B	4971bc

        (3358) 0x4971a0 LDR	D0, [X17, X24,LSL #3]

        (3358) 0x4971a4 STR	D0, [X4]

        (3358) 0x4971a8 LDP	X5, X6, [X29, #1000]

        (3358) 0x4971ac ADD	X24, X24, #1

        (3358) 0x4971b0 ADD	X10, X10, #1

        (3358) 0x4971b4 CMP	X10, X20

        (3358) 0x4971b8 B.EQ	496f28

        (3358) 0x4971bc LDP	X3, X4, [X29, #984]

        (3358) 0x4971c0 LDR	X2, [X15, X24,LSL #3]

        (3358) 0x4971c4 LDR	X3, [X3]

        (3358) 0x4971c8 LDR	X4, [X4]

        (3358) 0x4971cc CMP	X2, X3

        (3358) 0x4971d0 CCMP	X2, X4, #0, #10

        (3358) 0x4971d4 B.LE	497220

        (3358) 0x4971d8 LDR	X5, [X13, X6,LSL #3]

        (3358) 0x4971dc SUBS	X3, X8, X5

        (3358) 0x4971e0 B.LE	497204

        (3358) 0x4971e4 ADD	X4, X1, X5,LSL #3

        (3358) 0x4971e8 ADD	X5, X0, X5,LSL #3

          (3360) 0x4971ec LDR	X6, [X5], #8

          (3360) 0x4971f0 CMP	X6, X2

          (3360) 0x4971f4 B.EQ	4971a0

          (3360) 0x4971f8 ADD	X4, X4, #8

          (3360) 0x4971fc SUBS	X3, X3, #1

          (3360) 0x497200 B.NE	4971ec

        (3358) 0x497204 CMP	X26, X14

        (3358) 0x497208 B.GE	4974e0

        (3358) 0x49720c LDR	D0, [X17, X24,LSL #3]

        (3358) 0x497210 STR	X2, [X0, X26,LSL #3]

        (3358) 0x497214 STR	D0, [X1, X26,LSL #3]

        (3358) 0x497218 ADD	X26, X26, #1

        (3358) 0x49721c B	4971a8

        (3358) 0x497220 LDR	X5, [X11, X6,LSL #3]

        (3358) 0x497224 SUBS	X3, X9, X5

        (3358) 0x497228 B.LE	497258

        (3358) 0x49722c ADD	X4, X18, X5,LSL #3

        (3358) 0x497230 ADD	X5, X16, X5,LSL #3

        (3358) 0x497234 HINT	#0

        (3358) 0x497238 HINT	#0

        (3358) 0x49723c HINT	#0

          (3359) 0x497240 LDR	X6, [X5], #8

          (3359) 0x497244 CMP	X6, X2

          (3359) 0x497248 B.EQ	4971a0

          (3359) 0x49724c ADD	X4, X4, #8

          (3359) 0x497250 SUBS	X3, X3, #1

          (3359) 0x497254 B.NE	497240

        (3358) 0x497258 CMP	X21, X12

        (3358) 0x49725c B.GE	497510

        (3358) 0x497260 LDR	D0, [X17, X24,LSL #3]

        (3358) 0x497264 STR	X2, [X16, X21,LSL #3]

        (3358) 0x497268 STR	D0, [X18, X21,LSL #3]

        (3358) 0x49726c ADD	X21, X21, #1

        (3358) 0x497270 B	4971a8

    (3361) 0x497274 LDUR	X0, [X29, #448]

    (3361) 0x497278 ORR	X1, XZR, XZR

    (3361) 0x49727c STUR	X0, [X29, #448]

    (3361) 0x497280 CMP	X20, #0

    (3361) 0x497284 B.LE	497428

  (3362) 0x497288 LDR	X10, [SP, #80]

  (3362) 0x49728c LDR	X9, [X5]

  (3362) 0x497290 ORR	X25, XZR, XZR

  (3362) 0x497294 ORR	X8, XZR, XZR

  (3362) 0x497298 ORR	X28, XZR, X26

  (3362) 0x49729c LDR	X10, [X10]

  (3362) 0x4972a0 B	4972c4

  (3362) 0x4972a4 LDR	D0, [X10, X24,LSL #3]

  (3362) 0x4972a8 STR	X11, [X1, X25,LSL #3]

  (3362) 0x4972ac STR	D0, [X0, X25,LSL #3]

  (3362) 0x4972b0 ADD	X25, X25, #1

  (3362) 0x4972b4 ADD	X24, X24, #1

  (3362) 0x4972b8 ADD	X8, X8, #1

  (3362) 0x4972bc CMP	X8, X20

  (3362) 0x4972c0 B.EQ	49732c

  (3362) 0x4972c4 CMP	X26, #1

  (3362) 0x4972c8 B.LT	4972f8

(3363) 0x4972cc LDR	X11, [X9, X24,LSL #3]

(3363) 0x4972d0 ORR	X13, XZR, X26

(3363) 0x4972d4 ORR	X14, XZR, X21

(3363) 0x4972d8 ORR	X12, XZR, X23

(3363) 0x4972dc HINT	#0

  (3364) 0x4972e0 LDR	X15, [X14], #8

  (3364) 0x4972e4 CMP	X15, X11

  (3364) 0x4972e8 B.EQ	497320

  (3364) 0x4972ec ADD	X12, X12, #8

  (3364) 0x4972f0 SUBS	X13, X13, #1

  (3364) 0x4972f4 B.NE	4972e0

  (3362) 0x4972f8 LDR	X11, [X9, X24,LSL #3]

  (3362) 0x4972fc CMP	X28, X16

  (3362) 0x497300 B.GE	4972a4

  (3362) 0x497304 LDR	D0, [X10, X24,LSL #3]

  (3362) 0x497308 STR	X11, [X21, X28,LSL #3]

  (3362) 0x49730c STR	D0, [X23, X28,LSL #3]

  (3362) 0x497310 ADD	X28, X28, #1

  (3362) 0x497314 B	4972b4

0x497318 HINT	#0

0x49731c HINT	#0

(3363) 0x497320 LDR	D0, [X10, X24,LSL #3]

(3363) 0x497324 STR	D0, [X12]

(3363) 0x497328 B	4972b4

  (3362) 0x49732c LDUR	X8, [X29, #432]

  (3362) 0x497330 ADD	X21, X28, X25

  (3362) 0x497334 LDR	X8, [X8]

  (3362) 0x497338 STR	X21, [X8, X6,LSL #3]

  (3362) 0x49733c CBZ	X25, 497438

  (3362) 0x497340 LDUR	X23, [X29, #408]

  (3362) 0x497344 UBFM	X20, X21, #61, #60

  (3362) 0x497348 STR	X1, [SP, #72]

  (3362) 0x49734c ORR	X1, XZR, X20

  (3362) 0x497350 LDR	X8, [X23]

  (3362) 0x497354 LDR	X0, [X8, X6,LSL #3]

  (3362) 0x497358 BL	4a6d00

  (3362) 0x49735c LDR	X8, [X23]

  (3362) 0x497360 LDUR	X9, [X29, #496]

  (3362) 0x497364 LDR	X23, [SP, #96]

  (3362) 0x497368 ORR	X1, XZR, X20

  (3362) 0x49736c STR	X0, [X8, X9,LSL #3]

  (3362) 0x497370 LDUR	X9, [X29, #496]

  (3362) 0x497374 LDR	X8, [X23]

  (3362) 0x497378 LDR	X0, [X8, X9,LSL #3]

  (3362) 0x49737c BL	4a6d00

  (3362) 0x497380 LDUR	X10, [X29, #496]

  (3362) 0x497384 LDR	X8, [X23]

  (3362) 0x497388 ORR	X9, XZR, X23

  (3362) 0x49738c LDUR	X23, [X29, #400]

  (3362) 0x497390 LDR	X26, [SP, #120]

  (3362) 0x497394 STR	X0, [X8, X10,LSL #3]

  (3362) 0x497398 LDR	X8, [SP, #104]

  (3362) 0x49739c LDR	X8, [X8]

  (3362) 0x4973a0 STR	X21, [X8, X10,LSL #3]

  (3362) 0x4973a4 CMP	X25, #1

  (3362) 0x4973a8 B.LT	49744c

  (3362) 0x4973ac LDUR	X8, [X29, #408]

  (3362) 0x4973b0 LDR	X9, [X9]

  (3362) 0x4973b4 LDUR	X21, [X29, #392]

  (3362) 0x4973b8 LDUR	X18, [X29, #448]

  (3362) 0x4973bc LDR	X1, [SP, #72]

  (3362) 0x4973c0 LDR	X8, [X8]

  (3362) 0x4973c4 LDR	X9, [X9, X10,LSL #3]

  (3362) 0x4973c8 LDR	X8, [X8, X10,LSL #3]

  (3362) 0x4973cc ORR	X10, XZR, XZR

  (3362) 0x4973d0 CMP	X25, #4

  (3362) 0x4973d4 B.CS	497464

  (3362) 0x4973d8 ANDS	X12, X25, #4160

  (3362) 0x4973dc B.EQ	497564

  (3362) 0x4973e0 ADD	X13, X9, X28,LSL #3

  (3362) 0x4973e4 ADD	X14, X8, X28,LSL #3

  (3362) 0x4973e8 ADD	X15, X18, X10,LSL #3

  (3362) 0x4973ec ADD	X16, X1, X10,LSL #3

  (3362) 0x4973f0 ORR	X11, XZR, XZR

  (3362) 0x4973f4 HINT	#0

  (3362) 0x4973f8 HINT	#0

  (3362) 0x4973fc HINT	#0

    (3366) 0x497400 LDR	D0, [X15, X11,LSL #3]

    (3366) 0x497404 LDR	X17, [X16, X11,LSL #3]

    (3366) 0x497408 STR	X17, [X14, X11,LSL #3]

    (3366) 0x49740c STR	D0, [X13, X11,LSL #3]

    (3366) 0x497410 ADD	X11, X11, #1

    (3366) 0x497414 CMP	X12, X11

    (3366) 0x497418 B.NE	497400

  (3362) 0x49741c ADD	X28, X28, X11

  (3362) 0x497420 ADD	X12, X10, X11

  (3362) 0x497424 B	497568

    (3361) 0x497428 LDUR	X8, [X29, #432]

    (3361) 0x49742c LDR	X8, [X8]

    (3361) 0x497430 STR	X26, [X8, X6,LSL #3]

    (3361) 0x497434 B	49743c

  (3362) 0x497438 LDR	X28, [SP, #88]

    (3361) 0x49743c LDP	X21, X23, [X29, #904]

    (3361) 0x497440 LDR	X26, [SP, #120]

    (3361) 0x497444 CBNZ	X1, 4975fc

    (3361) 0x497448 B	497614

  (3362) 0x49744c LDR	X28, [SP, #88]

  (3362) 0x497450 LDUR	X21, [X29, #392]

  (3362) 0x497454 LDUR	X5, [X29, #488]

  (3362) 0x497458 LDR	X1, [SP, #72]

  (3362) 0x49745c CBNZ	X1, 4975fc

  (3362) 0x497460 B	497614

  (3362) 0x497464 SUB	X11, X8, X1

  (3362) 0x497468 ADD	X11, X11, X28,LSL #3

  (3362) 0x49746c CMP	X11, #32

  (3362) 0x497470 B.CC	4973d8

  (3362) 0x497474 SUB	X11, X9, X18

  (3362) 0x497478 ADD	X11, X11, X28,LSL #3

  (3362) 0x49747c CMP	X11, #32

  (3362) 0x497480 B.CC	4973d8

  (3362) 0x497484 UBFM	X14, X28, #61, #60

  (3362) 0x497488 AND	X10, X25, #7998

  (3362) 0x49748c ADD	X11, X1, #16

  (3362) 0x497490 ADD	X13, X18, #16

  (3362) 0x497494 ADD	X12, X9, X14

  (3362) 0x497498 ADD	X14, X8, X14

  (3362) 0x49749c ADD	X28, X28, X10

  (3362) 0x4974a0 ORR	X15, XZR, X10

  (3362) 0x4974a4 ADD	X12, X12, #16

  (3362) 0x4974a8 ADD	X14, X14, #16

    (3367) 0x4974ac LDP	Q0, Q1, [X11, #2032]

    (3367) 0x4974b0 ADD	X11, X11, #32

    (3367) 0x4974b4 SUBS	X15, X15, #4

    (3367) 0x4974b8 STP	Q0, Q1, [X14, #2032]

    (3367) 0x4974bc LDP	Q0, Q1, [X13, #2032]

    (3367) 0x4974c0 ADD	X13, X13, #32

    (3367) 0x4974c4 ADD	X14, X14, #32

    (3367) 0x4974c8 STP	Q0, Q1, [X12, #2032]

    (3367) 0x4974cc ADD	X12, X12, #32

    (3367) 0x4974d0 B.NE	4974ac

  (3362) 0x4974d4 CMP	X25, X10

  (3362) 0x4974d8 B.NE	4973d8

  (3362) 0x4974dc B	4975f8

      (3354) 0x4974e0 ADRP	X0,

      (3354) 0x4974e4 ADD	X0, X0, #1111

      (3354) 0x4974e8 MOVZ	W1, #3406

      (3354) 0x4974ec MOVZ	W2, #1

      (3354) 0x4974f0 ORR	X20, XZR, X30

      (3354) 0x4974f4 ORR	X3, XZR, XZR

      (3354) 0x4974f8 BL	4a9360

      (3354) 0x4974fc LDR	X8, [SP, #8]

      (3354) 0x497500 MOVZ	W9, #1

      (3354) 0x497504 ADRP	X0,

      (3354) 0x497508 ADD	X0, X0, #1452

      (3354) 0x49750c B	49753c

      (3354) 0x497510 ADRP	X0,

      (3354) 0x497514 ADD	X0, X0, #1111

      (3354) 0x497518 MOVZ	W1, #3440

      (3354) 0x49751c MOVZ	W2, #1

      (3354) 0x497520 ORR	X20, XZR, X30

      (3354) 0x497524 ORR	X3, XZR, XZR

      (3354) 0x497528 BL	4a9360

      (3354) 0x49752c LDR	X8, [SP, #8]

      (3354) 0x497530 MOVZ	W9, #1

      (3354) 0x497534 ADRP	X0,

      (3354) 0x497538 ADD	X0, X0, #1490

      (3354) 0x49753c LDADD	X9, X8, [X8]

      (3354) 0x497540 LDR	X8, [SP, #16]

      (3354) 0x497544 LDR	X8, [X8]

      (3354) 0x497548 CBZ	X8, 497554

      (3354) 0x49754c ORR	X1, XZR, X25

      (3354) 0x497550 BL	4a6ee0

      (3354) 0x497554 LDUR	X7, [X29, #416]

      (3354) 0x497558 LDP	X5, X6, [X29, #1000]

      (3354) 0x49755c ORR	X30, XZR, X20

      (3354) 0x497560 B	496f28

  (3362) 0x497564 ORR	X12, XZR, X10

  (3362) 0x497568 SUB	X10, X10, X25

  (3362) 0x49756c CMN	X10, #4

  (3362) 0x497570 B.HI	4975f8

  (3362) 0x497574 ADD	X10, X1, X12,LSL #3

  (3362) 0x497578 ADD	X11, X18, X12,LSL #3

  (3362) 0x49757c ADD	X9, X9, X28,LSL #3

  (3362) 0x497580 ADD	X8, X8, X28,LSL #3

  (3362) 0x497584 SUB	X12, X25, X12

  (3362) 0x497588 ADD	X10, X10, #16

  (3362) 0x49758c ADD	X11, X11, #16

  (3362) 0x497590 ADD	X9, X9, #16

  (3362) 0x497594 ADD	X8, X8, #16

  (3362) 0x497598 HINT	#0

  (3362) 0x49759c HINT	#0

    (3365) 0x4975a0 LDUR	D0, [X11, #496]

    (3365) 0x4975a4 LDUR	X13, [X10, #496]

    (3365) 0x4975a8 SUBS	X12, X12, #4

    (3365) 0x4975ac STUR	X13, [X8, #496]

    (3365) 0x4975b0 LDUR	X13, [X10, #504]

    (3365) 0x4975b4 STUR	D0, [X9, #496]

    (3365) 0x4975b8 LDUR	D0, [X11, #504]

    (3365) 0x4975bc STUR	X13, [X8, #504]

    (3365) 0x4975c0 LDR	X13, [X10]

    (3365) 0x4975c4 STUR	D0, [X9, #504]

    (3365) 0x4975c8 LDR	D0, [X11]

    (3365) 0x4975cc STR	X13, [X8]

    (3365) 0x4975d0 LDR	X13, [X10, #8]

    (3365) 0x4975d4 ADD	X10, X10, #32

    (3365) 0x4975d8 STR	X13, [X8, #8]

    (3365) 0x4975dc ADD	X8, X8, #32

    (3365) 0x4975e0 STR	D0, [X9]

    (3365) 0x4975e4 LDR	D0, [X11, #8]

    (3365) 0x4975e8 ADD	X11, X11, #32

    (3365) 0x4975ec STR	D0, [X9, #8]

    (3365) 0x4975f0 ADD	X9, X9, #32

    (3365) 0x4975f4 B.NE	4975a0

  (3362) 0x4975f8 LDR	X28, [SP, #88]

    (3361) 0x4975fc ORR	X0, XZR, X1

    (3361) 0x497600 BL	4a6d90

    (3361) 0x497604 LDUR	X0, [X29, #448]

    (3361) 0x497608 BL	4a6d90

    (3361) 0x49760c LDUR	X5, [X29, #488]

    (3361) 0x497610 STUR	XZR, [X29, #448]

    (3361) 0x497614 LDP	X7, X30, [X29, #928]

    (3361) 0x497618 LDR	X4, [SP, #128]

    (3361) 0x49761c B	496f44

0x497620 LDP	X20, X19, [SP, #336]

0x497624 LDP	X22, X21, [SP, #320]

0x497628 LDP	X24, X23, [SP, #304]

0x49762c LDP	X26, X25, [SP, #288]

0x497630 LDP	X28, X27, [SP, #272]

0x497634 LDP	X29, X30, [SP, #256]

0x497638 ADD	SP, SP, #352

0x49763c RET

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3352,3359-3368,3376-3377,3383-3390,3399-3410,3417-3424,3433-3444,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.00 to 1.00 cycles (22.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 22.00 to 17.58 cycles (1.25x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
7% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.00 to 2.00 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 364 bytes. The binary function is storing 328 bytes.

General properties

nb instructions	156
loop length	624
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.00	8.00	10.17	10.17	10.17	10.17	10.17	10.17	1.50	1.50	1.50	1.50	22.00	22.00	22.00	15.50	15.50
cycles	8.00	8.00	10.17	10.17	10.17	10.17	10.17	10.17	1.50	1.50	1.50	1.50	22.00	22.00	22.00	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	17.88
Overall L1	22.00

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

17% of peak load performance is reached (16.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (14.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 496c90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X6, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X10, X8, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD X13, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MSUB X11, X10, X27, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X8, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X10, X8, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X8, X13, X8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X9, X10, X0, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X14, X13, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X0, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X15, X12, X8, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CSEL X16, X9, X14, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X12, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X16, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 496dd8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CSEL X11, X22, X11, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X10, X22, X10, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
SUB X11, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X11, #14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 496db4 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X12, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X9, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X9, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X13, X10, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 496db4 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X12, X11, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X16, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X14, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADDP D0, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMOV X13, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X11, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 496dc0 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 496dd8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4deddc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X15, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 496e40 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 496e40 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X8], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <4dee40>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3776	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X22, 496e64 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 496e68 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X23, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X19, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 497620 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x990>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X26, X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MOVN X27, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X21, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, XZR, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X26, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X5, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X5, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 496f50 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
7% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.00 to 2.00 cycles (11.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 364 bytes. The binary function is storing 328 bytes.

General properties

nb instructions	156
loop length	624
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.00	8.00	10.17	10.17	10.17	10.17	10.17	10.17	1.50	1.50	1.50	1.50	22.00	22.00	22.00	15.50	15.50
cycles	8.00	8.00	10.17	10.17	10.17	10.17	10.17	10.17	1.50	1.50	1.50	1.50	22.00	22.00	22.00	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	17.88
Overall L1	22.00

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

17% of peak load performance is reached (16.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (14.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 496c90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X6, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X10, X8, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD X13, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MSUB X11, X10, X27, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X8, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X10, X8, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X8, X13, X8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X9, X10, X0, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X14, X13, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X0, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X15, X12, X8, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CSEL X16, X9, X14, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X12, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X16, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 496dd8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CSEL X11, X22, X11, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X10, X22, X10, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
SUB X11, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X11, #14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 496db4 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X12, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X9, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X9, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X13, X10, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 496db4 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X12, X11, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X16, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X14, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADDP D0, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMOV X13, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X11, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 496dc0 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 496dd8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4deddc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X15, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 496e40 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 496e40 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X8], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <4dee40>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3776	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X22, 496e64 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 496e68 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X23, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X19, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 497620 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x990>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X26, X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MOVN X27, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X21, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, XZR, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X26, X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X5, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X5, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 496f50 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15–	0.27	0.06
○Loop 3369 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00
○Loop 3368 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00
▼Loop 3363 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
○Loop 3364 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
▼Loop 3362 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
○Loop 3365 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 3361 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
▼Loop 3354 - IJMatrix_parcsr.c:3291-3484 - exec–	0.05	0.01
▼Loop 3358 - IJMatrix_parcsr.c:3383-3454 - exec–	0.22	0.03
○Loop 3359 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 3360 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
▼Loop 3355 - IJMatrix_parcsr.c:3470-3484 - exec–	0.00	0.00
▼Loop 3356 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 3357 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 3366 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3367 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3370 - IJMatrix_parcsr.c:3275-3275 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code