OV - exec - Function hypre_ParMatmul.omp

	Function: hypre_ParMatmul.omp_outlined.7	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 0.90% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x483990 SUB	SP, SP, #320

0x483994 STP	X29, X30, [SP, #224]

0x483998 STP	X28, X27, [SP, #240]

0x48399c STP	X26, X25, [SP, #256]

0x4839a0 STP	X24, X23, [SP, #272]

0x4839a4 STP	X22, X21, [SP, #288]

0x4839a8 STP	X20, X19, [SP, #304]

0x4839ac ADD	X29, SP, #224

0x4839b0 LDP	X8, X9, [X29, #288]

0x4839b4 STUR	X7, [X29, #424]

0x4839b8 STUR	X4, [X29, #480]

0x4839bc ORR	X19, XZR, X6

0x4839c0 ORR	X20, XZR, X5

0x4839c4 ORR	X22, XZR, X3

0x4839c8 ORR	X26, XZR, X2

0x4839cc STUR	X9, [X29, #456]

0x4839d0 STR	X8, [SP, #88]

0x4839d4 LDR	X8, [X29, #280]

0x4839d8 STR	X8, [SP, #80]

0x4839dc LDR	X8, [X29, #272]

0x4839e0 STR	X8, [SP, #72]

0x4839e4 LDP	X8, X28, [X29, #256]

0x4839e8 STUR	X8, [X29, #464]

0x4839ec LDR	X8, [X29, #248]

0x4839f0 STR	X8, [SP, #64]

0x4839f4 LDP	X27, X8, [X29, #232]

0x4839f8 STUR	X8, [X29, #472]

0x4839fc LDP	X8, X24, [X29, #216]

0x483a00 STR	X8, [SP, #40]

0x483a04 LDP	X8, X9, [X29, #200]

0x483a08 STUR	X9, [X29, #448]

0x483a0c STR	X8, [SP, #56]

0x483a10 LDR	X8, [X29, #192]

0x483a14 STR	X8, [SP, #32]

0x483a18 LDP	X8, X9, [X29, #176]

0x483a1c STUR	X8, [X29, #440]

0x483a20 LDP	X8, X10, [X29, #160]

0x483a24 STP	X10, X9, [X29, #1000]

0x483a28 STR	X8, [SP, #48]

0x483a2c LDR	X8, [X29, #152]

0x483a30 STR	X8, [SP, #24]

0x483a34 LDR	X8, [X29, #144]

0x483a38 STR	X8, [SP, #16]

0x483a3c LDR	X8, [X29, #136]

0x483a40 STR	X8, [SP, #8]

0x483a44 LDR	X8, [X29, #128]

0x483a48 STR	X8, [SP, #96]

0x483a4c LDP	X21, X9, [X29, #112]

0x483a50 LDP	X25, X8, [X29, #96]

0x483a54 STP	X8, X9, [X29, #920]

0x483a58 BL	4a8a10

0x483a5c ORR	X23, XZR, X0

0x483a60 BL	4a89f0

0x483a64 LDR	X8, [X26]

0x483a68 ADD	X10, X23, #1

0x483a6c ORR	X13, XZR, X19

0x483a70 SDIV	X9, X8, X0

0x483a74 MSUB	X8, X9, X0, X8

0x483a78 MADD	X11, X9, X23, X8

0x483a7c CMP	X23, X8

0x483a80 MADD	X8, X9, X10, X8

0x483a84 ADD	X9, X9, #1

0x483a88 MADD	X12, X9, X23, XZR

0x483a8c MADD	X9, X10, X9, XZR

0x483a90 CSEL	X8, X8, X9, #10

0x483a94 CSEL	X26, X11, X12, #10

0x483a98 LDR	X9, [X13]

0x483a9c STUR	X8, [X29, #432]

0x483aa0 LDR	X8, [X22]

0x483aa4 LDR	X22, [X8, X26,LSL #3]

0x483aa8 LDUR	X8, [X29, #480]

0x483aac LDR	X8, [X8]

0x483ab0 LDR	X19, [X8, X26,LSL #3]

0x483ab4 LDR	X8, [X20]

0x483ab8 ORR	X10, X8, X9

0x483abc CBNZ	X10, 483acc

0x483ac0 LDUR	X9, [X29, #472]

0x483ac4 ORR	X0, XZR, XZR

0x483ac8 B	483b24

0x483acc STUR	X24, [X29, #480]

0x483ad0 LDUR	X24, [X29, #472]

0x483ad4 ADD	X0, X9, X8

0x483ad8 MOVZ	W1, #8

0x483adc ORR	X23, XZR, X13

0x483ae0 BL	4a6c90

0x483ae4 LDR	X8, [X20]

0x483ae8 LDR	X9, [X23]

0x483aec ADD	X8, X9, X8

0x483af0 CMP	X8, #1

0x483af4 B.LT	483b1c

0x483af8 MOVN	X9, #0

0x483afc ORR	X8, XZR, XZR

(2880) 0x483b00 STR	X9, [X0, X8,LSL #3]

(2880) 0x483b04 ADD	X8, X8, #1

(2880) 0x483b08 LDR	X10, [X20]

(2880) 0x483b0c LDR	X11, [X23]

(2880) 0x483b10 ADD	X10, X11, X10

(2880) 0x483b14 CMP	X8, X10

(2880) 0x483b18 B.LT	483b00

0x483b1c ORR	X9, XZR, X24

0x483b20 LDUR	X24, [X29, #480]

0x483b24 LDUR	X8, [X29, #432]

0x483b28 CMP	X26, X8

0x483b2c B.GE	483e80

0x483b30 LDR	X10, [X25]

0x483b34 LDR	X8, [X21]

0x483b38 LDR	X16, [X24]

0x483b3c ORR	X1, XZR, X22

0x483b40 LDR	X17, [X27]

0x483b44 LDR	X18, [X9]

0x483b48 STP	X8, X10, [SP, #104]

0x483b4c LDR	X8, [SP, #96]

0x483b50 LDR	X8, [X8]

0x483b54 STR	X8, [SP, #96]

0x483b58 LDR	X8, [SP, #8]

0x483b5c LDR	X8, [X8]

0x483b60 STUR	X8, [X29, #480]

0x483b64 LDR	X8, [SP, #16]

0x483b68 LDR	X8, [X8]

0x483b6c STUR	X8, [X29, #472]

0x483b70 LDP	X10, X8, [SP, #24]

0x483b74 LDR	X14, [X8]

0x483b78 LDR	X8, [SP, #40]

0x483b7c LDR	X13, [X10]

0x483b80 LDR	X15, [X8]

0x483b84 B	483b9c

      (2872) 0x483b88 LDUR	X8, [X29, #432]

      (2872) 0x483b8c ORR	X19, XZR, X2

      (2872) 0x483b90 ORR	X22, XZR, X1

      (2872) 0x483b94 CMP	X26, X8

      (2872) 0x483b98 B.GE	483e80

      (2872) 0x483b9c LDUR	X8, [X29, #424]

      (2872) 0x483ba0 LDR	X8, [X8]

      (2872) 0x483ba4 CBZ	X8, 483bc4

      (2872) 0x483ba8 LDUR	X8, [X29, #408]

      (2872) 0x483bac ADD	X1, X22, #1

      (2872) 0x483bb0 STR	X22, [X0, X26,LSL #3]

      (2872) 0x483bb4 LDR	D0, [X8]

      (2872) 0x483bb8 LDP	X8, X9, [SP, #104]

      (2872) 0x483bbc STR	X26, [X8, X22,LSL #3]

      (2872) 0x483bc0 STR	D0, [X9, X22,LSL #3]

      (2872) 0x483bc4 LDUR	X8, [X29, #416]

      (2872) 0x483bc8 LDR	X8, [X8]

      (2872) 0x483bcc CBZ	X8, 483d20

      (2872) 0x483bd0 LDR	X8, [SP, #96]

      (2872) 0x483bd4 ADD	X3, X8, X26,LSL #3

      (2872) 0x483bd8 LDP	X4, X8, [X3]

      (2872) 0x483bdc CMP	X4, X8

      (2872) 0x483be0 B.GE	483d20

      (2872) 0x483be4 LDP	X9, X8, [SP, #48]

      (2872) 0x483be8 ORR	X2, XZR, X19

      (2872) 0x483bec LDR	X5, [X9]

      (2872) 0x483bf0 LDR	X6, [X8]

      (2872) 0x483bf4 B	483c10

0x483bf8 HINT	#0

0x483bfc HINT	#0

        (2877) 0x483c00 LDR	X8, [X3, #8]

        (2877) 0x483c04 ADD	X4, X4, #1

        (2877) 0x483c08 CMP	X4, X8

        (2877) 0x483c0c B.GE	483d24

        (2877) 0x483c10 LDP	X8, X9, [X29, #984]

        (2877) 0x483c14 LDR	X30, [X9, X4,LSL #3]

        (2877) 0x483c18 LDR	D0, [X8, X4,LSL #3]

        (2877) 0x483c1c ADD	X7, X30, #1

        (2877) 0x483c20 LDR	X8, [X13, X30,LSL #3]

        (2877) 0x483c24 LDR	X23, [X13, X7,LSL #3]

        (2877) 0x483c28 CMP	X8, X23

        (2877) 0x483c2c B.GE	483ca4

        (2877) 0x483c30 LDUR	X9, [X29, #440]

        (2877) 0x483c34 LDP	X10, X11, [X29, #1000]

        (2877) 0x483c38 LDR	X9, [X9]

        (2877) 0x483c3c LDR	X10, [X10]

        (2877) 0x483c40 LDR	X27, [X11]

        (2877) 0x483c44 B	483c64

          (2879) 0x483c48 LDR	D1, [X9, X8,LSL #3]

          (2879) 0x483c4c LDR	D2, [X10, X11,LSL #3]

          (2879) 0x483c50 FMADD	D1, D1, D0, D2

          (2879) 0x483c54 STR	D1, [X10, X11,LSL #3]

          (2879) 0x483c58 ADD	X8, X8, #1

          (2879) 0x483c5c CMP	X8, X23

          (2879) 0x483c60 B.GE	483ca4

          (2879) 0x483c64 LDR	X11, [X20]

          (2879) 0x483c68 LDR	X12, [X5, X8,LSL #3]

          (2879) 0x483c6c ADD	X24, X12, X11

          (2879) 0x483c70 LDR	X11, [X0, X24,LSL #3]

          (2879) 0x483c74 CMP	X11, X19

          (2879) 0x483c78 B.GE	483c48

          (2879) 0x483c7c STR	X2, [X0, X24,LSL #3]

          (2879) 0x483c80 LDR	D1, [X9, X8,LSL #3]

          (2879) 0x483c84 LDR	X11, [X20]

          (2879) 0x483c88 SUB	X11, X24, X11

          (2879) 0x483c8c STR	X11, [X27, X2,LSL #3]

          (2879) 0x483c90 FMUL	D1, D1, D0

          (2879) 0x483c94 LDR	X23, [X13, X7,LSL #3]

          (2879) 0x483c98 STR	D1, [X10, X2,LSL #3]

          (2879) 0x483c9c ADD	X2, X2, #1

          (2879) 0x483ca0 B	483c58

        (2877) 0x483ca4 LDR	X8, [X14, X30,LSL #3]

        (2877) 0x483ca8 LDR	X23, [X14, X7,LSL #3]

        (2877) 0x483cac CMP	X8, X23

        (2877) 0x483cb0 B.GE	483c00

        (2877) 0x483cb4 LDUR	X9, [X29, #448]

        (2877) 0x483cb8 LDR	X10, [X25]

        (2877) 0x483cbc LDR	X27, [X21]

        (2877) 0x483cc0 LDR	X9, [X9]

        (2877) 0x483cc4 B	483ce4

          (2878) 0x483cc8 LDR	D1, [X9, X8,LSL #3]

          (2878) 0x483ccc LDR	D2, [X10, X11,LSL #3]

          (2878) 0x483cd0 FMADD	D1, D1, D0, D2

          (2878) 0x483cd4 STR	D1, [X10, X11,LSL #3]

          (2878) 0x483cd8 ADD	X8, X8, #1

          (2878) 0x483cdc CMP	X8, X23

          (2878) 0x483ce0 B.GE	483c00

          (2878) 0x483ce4 LDR	X24, [X6, X8,LSL #3]

          (2878) 0x483ce8 LDR	X11, [X0, X24,LSL #3]

          (2878) 0x483cec CMP	X11, X22

          (2878) 0x483cf0 B.GE	483cc8

          (2878) 0x483cf4 LDR	D1, [X9, X8,LSL #3]

          (2878) 0x483cf8 STR	X1, [X0, X24,LSL #3]

          (2878) 0x483cfc STR	X24, [X27, X1,LSL #3]

          (2878) 0x483d00 LDR	X23, [X14, X7,LSL #3]

          (2878) 0x483d04 FMUL	D1, D1, D0

          (2878) 0x483d08 STR	D1, [X10, X1,LSL #3]

          (2878) 0x483d0c ADD	X1, X1, #1

          (2878) 0x483d10 B	483cd8

0x483d14 HINT	#0

0x483d18 HINT	#0

0x483d1c HINT	#0

      (2872) 0x483d20 ORR	X2, XZR, X19

      (2872) 0x483d24 LDR	X3, [X15, X26,LSL #3]

      (2872) 0x483d28 ADD	X26, X26, #1

      (2872) 0x483d2c LDR	X8, [X15, X26,LSL #3]

      (2872) 0x483d30 CMP	X3, X8

      (2872) 0x483d34 B.GE	483b88

    (2873) 0x483d38 LDP	X9, X8, [SP, #64]

    (2873) 0x483d3c LDR	X4, [X9]

    (2873) 0x483d40 LDR	X5, [X8]

    (2873) 0x483d44 LDP	X9, X8, [SP, #80]

    (2873) 0x483d48 LDR	X6, [X9]

    (2873) 0x483d4c LDR	X7, [X8]

    (2873) 0x483d50 B	483d70

0x483d54 HINT	#0

0x483d58 HINT	#0

0x483d5c HINT	#0

    (2873) 0x483d60 LDR	X8, [X15, X26,LSL #3]

    (2873) 0x483d64 ADD	X3, X3, #1

    (2873) 0x483d68 CMP	X3, X8

    (2873) 0x483d6c B.GE	483b88

    (2873) 0x483d70 LDR	X8, [X16, X3,LSL #3]

    (2873) 0x483d74 LDR	D0, [X17, X3,LSL #3]

    (2873) 0x483d78 ADD	X30, X8, #1

    (2873) 0x483d7c LDR	X9, [X18, X8,LSL #3]

    (2873) 0x483d80 LDR	X27, [X18, X30,LSL #3]

    (2873) 0x483d84 CMP	X9, X27

    (2873) 0x483d88 B.GE	483dec

    (2873) 0x483d8c LDUR	X10, [X29, #464]

    (2873) 0x483d90 LDR	X23, [X25]

    (2873) 0x483d94 LDR	X24, [X21]

    (2873) 0x483d98 LDR	X10, [X10]

    (2873) 0x483d9c B	483dbc

      (2876) 0x483da0 LDR	D1, [X10, X9,LSL #3]

      (2876) 0x483da4 LDR	D2, [X23, X12,LSL #3]

      (2876) 0x483da8 FMADD	D1, D1, D0, D2

      (2876) 0x483dac STR	D1, [X23, X12,LSL #3]

      (2876) 0x483db0 ADD	X9, X9, #1

      (2876) 0x483db4 CMP	X9, X27

      (2876) 0x483db8 B.GE	483dec

      (2876) 0x483dbc LDR	X11, [X4, X9,LSL #3]

      (2876) 0x483dc0 LDR	X12, [X0, X11,LSL #3]

      (2876) 0x483dc4 CMP	X12, X22

      (2876) 0x483dc8 B.GE	483da0

      (2876) 0x483dcc LDR	D1, [X10, X9,LSL #3]

      (2876) 0x483dd0 STR	X1, [X0, X11,LSL #3]

      (2876) 0x483dd4 STR	X11, [X24, X1,LSL #3]

      (2876) 0x483dd8 LDR	X27, [X18, X30,LSL #3]

      (2876) 0x483ddc FMUL	D1, D1, D0

      (2876) 0x483de0 STR	D1, [X23, X1,LSL #3]

      (2876) 0x483de4 ADD	X1, X1, #1

      (2876) 0x483de8 B	483db0

    (2873) 0x483dec LDR	X9, [X28]

    (2873) 0x483df0 CBZ	X9, 483d60

    (2873) 0x483df4 LDR	X8, [X5, X8,LSL #3]

    (2873) 0x483df8 LDR	X23, [X5, X30,LSL #3]

    (2873) 0x483dfc CMP	X8, X23

    (2873) 0x483e00 B.GE	483d60

  (2875) 0x483e04 LDUR	X9, [X29, #456]

  (2875) 0x483e08 LDP	X10, X11, [X29, #1000]

  (2875) 0x483e0c LDR	X9, [X9]

  (2875) 0x483e10 LDR	X10, [X10]

  (2875) 0x483e14 LDR	X27, [X11]

  (2875) 0x483e18 B	483e3c

0x483e1c HINT	#0

(2874) 0x483e20 LDR	D1, [X9, X8,LSL #3]

(2874) 0x483e24 LDR	D2, [X10, X11,LSL #3]

(2874) 0x483e28 FMADD	D1, D1, D0, D2

(2874) 0x483e2c STR	D1, [X10, X11,LSL #3]

  (2875) 0x483e30 ADD	X8, X8, #1

  (2875) 0x483e34 CMP	X8, X23

  (2875) 0x483e38 B.GE	483d60

  (2875) 0x483e3c LDR	X12, [X7, X8,LSL #3]

  (2875) 0x483e40 LDR	X11, [X20]

  (2875) 0x483e44 LDR	X12, [X6, X12,LSL #3]

  (2875) 0x483e48 ADD	X24, X12, X11

  (2875) 0x483e4c LDR	X11, [X0, X24,LSL #3]

  (2875) 0x483e50 CMP	X11, X19

  (2875) 0x483e54 B.GE	483e20

  (2875) 0x483e58 STR	X2, [X0, X24,LSL #3]

  (2875) 0x483e5c LDR	D1, [X9, X8,LSL #3]

  (2875) 0x483e60 LDR	X11, [X20]

  (2875) 0x483e64 SUB	X11, X24, X11

  (2875) 0x483e68 STR	X11, [X27, X2,LSL #3]

  (2875) 0x483e6c FMUL	D1, D1, D0

  (2875) 0x483e70 LDR	X23, [X5, X30,LSL #3]

  (2875) 0x483e74 STR	D1, [X10, X2,LSL #3]

  (2875) 0x483e78 ADD	X2, X2, #1

  (2875) 0x483e7c B	483e30

0x483e80 LDP	X20, X19, [SP, #304]

0x483e84 LDP	X22, X21, [SP, #288]

0x483e88 LDP	X24, X23, [SP, #272]

0x483e8c LDP	X26, X25, [SP, #256]

0x483e90 LDP	X28, X27, [SP, #240]

0x483e94 LDP	X29, X30, [SP, #224]

0x483e98 ADD	SP, SP, #320

0x483e9c B	4a6d90

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 28.83 to 23.67 cycles (1.22x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.83 to 1.50 cycles (19.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 552 bytes. The binary function is storing 336 bytes.

General properties

nb instructions	136
loop length	544
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	5.83	5.83	5.83	5.83	6.00	5.67	0.00	0.00	0.00	0.00	28.83	28.50	28.67	16.50	16.50
cycles	4.50	4.50	5.83	5.83	5.83	5.83	6.00	5.67	0.00	0.00	0.00	0.00	28.83	28.50	28.67	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	15.88
Overall L1	28.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.83 cycles. At this rate:

19% of peak load performance is reached (19.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 483990

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X24, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X10, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X9, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X8, X9, X0, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X11, X9, X23, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X23, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
MADD X8, X9, X10, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X9, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X9, X10, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CSEL X8, X8, X9, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X26, X11, X12, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X10, 483acc <hypre_ParMatmul.omp_outlined.7+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 483b24 <hypre_ParMatmul.omp_outlined.7+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X24, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X23, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 483b1c <hypre_ParMatmul.omp_outlined.7+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 483e80 <hypre_ParMatmul.omp_outlined.7+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X1, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X17, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X8, X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 483b9c <hypre_ParMatmul.omp_outlined.7+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a6d90 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.83 to 1.50 cycles (19.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 552 bytes. The binary function is storing 336 bytes.

General properties

nb instructions	136
loop length	544
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	5.83	5.83	5.83	5.83	6.00	5.67	0.00	0.00	0.00	0.00	28.83	28.50	28.67	16.50	16.50
cycles	4.50	4.50	5.83	5.83	5.83	5.83	6.00	5.67	0.00	0.00	0.00	0.00	28.83	28.50	28.67	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	15.88
Overall L1	28.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.83 cycles. At this rate:

19% of peak load performance is reached (19.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 483990

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X24, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X10, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X9, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X8, X9, X0, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X11, X9, X23, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X23, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
MADD X8, X9, X10, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X9, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X9, X10, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CSEL X8, X8, X9, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X26, X11, X12, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X10, 483acc <hypre_ParMatmul.omp_outlined.7+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 483b24 <hypre_ParMatmul.omp_outlined.7+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X24, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X23, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 483b1c <hypre_ParMatmul.omp_outlined.7+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 483e80 <hypre_ParMatmul.omp_outlined.7+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X1, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X17, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X8, X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 483b9c <hypre_ParMatmul.omp_outlined.7+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a6d90 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul.omp_outlined.7–	0.90	0.19
○Loop 2880 - par_csr_matop.c:858-859 - exec	0.01	0.00
▼Loop 2874 - par_csr_matop.c:865-989 - exec–	0.00	0.00
▼Loop 2875 - par_csr_matop.c:865-986 - exec–	0.00	0.00
▼Loop 2873 - par_csr_matop.c:865-970 - exec–	0.25	0.04
○Loop 2876 - par_csr_matop.c:946-965 - exec	0.63	0.10
▼Loop 2872 - par_csr_matop.c:865-937 - exec–	0.01	0.01
▼Loop 2877 - par_csr_matop.c:888-928 - exec–	0.00	0.00
○Loop 2879 - par_csr_matop.c:897-915 - exec	0.00	0.00
○Loop 2878 - par_csr_matop.c:917-928 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code