OV - exec - Function hypre_BoomerAMGBuildExtPIInterp.omp

	Function: hypre_BoomerAMGBuildExtPIInterp.omp_outlined	Module: exec	Source: par_lr_interp.c:1196-1757 [...]	Coverage (incl. loops): 0.23% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1196 - 1757

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1196: #pragma omp parallel private(i,my_thread_num,num_threads,start,stop,coarse_counter,jj_counter,jj_counter_offd, P_marker, P_marker_offd,jj,kk,i1,k1,loc_col,jj_begin_row,jj_begin_row_offd,jj_end_row,jj_end_row_offd,diagonal,sum,sgn,jj1,i2,distribute,strong_f_marker)

[...]

1219:        jj_counter = start_indexing;

1220:        jj_counter_offd = start_indexing;

1221:        if (n_fine)

1222:        {

1223:            P_marker = hypre_CTAlloc(HYPRE_Int, n_fine);

1224:            for (i = 0; i < n_fine; i++)

1225:            {  P_marker[i] = -1; }

1226:        }

1227:        if (full_off_procNodes)

1228:        {

1229:          P_marker_offd = hypre_CTAlloc(HYPRE_Int, full_off_procNodes);

1230:          for (i = 0; i < full_off_procNodes; i++)

1231:          {  P_marker_offd[i] = -1;}

1232:        }

1233:

1234:        /* this thread's row range */

1235:        my_thread_num = hypre_GetThreadNum();

1236:        num_threads = hypre_NumActiveThreads();

1237:        start = (n_fine/num_threads)*my_thread_num;

1238:        if (my_thread_num == num_threads-1)

[...]

1244:        for (i = start; i < stop; i++)

1245:        {

1246:          P_diag_i[i] = jj_counter;

1247:          if (num_procs > 1)

1248:            P_offd_i[i] = jj_counter_offd;

1249:

1250:          if (CF_marker[i] >= 0)

1251:          {

1252:            jj_counter++;

1253:            fine_to_coarse[i] = coarse_counter;

1254:            coarse_counter++;

[...]

1262:          else if (CF_marker[i] != -3)

1263:          {

1264:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1265:            {

1266:              i1 = S_diag_j[jj];

1267:              if (CF_marker[i1] >= 0)

1268:              { /* i1 is a C point */

1269:                if (P_marker[i1] < P_diag_i[i])

1270:                {

1271:                  P_marker[i1] = jj_counter;

1272:                  jj_counter++;

1273:                }

1274:              }

1275:              else if (CF_marker[i1] != -3)

1276:              { /* i1 is a F point, loop through it's strong neighbors */

1277:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1278:                {

1279:                  k1 = S_diag_j[kk];

1280:                  if (CF_marker[k1] >= 0)

1281:                  {

1282:                    if(P_marker[k1] < P_diag_i[i])

1283:                    {

1284:                      P_marker[k1] = jj_counter;

1285:                      jj_counter++;

1286:                    }

1287:                  }

1288:                }

1289:                if(num_procs > 1)

1290:                {

1291:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1292:                  {

1293:                    if(col_offd_S_to_A)

1294:                      k1 = col_offd_S_to_A[S_offd_j[kk]];

1295:                    else

1296:                      k1 = S_offd_j[kk];

1297:                    if (CF_marker_offd[k1] >= 0)

1298:                    {

1299:                      if(P_marker_offd[k1] < P_offd_i[i])

1300:                      {

1301:                        tmp_CF_marker_offd[k1] = 1;

1302:                        P_marker_offd[k1] = jj_counter_offd;

1303:                        jj_counter_offd++;

[...]

1311:            if (num_procs > 1)

1312:            {

1313:              for (jj = S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1314:              {

1315:                i1 = S_offd_j[jj];

1316:                if(col_offd_S_to_A)

1317:                  i1 = col_offd_S_to_A[i1];

1318:                if (CF_marker_offd[i1] >= 0)

1319:                {

1320:                  if(P_marker_offd[i1] < P_offd_i[i])

1321:                  {

1322:                    tmp_CF_marker_offd[i1] = 1;

1323:                    P_marker_offd[i1] = jj_counter_offd;

1324:                    jj_counter_offd++;

1325:                  }

1326:                }

1327:                else if (CF_marker_offd[i1] != -3)

1328:                { /* F point; look at neighbors of i1. Sop contains global col

1329:                   * numbers and entries that could be in S_diag or S_offd or

1330:                   * neither. */

1331:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1332:                  {

1333:                    k1 = Sop_j[kk];

1334:                    if(k1 >= col_1 && k1 < col_n)

1335:                    { /* In S_diag */

1336:                      loc_col = k1-col_1;

1337:                      if(P_marker[loc_col] < P_diag_i[i])

1338:                      {

1339:                        P_marker[loc_col] = jj_counter;

1340:                        jj_counter++;

1341:                      }

1342:                    }

1343:                    else

1344:                    {

1345:                      loc_col = -k1 - 1;

1346:                      if(P_marker_offd[loc_col] < P_offd_i[i])

1347:                      {

1348:                        P_marker_offd[loc_col] = jj_counter_offd;

1349:                        tmp_CF_marker_offd[loc_col] = 1;

1350:                        jj_counter_offd++;

[...]

1363: #pragma omp barrier

1364: #endif

1365:        P_diag_i[stop] = jj_counter;

1366:        P_offd_i[stop] = jj_counter_offd;

1367:        fine_to_coarse_offset[my_thread_num] = coarse_counter;

1368:        diag_offset[my_thread_num] = jj_counter;

1369:        offd_offset[my_thread_num] = jj_counter_offd;

1370:

1371:        /* Stitch P_diag_i, P_offd_i and fine_to_coarse together */

1372: #ifdef HYPRE_USING_OPENMP

1373: #pragma omp barrier

1374: #endif

1375:        if(my_thread_num == 0)

1376:        {

1377:          /* Calculate the offset for P_diag_i and P_offd_i for each thread */

1378:          for (i = 1; i < num_threads; i++)

1379:          {

1380:            diag_offset[i] = diag_offset[i-1] + diag_offset[i];

1381:            fine_to_coarse_offset[i] = fine_to_coarse_offset[i-1] + fine_to_coarse_offset[i];

1382:            offd_offset[i] = offd_offset[i-1] + offd_offset[i];

1383:          }

1384:        }

1385: #ifdef HYPRE_USING_OPENMP

1386: #pragma omp barrier

1387: #endif

1388:

1389:        if(my_thread_num > 0)

1390:        {

1391:          /* update row pointer array with offset,

1392:           * making sure to update the row stop index */

1393:          for (i = start+1; i <= stop; i++)

1394:          {

1395:             P_diag_i[i] += diag_offset[my_thread_num-1];

1396:             P_offd_i[i] += offd_offset[my_thread_num-1];

1397:          }

1398:          /* update fine_to_coarse by offsetting with the offset

1399:           * from the preceding thread */

1400:          for (i = start; i < stop; i++)

1401:          {

1402:            if(fine_to_coarse[i] >= 0)

1403:            { fine_to_coarse[i] += fine_to_coarse_offset[my_thread_num-1]; }

1404:          }

1405:        }

1406: #ifdef HYPRE_USING_OPENMP

1407: #pragma omp barrier

1408: #endif

1409:

1410:        if(my_thread_num == 0)

1411:        {

1412:          if (debug_flag==4)

1413:          {

1414:             wall_time = time_getWallclockSeconds() - wall_time;

1415:             hypre_printf("Proc = %d     determine structure    %f\n",

1416:                           my_id, wall_time);

1417:             fflush(NULL);

[...]

1423:          if (debug_flag== 4) wall_time = time_getWallclockSeconds();

1424:

1425:          P_diag_size =  P_diag_i[n_fine];

1426:          P_offd_size = P_offd_i[n_fine];

1427:

1428:          if (P_diag_size)

1429:          {

1430:             P_diag_j    = hypre_CTAlloc(HYPRE_Int, P_diag_size);

1431:             P_diag_data = hypre_CTAlloc(HYPRE_Real, P_diag_size);

1432:          }

1433:

1434:          if (P_offd_size)

1435:          {

1436:             P_offd_j    = hypre_CTAlloc(HYPRE_Int, P_offd_size);

1437:             P_offd_data = hypre_CTAlloc(HYPRE_Real, P_offd_size);

1438:          }

1439:        }

1440:

1441:        /* Fine to coarse mapping */

1442:        if(num_procs > 1   &&   my_thread_num == 0)

1443:        {

1444:          for (i = 0; i < n_fine; i++)

1445:            fine_to_coarse[i] += my_first_cpt;

1446:

1447:          hypre_alt_insert_new_nodes(comm_pkg, extend_comm_pkg, fine_to_coarse,

1448:                   full_off_procNodes,

1449:                   fine_to_coarse_offd);

1450:

1451:          for (i = 0; i < n_fine; i++)

1452:            fine_to_coarse[i] -= my_first_cpt;

1453:        }

1454:

1455:        for (i = 0; i < n_fine; i++)

1456:          P_marker[i] = -1;

1457:

1458:        for (i = 0; i < full_off_procNodes; i++)

1459:          P_marker_offd[i] = -1;

[...]

1467: #pragma omp barrier

1468: #endif

1469:        for (i = start; i < stop; i++)

1470:        {

1471:          jj_begin_row = P_diag_i[i];

[...]

1480:          if (CF_marker[i] >= 0)

1481:          {

1482:            P_diag_j[jj_counter]    = fine_to_coarse[i];

1483:            P_diag_data[jj_counter] = one;

[...]

1491:          else if (CF_marker[i] != -3)

1492:          {

1493:            strong_f_marker--;

1494:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1495:            {

1496:              i1 = S_diag_j[jj];

[...]

1503:              if (CF_marker[i1] >= 0)

1504:              {

1505:                if (P_marker[i1] < jj_begin_row)

1506:                {

1507:                  P_marker[i1] = jj_counter;

1508:                  P_diag_j[jj_counter]    = fine_to_coarse[i1];

1509:                  P_diag_data[jj_counter] = zero;

1510:                  jj_counter++;

1511:                }

1512:              }

1513:              else  if (CF_marker[i1] != -3)

1514:              {

1515:                P_marker[i1] = strong_f_marker;

1516:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1517:                {

1518:                  k1 = S_diag_j[kk];

1519:                  if (CF_marker[k1] >= 0)

1520:                  {

1521:                    if(P_marker[k1] < jj_begin_row)

1522:                    {

1523:                      P_marker[k1] = jj_counter;

1524:                      P_diag_j[jj_counter] = fine_to_coarse[k1];

1525:                      P_diag_data[jj_counter] = zero;

1526:                      jj_counter++;

1527:                    }

1528:                  }

1529:                }

1530:                if(num_procs > 1)

1531:                {

1532:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1533:                  {

1534:                    if(col_offd_S_to_A)

1535:                     k1 = col_offd_S_to_A[S_offd_j[kk]];

1536:                    else

1537:                     k1 = S_offd_j[kk];

1538:                    if(CF_marker_offd[k1] >= 0)

1539:                    {

1540:                      if(P_marker_offd[k1] < jj_begin_row_offd)

1541:                      {

1542:                        P_marker_offd[k1] = jj_counter_offd;

1543:                        P_offd_j[jj_counter_offd] = k1;

1544:                        P_offd_data[jj_counter_offd] = zero;

1545:                        jj_counter_offd++;

[...]

1553:            if ( num_procs > 1)

1554:            {

1555:              for (jj=S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1556:              {

1557:                i1 = S_offd_j[jj];

1558:                if(col_offd_S_to_A)

1559:                  i1 = col_offd_S_to_A[i1];

1560:                if ( CF_marker_offd[i1] >= 0)

1561:                {

1562:                  if(P_marker_offd[i1] < jj_begin_row_offd)

1563:                  {

1564:                    P_marker_offd[i1] = jj_counter_offd;

1565:                    P_offd_j[jj_counter_offd] = i1;

1566:                    P_offd_data[jj_counter_offd] = zero;

1567:                    jj_counter_offd++;

1568:                  }

1569:                }

1570:                else if (CF_marker_offd[i1] != -3)

1571:                {

1572:                  P_marker_offd[i1] = strong_f_marker;

1573:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1574:                  {

1575:                    k1 = Sop_j[kk];

1576:                    /* Find local col number */

1577:                    if(k1 >= col_1 && k1 < col_n)

1578:                    {

1579:                      loc_col = k1-col_1;

1580:                      if(P_marker[loc_col] < jj_begin_row)

1581:                      {

1582:                        P_marker[loc_col] = jj_counter;

1583:                        P_diag_j[jj_counter] = fine_to_coarse[loc_col];

1584:                        P_diag_data[jj_counter] = zero;

1585:                        jj_counter++;

1586:                      }

1587:                    }

1588:                    else

1589:                    {

1590:                      loc_col = -k1 - 1;

1591:                      if(P_marker_offd[loc_col] < jj_begin_row_offd)

1592:                      {

1593:                        P_marker_offd[loc_col] = jj_counter_offd;

1594:                        P_offd_j[jj_counter_offd]=loc_col;

1595:                        P_offd_data[jj_counter_offd] = zero;

1596:                        jj_counter_offd++;

[...]

1607:            diagonal = A_diag_data[A_diag_i[i]];

1608:

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

1676:              }

1677:            }

1678:            if(num_procs > 1)

1679:            {

1680:              for(jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

1681:              {

1682:                i1 = A_offd_j[jj];

1683:                if(P_marker_offd[i1] >= jj_begin_row_offd)

1684:                  P_offd_data[P_marker_offd[i1]] += A_offd_data[jj];

1685:                else if(P_marker_offd[i1] == strong_f_marker)

1686:                {

1687:                  sum = zero;

1688:                  for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1689:                  {

1690:                    k1 = A_ext_j[jj1];

1691:                    if(k1 >= col_1 && k1 < col_n)

1692:                    { /* diag */

1693:                      loc_col = k1 - col_1;

1694:                      if(P_marker[loc_col] >= jj_begin_row || loc_col == i)

1695:                        sum += A_ext_data[jj1];

1696:                    }

1697:                    else

1698:                    {

1699:                      loc_col = -k1 - 1;

1700:                      if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1701:                        sum += A_ext_data[jj1];

1702:                    }

1703:                  }

1704:                  if(sum != 0)

1705:                  {

1706:                    distribute = A_offd_data[jj] / sum;

1707:                    for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1708:                    {

1709:                      k1 = A_ext_j[jj1];

1710:                      if(k1 >= col_1 && k1 < col_n)

1711:                      { /* diag */

1712:                        loc_col = k1 - col_1;

1713:                        if(P_marker[loc_col] >= jj_begin_row)

1714:                          P_diag_data[P_marker[loc_col]] += distribute*

1715:                           A_ext_data[jj1];

1716:                                if(loc_col == i)

1717:                                  diagonal += distribute*A_ext_data[jj1];

1718:                      }

1719:                      else

1720:                      {

1721:                        loc_col = -k1 - 1;

1722:                        if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1723:                          P_offd_data[P_marker_offd[loc_col]] += distribute*

1724:                            A_ext_data[jj1];

[...]

1733:                else if (CF_marker_offd[i1] != -3)

1734:                {

1735:                  if(num_functions == 1 || dof_func[i] == dof_func_offd[i1])

1736:                    diagonal += A_offd_data[jj];

1737:                }

1738:              }

1739:            }

1740:            if (diagonal)

1741:            {

1742:              for(jj = jj_begin_row; jj < jj_end_row; jj++)

1743:                 P_diag_data[jj] /= -diagonal;

1744:              for(jj = jj_begin_row_offd; jj < jj_end_row_offd; jj++)

1745:                 P_offd_data[jj] /= -diagonal;

1746:            }

1747:          }

1748:          strong_f_marker--;

[...]

1754:        if (n_fine)

1755:        {  hypre_TFree(P_marker); }

1756:        if (full_off_procNodes)

1757:        {  hypre_TFree(P_marker_offd); }

0x438a00 STP	X29, X30, [SP, #928]!

0x438a04 STP	X28, X27, [SP, #16]

0x438a08 STP	X26, X25, [SP, #32]

0x438a0c STP	X24, X23, [SP, #48]

0x438a10 STP	X22, X21, [SP, #64]

0x438a14 STP	X20, X19, [SP, #80]

0x438a18 ADD	X29, SP, #0

0x438a1c SUB	SP, SP, #448

0x438a20 STUR	X7, [X29, #464]

0x438a24 STUR	X6, [X29, #480]

0x438a28 LDR	X20, [X2]

0x438a2c ORR	X19, XZR, X3

0x438a30 STUR	X5, [X29, #448]

0x438a34 STR	X0, [SP, #192]

0x438a38 LDR	X0, [X3]

0x438a3c LDR	X8, [X29, #432]

0x438a40 STR	X8, [SP, #96]

0x438a44 LDP	X8, X9, [X29, #416]

0x438a48 STUR	X9, [X29, #296]

0x438a4c STR	X8, [SP, #88]

0x438a50 LDR	X8, [X29, #408]

0x438a54 STR	X8, [SP, #80]

0x438a58 LDR	X8, [X29, #400]

0x438a5c STR	X8, [SP, #152]

0x438a60 LDR	X8, [X29, #392]

0x438a64 STR	X8, [SP, #144]

0x438a68 LDP	X8, X9, [X29, #376]

0x438a6c STUR	X9, [X29, #360]

0x438a70 STR	X8, [SP, #136]

0x438a74 LDR	X8, [X29, #368]

0x438a78 STR	X8, [SP, #128]

0x438a7c LDP	X8, X26, [X29, #336]

0x438a80 LDP	X25, X21, [X29, #352]

0x438a84 STUR	X8, [X29, #496]

0x438a88 LDP	X27, X8, [X29, #320]

0x438a8c STUR	X8, [X29, #320]

0x438a90 LDR	X8, [X29, #312]

0x438a94 STR	X8, [SP, #24]

0x438a98 LDR	X8, [X29, #304]

0x438a9c STR	X8, [SP, #16]

0x438aa0 LDR	X8, [X29, #296]

0x438aa4 STR	X8, [SP, #48]

0x438aa8 LDP	X8, X9, [X29, #280]

0x438aac STUR	X8, [X29, #344]

0x438ab0 LDP	X8, X10, [X29, #264]

0x438ab4 STP	X8, X9, [X29, #904]

0x438ab8 LDR	X8, [X29, #256]

0x438abc STUR	X10, [X29, #432]

0x438ac0 STR	X8, [SP, #216]

0x438ac4 LDR	X8, [X29, #248]

0x438ac8 STR	X8, [SP, #64]

0x438acc LDR	X8, [X29, #240]

0x438ad0 STR	X8, [SP, #8]

0x438ad4 LDR	X8, [X29, #232]

0x438ad8 STR	X8, [SP, #40]

0x438adc LDR	X8, [X29, #224]

0x438ae0 STR	X8, [SP, #56]

0x438ae4 LDR	X8, [X29, #216]

0x438ae8 STR	X8, [SP, #200]

0x438aec LDP	X8, X9, [X29, #200]

0x438af0 STUR	X9, [X29, #424]

0x438af4 STR	X8, [SP, #208]

0x438af8 LDR	X8, [X29, #176]

0x438afc LDP	X28, X24, [X29, #184]

0x438b00 STR	X8, [SP, #120]

0x438b04 LDR	X8, [X29, #168]

0x438b08 STR	X8, [SP, #112]

0x438b0c LDP	X8, X9, [X29, #152]

0x438b10 STUR	X9, [X29, #456]

0x438b14 LDP	X10, X9, [X29, #136]

0x438b18 STUR	X8, [X29, #336]

0x438b1c STUR	X9, [X29, #352]

0x438b20 LDP	X11, X9, [X29, #120]

0x438b24 STP	X9, X10, [X29, #816]

0x438b28 LDP	X8, X9, [X29, #104]

0x438b2c STP	X8, X11, [X29, #920]

0x438b30 LDR	X8, [X29, #96]

0x438b34 STP	X8, X9, [X29, #880]

0x438b38 STR	X4, [SP, #224]

0x438b3c CBZ	X0, 438b7c

0x438b40 MOVZ	W1, #8

0x438b44 BL	4a6c90

0x438b48 LDR	X8, [X19]

0x438b4c ORR	X22, XZR, X0

0x438b50 CMP	X8, #1

0x438b54 B.LT	438b74

0x438b58 MOVN	X9, #0

0x438b5c ORR	X8, XZR, XZR

(855) 0x438b60 STR	X9, [X22, X8,LSL #3]

(855) 0x438b64 ADD	X8, X8, #1

(855) 0x438b68 LDR	X10, [X19]

(855) 0x438b6c CMP	X8, X10

(855) 0x438b70 B.LT	438b60

0x438b74 LDR	X4, [SP, #224]

0x438b78 B	438b7c

0x438b7c LDR	X0, [X4]

0x438b80 STP	X26, X21, [SP, #160]

0x438b84 STR	X27, [SP, #32]

0x438b88 STR	X25, [SP, #104]

0x438b8c CBZ	X0, 438bd8

0x438b90 MOVZ	W1, #8

0x438b94 BL	4a6c90

0x438b98 LDR	X11, [SP, #224]

0x438b9c ORR	X23, XZR, X0

0x438ba0 LDR	X8, [X11]

0x438ba4 CMP	X8, #1

0x438ba8 B.LT	438bd8

0x438bac MOVN	X9, #0

0x438bb0 ORR	X8, XZR, XZR

0x438bb4 HINT	#0

0x438bb8 HINT	#0

0x438bbc HINT	#0

(854) 0x438bc0 STR	X9, [X23, X8,LSL #3]

(854) 0x438bc4 ADD	X8, X8, #1

(854) 0x438bc8 LDR	X10, [X11]

(854) 0x438bcc CMP	X8, X10

(854) 0x438bd0 B.LT	438bc0

0x438bd4 B	438bd8

0x438bd8 BL	4a8a10

0x438bdc ORR	X21, XZR, X0

0x438be0 BL	4a89f0

0x438be4 LDR	X8, [X19]

0x438be8 SUB	X9, X0, #1

0x438bec STUR	X19, [X29, #328]

0x438bf0 STR	X21, [SP, #176]

0x438bf4 ORR	X26, XZR, XZR

0x438bf8 CMP	X21, X9

0x438bfc SDIV	X10, X8, X0

0x438c00 MADD	X27, X10, X21, XZR

0x438c04 STR	X10, [SP, #72]

0x438c08 ADD	X10, X10, X27

0x438c0c CSEL	X14, X8, X10, #0

0x438c10 STUR	X14, [X29, #384]

0x438c14 STR	X0, [SP, #184]

0x438c18 CMP	X14, X27

0x438c1c B.GT	438d34

0x438c20 ORR	X19, XZR, X20

0x438c24 STUR	X28, [X29, #488]

0x438c28 ADRP	X0,

0x438c2c ADD	X0, X0, #1192

0x438c30 ORR	X21, XZR, X14

0x438c34 LDR	X8, [SP, #192]

0x438c38 LDR	W28, [X8]

0x438c3c ORR	W1, WZR, W28

0x438c40 BL	40f440

0x438c44 LDUR	X8, [X29, #448]

0x438c48 LDR	X25, [SP, #176]

0x438c4c ADRP	X0,

0x438c50 ADD	X0, X0, #1216

0x438c54 ORR	W1, WZR, W28

0x438c58 LDR	X8, [X8]

0x438c5c STR	X19, [X8, X21,LSL #3]

0x438c60 LDUR	X8, [X29, #464]

0x438c64 LDR	X8, [X8]

0x438c68 STR	X20, [X8, X21,LSL #3]

0x438c6c LDR	X21, [SP, #208]

0x438c70 LDR	X8, [X21]

0x438c74 STR	X26, [X8, X25,LSL #3]

0x438c78 LDUR	X8, [X29, #424]

0x438c7c LDR	X26, [SP, #200]

0x438c80 LDR	X8, [X8]

0x438c84 STR	X19, [X8, X25,LSL #3]

0x438c88 LDR	X8, [X26]

0x438c8c STR	X20, [X8, X25,LSL #3]

0x438c90 ORR	W20, WZR, W28

0x438c94 BL	40f440

0x438c98 LDUR	X19, [X29, #328]

0x438c9c LDR	X28, [SP, #216]

0x438ca0 LDR	X12, [SP, #184]

0x438ca4 CBNZ	X25, 4390ec

0x438ca8 SUBS	X8, X12, #1

0x438cac B.LE	4390ec

0x438cb0 LDUR	X9, [X29, #424]

0x438cb4 LDR	X11, [X26]

0x438cb8 LDR	X10, [X21]

0x438cbc ADD	X13, X11, X12,LSL #3

0x438cc0 LDR	X9, [X9]

0x438cc4 ADD	X15, X10, X12,LSL #3

0x438cc8 ADD	X14, X9, X12,LSL #3

0x438ccc CMP	X9, X13

0x438cd0 CCMP	X11, X14, #2, #3

0x438cd4 CSINC	W12, WZR, WZR, #2

0x438cd8 CMP	X10, X13

0x438cdc CCMP	X11, X15, #2, #3

0x438ce0 CSINC	W13, WZR, WZR, #2

0x438ce4 CMP	X10, X14

0x438ce8 CCMP	X9, X15, #2, #3

0x438cec B.CC	4390a8

0x438cf0 TBNZ	W12, #0, 4390a8

0x438cf4 CBNZ	W13, 4390a8

0x438cf8 LDR	X12, [X9], #8

0x438cfc LDR	X13, [X11], #8

0x438d00 LDR	X14, [X10], #8

(845) 0x438d04 LDR	X15, [X9]

(845) 0x438d08 SUBS	X8, X8, #1

(845) 0x438d0c ADD	X12, X15, X12

(845) 0x438d10 STR	X12, [X9], #8

(845) 0x438d14 LDR	X15, [X10]

(845) 0x438d18 ADD	X14, X15, X14

(845) 0x438d1c STR	X14, [X10], #8

(845) 0x438d20 LDR	X15, [X11]

(845) 0x438d24 ADD	X13, X15, X13

(845) 0x438d28 STR	X13, [X11], #8

(845) 0x438d2c B.NE	438d04

0x438d30 B	4390ec

0x438d34 LDUR	X9, [X29, #464]

0x438d38 LDUR	X8, [X29, #448]

0x438d3c ORR	X18, XZR, X27

0x438d40 ORR	X19, XZR, X20

0x438d44 LDR	X25, [X9]

0x438d48 LDP	X11, X9, [X29, #880]

0x438d4c LDR	X8, [X8]

0x438d50 LDR	X10, [X11]

0x438d54 LDR	X11, [X9]

0x438d58 LDUR	X9, [X29, #416]

0x438d5c LDR	X12, [X9]

0x438d60 LDUR	X9, [X29, #304]

0x438d64 LDR	X13, [X9]

0x438d68 LDUR	X9, [X29, #352]

0x438d6c LDR	X9, [X9]

0x438d70 STUR	X9, [X29, #488]

0x438d74 LDUR	X9, [X29, #312]

0x438d78 LDR	X15, [X9]

0x438d7c LDUR	X9, [X29, #336]

0x438d80 LDR	X9, [X9]

0x438d84 STUR	X9, [X29, #472]

0x438d88 LDUR	X9, [X29, #408]

0x438d8c LDR	X16, [X9]

0x438d90 STUR	X16, [X29, #440]

0x438d94 B	438dc0

0x438d98 HINT	#0

0x438d9c HINT	#0

        (846) 0x438da0 LDR	X9, [X10, X18,LSL #3]

        (846) 0x438da4 TBNZ	X9, #63, 438de0

        (846) 0x438da8 ADD	X19, X19, #1

        (846) 0x438dac STR	X26, [X16, X18,LSL #3]

        (846) 0x438db0 ADD	X26, X26, #1

        (846) 0x438db4 ADD	X18, X18, #1

        (846) 0x438db8 CMP	X18, X14

        (846) 0x438dbc B.EQ	438c24

        (846) 0x438dc0 LDUR	X9, [X29, #480]

        (846) 0x438dc4 STR	X19, [X8, X18,LSL #3]

        (846) 0x438dc8 LDR	X9, [X9]

        (846) 0x438dcc CMP	X9, #2

        (846) 0x438dd0 B.LT	438da0

        (846) 0x438dd4 STR	X20, [X25, X18,LSL #3]

        (846) 0x438dd8 B	438da0

0x438ddc HINT	#0

        (846) 0x438de0 CMN	X9, #3

        (846) 0x438de4 B.EQ	438db4

      (847) 0x438de8 ADD	X1, X18, #1

      (847) 0x438dec LDR	X2, [X11, X18,LSL #3]

      (847) 0x438df0 LDR	X9, [X11, X1,LSL #3]

      (847) 0x438df4 CMP	X2, X9

      (847) 0x438df8 B.GE	438f54

      (847) 0x438dfc LDUR	X9, [X29, #304]

      (847) 0x438e00 LDR	X3, [X9]

      (847) 0x438e04 LDUR	X9, [X29, #312]

      (847) 0x438e08 LDR	X4, [X9]

      (847) 0x438e0c LDUR	X9, [X29, #336]

      (847) 0x438e10 LDR	X5, [X9]

      (847) 0x438e14 B	438e30

0x438e18 HINT	#0

0x438e1c HINT	#0

        (851) 0x438e20 LDR	X9, [X11, X1,LSL #3]

        (851) 0x438e24 ADD	X2, X2, #1

        (851) 0x438e28 CMP	X2, X9

        (851) 0x438e2c B.GE	438f54

        (851) 0x438e30 LDR	X7, [X12, X2,LSL #3]

        (851) 0x438e34 LDR	X9, [X10, X7,LSL #3]

        (851) 0x438e38 TBNZ	X9, #63, 438e60

        (851) 0x438e3c LDR	X9, [X22, X7,LSL #3]

        (851) 0x438e40 LDR	X14, [X8, X18,LSL #3]

        (851) 0x438e44 CMP	X9, X14

        (851) 0x438e48 B.GE	438e20

        (851) 0x438e4c STR	X19, [X22, X7,LSL #3]

        (851) 0x438e50 ADD	X19, X19, #1

        (851) 0x438e54 B	438e20

0x438e58 HINT	#0

0x438e5c HINT	#0

        (851) 0x438e60 CMN	X9, #3

        (851) 0x438e64 B.EQ	438e20

        (851) 0x438e68 ADD	X6, X7, #1

        (851) 0x438e6c LDR	X9, [X11, X7,LSL #3]

        (851) 0x438e70 LDR	X0, [X11, X6,LSL #3]

        (851) 0x438e74 B	438e84

0x438e78 HINT	#0

0x438e7c HINT	#0

          (853) 0x438e80 ADD	X9, X9, #1

          (853) 0x438e84 CMP	X9, X0

          (853) 0x438e88 B.GE	438eb8

          (853) 0x438e8c LDR	X14, [X12, X9,LSL #3]

          (853) 0x438e90 LDR	X21, [X10, X14,LSL #3]

          (853) 0x438e94 TBNZ	X21, #63, 438e80

          (853) 0x438e98 LDR	X21, [X22, X14,LSL #3]

          (853) 0x438e9c LDR	X30, [X8, X18,LSL #3]

          (853) 0x438ea0 CMP	X21, X30

          (853) 0x438ea4 B.GE	438e80

          (853) 0x438ea8 STR	X19, [X22, X14,LSL #3]

          (853) 0x438eac ADD	X19, X19, #1

          (853) 0x438eb0 LDR	X0, [X11, X6,LSL #3]

          (853) 0x438eb4 B	438e80

        (851) 0x438eb8 LDUR	X9, [X29, #480]

        (851) 0x438ebc LDR	X9, [X9]

        (851) 0x438ec0 CMP	X9, #2

        (851) 0x438ec4 B.LT	438e20

        (851) 0x438ec8 LDR	X7, [X3, X7,LSL #3]

        (851) 0x438ecc LDR	X9, [X3, X6,LSL #3]

        (851) 0x438ed0 CMP	X7, X9

        (851) 0x438ed4 B.GE	438e20

        (851) 0x438ed8 LDUR	X14, [X29, #352]

        (851) 0x438edc LDP	X16, X17, [X29, #968]

        (851) 0x438ee0 LDR	X14, [X14]

        (851) 0x438ee4 LDR	X21, [X17]

        (851) 0x438ee8 LDR	X30, [X16]

        (851) 0x438eec ADD	X0, X14, X7,LSL #3

        (851) 0x438ef0 B	438f10

0x438ef4 HINT	#0

0x438ef8 HINT	#0

0x438efc HINT	#0

          (852) 0x438f00 ADD	X7, X7, #1

          (852) 0x438f04 ADD	X0, X0, #8

          (852) 0x438f08 CMP	X7, X9

          (852) 0x438f0c B.GE	438e20

          (852) 0x438f10 ORR	X14, XZR, X0

          (852) 0x438f14 CBZ	X4, 438f20

          (852) 0x438f18 LDR	X14, [X0]

          (852) 0x438f1c ADD	X14, X4, X14,LSL #3

          (852) 0x438f20 LDR	X14, [X14]

          (852) 0x438f24 LDR	X16, [X5, X14,LSL #3]

          (852) 0x438f28 TBNZ	X16, #63, 438f00

          (852) 0x438f2c LDR	X16, [X23, X14,LSL #3]

          (852) 0x438f30 LDR	X17, [X21, X18,LSL #3]

          (852) 0x438f34 CMP	X16, X17

          (852) 0x438f38 B.GE	438f00

          (852) 0x438f3c MOVZ	W9, #1

          (852) 0x438f40 STR	X9, [X30, X14,LSL #3]

          (852) 0x438f44 STR	X20, [X23, X14,LSL #3]

          (852) 0x438f48 ADD	X20, X20, #1

          (852) 0x438f4c LDR	X9, [X3, X6,LSL #3]

          (852) 0x438f50 B	438f00

      (847) 0x438f54 LDUR	X9, [X29, #480]

      (847) 0x438f58 LDR	X9, [X9]

      (847) 0x438f5c CMP	X9, #2

      (847) 0x438f60 B.LT	43909c

      (847) 0x438f64 LDR	X2, [X13, X18,LSL #3]

      (847) 0x438f68 LDR	X9, [X13, X1,LSL #3]

      (847) 0x438f6c CMP	X2, X9

      (847) 0x438f70 B.GE	43909c

    (848) 0x438f74 LDR	X9, [SP, #112]

    (848) 0x438f78 LDR	X3, [X9]

    (848) 0x438f7c LDR	X9, [SP, #120]

    (848) 0x438f80 LDR	X4, [X9]

    (848) 0x438f84 LDUR	X9, [X29, #464]

    (848) 0x438f88 LDR	X5, [X9]

    (848) 0x438f8c LDUR	X9, [X29, #456]

    (848) 0x438f90 LDR	X6, [X9]

    (848) 0x438f94 B	438fb0

0x438f98 HINT	#0

0x438f9c HINT	#0

    (848) 0x438fa0 LDR	X9, [X13, X1,LSL #3]

    (848) 0x438fa4 ADD	X2, X2, #1

    (848) 0x438fa8 CMP	X2, X9

    (848) 0x438fac B.GE	43909c

    (848) 0x438fb0 LDUR	X9, [X29, #488]

    (848) 0x438fb4 LDR	X9, [X9, X2,LSL #3]

    (848) 0x438fb8 CBZ	X15, 438fc0

    (848) 0x438fbc LDR	X9, [X15, X9,LSL #3]

    (848) 0x438fc0 LDUR	X14, [X29, #472]

    (848) 0x438fc4 LDR	X14, [X14, X9,LSL #3]

    (848) 0x438fc8 TBNZ	X14, #63, 439000

    (848) 0x438fcc LDR	X14, [X23, X9,LSL #3]

    (848) 0x438fd0 LDR	X16, [X5, X18,LSL #3]

    (848) 0x438fd4 CMP	X14, X16

    (848) 0x438fd8 B.GE	438fa0

    (848) 0x438fdc MOVZ	W14, #1

    (848) 0x438fe0 STR	X14, [X6, X9,LSL #3]

    (848) 0x438fe4 STR	X20, [X23, X9,LSL #3]

    (848) 0x438fe8 ADD	X20, X20, #1

    (848) 0x438fec B	438fa0

0x438ff0 HINT	#0

0x438ff4 HINT	#0

0x438ff8 HINT	#0

0x438ffc HINT	#0

    (848) 0x439000 CMN	X14, #3

    (848) 0x439004 B.EQ	438fa0

    (848) 0x439008 ADD	X7, X3, X9,LSL #3

    (848) 0x43900c LDP	X21, X9, [X7]

    (848) 0x439010 CMP	X21, X9

    (848) 0x439014 B.GE	438fa0

  (850) 0x439018 LDUR	X9, [X29, #464]

  (850) 0x43901c LDR	X30, [X9]

  (850) 0x439020 LDUR	X9, [X29, #456]

  (850) 0x439024 LDR	X9, [X9]

  (850) 0x439028 B	43903c

  (850) 0x43902c LDR	X14, [X7, #8]

  (850) 0x439030 ADD	X21, X21, #1

  (850) 0x439034 CMP	X21, X14

  (850) 0x439038 B.GE	438fa0

  (850) 0x43903c LDR	X0, [X4, X21,LSL #3]

  (850) 0x439040 LDR	X14, [X28]

  (850) 0x439044 LDR	X16, [X24]

  (850) 0x439048 SUBS	X14, X0, X14

  (850) 0x43904c CCMP	X0, X16, #0, #10

  (850) 0x439050 B.LT	439080

  (850) 0x439054 ORN	X14, XZR, X0

  (850) 0x439058 LDR	X17, [X30, X18,LSL #3]

  (850) 0x43905c LDR	X16, [X23, X14,LSL #3]

  (850) 0x439060 CMP	X16, X17

  (850) 0x439064 B.GE	43902c

  (850) 0x439068 STR	X20, [X23, X14,LSL #3]

  (850) 0x43906c MOVZ	W16, #1

  (850) 0x439070 ADD	X20, X20, #1

  (850) 0x439074 STR	X16, [X9, X14,LSL #3]

  (850) 0x439078 B	43902c

0x43907c HINT	#0

(849) 0x439080 LDR	X16, [X22, X14,LSL #3]

(849) 0x439084 LDR	X17, [X8, X18,LSL #3]

(849) 0x439088 CMP	X16, X17

(849) 0x43908c B.GE	43902c

(849) 0x439090 STR	X19, [X22, X14,LSL #3]

(849) 0x439094 ADD	X19, X19, #1

(849) 0x439098 B	43902c

      (847) 0x43909c LDUR	X14, [X29, #384]

      (847) 0x4390a0 LDUR	X16, [X29, #440]

      (847) 0x4390a4 B	438db4

0x4390a8 ADD	X11, X11, #8

0x4390ac ADD	X10, X10, #8

0x4390b0 ADD	X9, X9, #8

0x4390b4 HINT	#0

0x4390b8 HINT	#0

0x4390bc HINT	#0

(844) 0x4390c0 LDP	X12, X13, [X9, #1016]

(844) 0x4390c4 SUBS	X8, X8, #1

(844) 0x4390c8 ADD	X12, X13, X12

(844) 0x4390cc STR	X12, [X9], #8

(844) 0x4390d0 LDP	X12, X13, [X10, #1016]

(844) 0x4390d4 ADD	X12, X13, X12

(844) 0x4390d8 STR	X12, [X10], #8

(844) 0x4390dc LDP	X12, X13, [X11, #1016]

(844) 0x4390e0 ADD	X12, X13, X12

(844) 0x4390e4 STR	X12, [X11], #8

(844) 0x4390e8 B.NE	4390c0

0x4390ec ADRP	X0,

0x4390f0 ADD	X0, X0, #1240

0x4390f4 ORR	W1, WZR, W20

0x4390f8 BL	40f440

0x4390fc LDUR	X1, [X29, #384]

0x439100 CMP	X25, #1

0x439104 B.LT	439190

0x439108 SUBS	X8, X1, X27

0x43910c B.LE	439190

0x439110 LDUR	X9, [X29, #424]

0x439114 LDUR	X11, [X29, #448]

0x439118 LDUR	X12, [X29, #464]

0x43911c ORR	X13, XZR, X27

0x439120 LDR	X16, [X26]

0x439124 LDR	X15, [X9]

0x439128 LDR	X11, [X11]

0x43912c LDR	X12, [X12]

0x439130 UBFM	X9, X25, #61, #60

0x439134 SUB	X10, X9, #8

0x439138 ADD	X9, X15, X10

0x43913c ADD	X10, X16, X10

0x439140 CMP	X8, #15

0x439144 B.HI	43a084

        (833) 0x439148 SUB	X14, X1, X13

        (833) 0x43914c UBFM	X13, X13, #61, #60

        (833) 0x439150 ADD	X13, X13, #8

        (833) 0x439154 ADD	X12, X12, X13

        (833) 0x439158 ADD	X11, X11, X13

        (833) 0x43915c HINT	#0

          (817) 0x439160 LDR	X13, [X9]

          (817) 0x439164 LDR	X15, [X11]

          (817) 0x439168 SUBS	X14, X14, #1

          (817) 0x43916c ADD	X13, X15, X13

          (817) 0x439170 STR	X13, [X11], #8

          (817) 0x439174 LDR	X13, [X10]

          (817) 0x439178 LDR	X15, [X12]

          (817) 0x43917c ADD	X13, X15, X13

          (817) 0x439180 STR	X13, [X12], #8

          (817) 0x439184 B.NE	439160

        (833) 0x439188 CMP	X1, X27

        (833) 0x43918c B.GT	43a16c

        (833) 0x439190 ADRP	X0,

        (833) 0x439194 ADD	X0, X0, #1264

        (833) 0x439198 ORR	W1, WZR, W20

        (833) 0x43919c BL	40f440

        (833) 0x4391a0 CBZ	X25, 4391b4

        (833) 0x4391a4 LDR	X8, [X19]

        (833) 0x4391a8 LDR	X12, [SP, #224]

        (833) 0x4391ac LDUR	X28, [X29, #488]

        (833) 0x4391b0 B	439364

        (833) 0x4391b4 LDR	X9, [SP, #56]

        (833) 0x4391b8 LDR	X8, [X9]

        (833) 0x4391bc CMP	X8, #4

        (833) 0x4391c0 B.NE	439210

        (833) 0x4391c4 ORR	X21, XZR, X9

        (833) 0x4391c8 BL	4a8aa0

        (833) 0x4391cc LDR	X8, [SP, #40]

        (833) 0x4391d0 ADRP	X0,

        (833) 0x4391d4 ADD	X0, X0, #3080

        (833) 0x4391d8 LDR	D1, [X8]

        (833) 0x4391dc FSUB	D0, D0, S1

        (833) 0x4391e0 STR	D0, [X8]

        (833) 0x4391e4 LDR	X8, [SP, #8]

        (833) 0x4391e8 LDR	X1, [X8]

        (833) 0x4391ec BL	4a6ee0

        (833) 0x4391f0 ORR	X0, XZR, XZR

        (833) 0x4391f4 BL	40f6b0

        (833) 0x4391f8 LDR	X8, [X21]

        (833) 0x4391fc CMP	X8, #4

        (833) 0x439200 B.NE	439210

        (833) 0x439204 BL	4a8aa0

        (833) 0x439208 LDR	X8, [SP, #40]

        (833) 0x43920c STR	D0, [X8]

        (833) 0x439210 LDUR	X8, [X29, #448]

        (833) 0x439214 LDR	X9, [X19]

        (833) 0x439218 LDR	X10, [SP, #64]

        (833) 0x43921c LDR	X8, [X8]

        (833) 0x439220 LDR	X8, [X8, X9,LSL #3]

        (833) 0x439224 STR	X8, [X10]

        (833) 0x439228 LDUR	X8, [X29, #464]

        (833) 0x43922c LDR	X9, [X19]

        (833) 0x439230 LDR	X8, [X8]

        (833) 0x439234 LDR	X0, [X8, X9,LSL #3]

        (833) 0x439238 STR	X0, [X28]

        (833) 0x43923c LDR	X8, [X10]

        (833) 0x439240 CBZ	X8, 439274

        (833) 0x439244 MOVZ	W1, #8

        (833) 0x439248 ORR	X0, XZR, X8

        (833) 0x43924c ORR	X21, XZR, X10

        (833) 0x439250 BL	4a6c90

        (833) 0x439254 LDUR	X8, [X29, #392]

        (833) 0x439258 MOVZ	W1, #8

        (833) 0x43925c STR	X0, [X8]

        (833) 0x439260 LDR	X0, [X21]

        (833) 0x439264 BL	4a6c90

        (833) 0x439268 LDUR	X8, [X29, #432]

        (833) 0x43926c STR	X0, [X8]

        (833) 0x439270 LDR	X0, [X28]

        (833) 0x439274 LDR	X12, [SP, #224]

        (833) 0x439278 CBZ	X0, 4392a4

        (833) 0x43927c MOVZ	W1, #8

        (833) 0x439280 BL	4a6c90

        (833) 0x439284 LDUR	X8, [X29, #344]

        (833) 0x439288 MOVZ	W1, #8

        (833) 0x43928c STR	X0, [X8]

        (833) 0x439290 LDR	X0, [X28]

        (833) 0x439294 BL	4a6c90

        (833) 0x439298 LDR	X12, [SP, #224]

        (833) 0x43929c LDUR	X8, [X29, #400]

        (833) 0x4392a0 STR	X0, [X8]

        (833) 0x4392a4 LDP	X8, X28, [X29, #992]

        (833) 0x4392a8 LDR	X9, [X8]

        (833) 0x4392ac LDR	X8, [X19]

        (833) 0x4392b0 CMP	X9, #1

        (833) 0x4392b4 B.LE	439364

        (833) 0x4392b8 LDR	X13, [SP, #48]

        (833) 0x4392bc CMP	X8, #1

        (833) 0x4392c0 B.LT	439300

        (833) 0x4392c4 LDUR	X9, [X29, #408]

        (833) 0x4392c8 ORR	X8, XZR, XZR

        (833) 0x4392cc LDR	X9, [X9]

        (833) 0x4392d0 HINT	#0

        (833) 0x4392d4 HINT	#0

        (833) 0x4392d8 HINT	#0

        (833) 0x4392dc HINT	#0

          (837) 0x4392e0 LDR	X10, [X13]

          (837) 0x4392e4 LDR	X11, [X9, X8,LSL #3]

          (837) 0x4392e8 ADD	X10, X11, X10

          (837) 0x4392ec STR	X10, [X9, X8,LSL #3]

          (837) 0x4392f0 ADD	X8, X8, #1

          (837) 0x4392f4 LDR	X10, [X19]

          (837) 0x4392f8 CMP	X8, X10

          (837) 0x4392fc B.LT	4392e0

        (833) 0x439300 LDP	X9, X8, [SP, #16]

        (833) 0x439304 LDR	X3, [X12]

        (833) 0x439308 LDR	X1, [X8]

        (833) 0x43930c LDUR	X8, [X29, #408]

        (833) 0x439310 LDR	X0, [X9]

        (833) 0x439314 LDR	X2, [X8]

        (833) 0x439318 LDR	X8, [SP, #32]

        (833) 0x43931c LDR	X4, [X8]

        (833) 0x439320 BL	47a8e0

        (833) 0x439324 LDR	X12, [SP, #224]

        (833) 0x439328 LDR	X8, [X19]

        (833) 0x43932c CMP	X8, #1

        (833) 0x439330 B.LT	439394

        (833) 0x439334 LDUR	X8, [X29, #408]

        (833) 0x439338 LDR	X13, [SP, #48]

        (833) 0x43933c ORR	X9, XZR, XZR

        (833) 0x439340 LDR	X10, [X8]

          (836) 0x439344 LDR	X8, [X13]

          (836) 0x439348 LDR	X11, [X10, X9,LSL #3]

          (836) 0x43934c SUB	X8, X11, X8

          (836) 0x439350 STR	X8, [X10, X9,LSL #3]

          (836) 0x439354 ADD	X9, X9, #1

          (836) 0x439358 LDR	X8, [X19]

          (836) 0x43935c CMP	X9, X8

          (836) 0x439360 B.LT	439344

        (833) 0x439364 CMP	X8, #1

        (833) 0x439368 B.LT	439394

        (833) 0x43936c MOVN	X9, #0

        (833) 0x439370 ORR	X8, XZR, XZR

        (833) 0x439374 HINT	#0

        (833) 0x439378 HINT	#0

        (833) 0x43937c HINT	#0

          (835) 0x439380 STR	X9, [X22, X8,LSL #3]

          (835) 0x439384 ADD	X8, X8, #1

          (835) 0x439388 LDR	X10, [X19]

          (835) 0x43938c CMP	X8, X10

          (835) 0x439390 B.LT	439380

        (833) 0x439394 LDR	X8, [X12]

        (833) 0x439398 CMP	X8, #1

        (833) 0x43939c B.LT	4393bc

        (833) 0x4393a0 MOVN	X9, #0

        (833) 0x4393a4 ORR	X8, XZR, XZR

          (834) 0x4393a8 STR	X9, [X23, X8,LSL #3]

          (834) 0x4393ac ADD	X8, X8, #1

          (834) 0x4393b0 LDR	X10, [X12]

          (834) 0x4393b4 CMP	X8, X10

          (834) 0x4393b8 B.LT	4393a8

        (833) 0x4393bc ADRP	X0,

        (833) 0x4393c0 ADD	X0, X0, #1288

        (833) 0x4393c4 ORR	W1, WZR, W20

        (833) 0x4393c8 BL	40f440

        (833) 0x4393cc LDUR	X13, [X29, #384]

        (833) 0x4393d0 LDUR	X9, [X29, #320]

        (833) 0x4393d4 CMP	X13, X27

        (833) 0x4393d8 B.GT	43941c

        (833) 0x4393dc LDR	X8, [X19]

        (833) 0x4393e0 CBZ	X8, 4393ec

        (833) 0x4393e4 ORR	X0, XZR, X22

        (833) 0x4393e8 BL	4a6d90

        (833) 0x4393ec LDR	X8, [SP, #224]

        (833) 0x4393f0 LDR	X8, [X8]

        (833) 0x4393f4 CBZ	X8, 43a064

0x4393f8 ORR	X0, XZR, X23

0x4393fc ADD	SP, SP, #448

0x439400 LDP	X20, X19, [SP, #80]

0x439404 LDP	X22, X21, [SP, #64]

0x439408 LDP	X24, X23, [SP, #48]

0x43940c LDP	X26, X25, [SP, #32]

0x439410 LDP	X28, X27, [SP, #16]

0x439414 LDP	X29, X30, [SP], #96

0x439418 B	4a6d90

      (818) 0x43941c LDUR	X8, [X29, #448]

      (818) 0x439420 FMOV	D0, #1.0000000

      (818) 0x439424 FMOV	D1, #-1.0000000

      (818) 0x439428 MOVN	X7, #1

      (818) 0x43942c LDR	X14, [X8]

      (818) 0x439430 LDUR	X8, [X29, #464]

      (818) 0x439434 LDR	X8, [X8]

      (818) 0x439438 STR	X8, [SP, #184]

      (818) 0x43943c LDP	X11, X8, [X29, #880]

      (818) 0x439440 LDR	X10, [X11]

      (818) 0x439444 LDR	X11, [X8]

      (818) 0x439448 LDUR	X8, [X29, #416]

      (818) 0x43944c LDR	X12, [X8]

      (818) 0x439450 LDUR	X8, [X29, #304]

      (818) 0x439454 LDR	X26, [X8]

      (818) 0x439458 LDUR	X8, [X29, #352]

      (818) 0x43945c LDR	X8, [X8]

      (818) 0x439460 STUR	X8, [X29, #472]

      (818) 0x439464 LDUR	X8, [X29, #312]

      (818) 0x439468 LDR	X8, [X8]

      (818) 0x43946c STUR	X8, [X29, #464]

      (818) 0x439470 LDUR	X8, [X29, #336]

      (818) 0x439474 LDR	X8, [X8]

      (818) 0x439478 STUR	X8, [X29, #456]

      (818) 0x43947c LDR	X8, [SP, #160]

      (818) 0x439480 LDR	X15, [X8]

      (818) 0x439484 LDR	X8, [SP, #104]

      (818) 0x439488 LDR	X8, [X8]

      (818) 0x43948c STUR	X8, [X29, #424]

      (818) 0x439490 LDR	X8, [SP, #168]

      (818) 0x439494 LDR	X16, [X8]

      (818) 0x439498 LDR	X8, [SP, #128]

      (818) 0x43949c LDR	X8, [X8]

      (818) 0x4394a0 STR	X8, [SP, #104]

      (818) 0x4394a4 LDR	X8, [SP, #136]

      (818) 0x4394a8 STUR	X15, [X29, #488]

      (818) 0x4394ac ADD	X15, X15, #8

      (818) 0x4394b0 STUR	X15, [X29, #376]

      (818) 0x4394b4 ADD	X15, X16, #8

      (818) 0x4394b8 STUR	X15, [X29, #368]

      (818) 0x4394bc LDR	X8, [X8]

      (818) 0x4394c0 STUR	X8, [X29, #448]

      (818) 0x4394c4 LDUR	X8, [X29, #432]

      (818) 0x4394c8 LDR	X17, [X8]

      (818) 0x4394cc LDUR	X8, [X29, #400]

      (818) 0x4394d0 LDR	X8, [X8]

      (818) 0x4394d4 ADD	X15, X17, #16

      (818) 0x4394d8 STP	X15, X8, [SP, #64]

      (818) 0x4394dc ADD	X8, X8, #16

      (818) 0x4394e0 STR	X8, [SP, #56]

      (818) 0x4394e4 LDUR	X8, [X29, #408]

      (818) 0x4394e8 STUR	X26, [X29, #416]

      (818) 0x4394ec LDR	X15, [X8]

      (818) 0x4394f0 LDUR	X8, [X29, #392]

      (818) 0x4394f4 STR	X14, [SP, #192]

      (818) 0x4394f8 STUR	X16, [X29, #440]

      (818) 0x4394fc LDR	X18, [X8]

      (818) 0x439500 STP	X15, X17, [SP, #168]

      (818) 0x439504 STR	X18, [SP, #160]

      (818) 0x439508 B	43952c

      (818) 0x43950c LDR	D2, [X9]

      (818) 0x439510 LDR	X8, [X15, X27,LSL #3]

      (818) 0x439514 STR	X8, [X18, X5,LSL #3]

      (818) 0x439518 STR	D2, [X17, X5,LSL #3]

      (818) 0x43951c SUB	X7, X7, #1

      (818) 0x439520 ADD	X27, X27, #1

      (818) 0x439524 CMP	X27, X13

      (818) 0x439528 B.EQ	4393dc

      (818) 0x43952c LDR	X5, [X14, X27,LSL #3]

      (818) 0x439530 LDR	X8, [X10, X27,LSL #3]

      (818) 0x439534 TBZ	X8, #63, 43950c

      (818) 0x439538 CMN	X8, #3

      (818) 0x43953c B.EQ	43951c

    (819) 0x439540 LDR	X8, [SP, #184]

    (819) 0x439544 ADD	X30, X27, #1

    (819) 0x439548 SUB	X7, X7, #1

    (819) 0x43954c ORR	X6, XZR, X5

    (819) 0x439550 LDR	X13, [X11, X30,LSL #3]

    (819) 0x439554 LDR	X9, [X8, X27,LSL #3]

    (819) 0x439558 LDR	X8, [X11, X27,LSL #3]

    (819) 0x43955c ORR	X1, XZR, X9

    (819) 0x439560 CMP	X8, X13

    (819) 0x439564 B.GE	439718

    (819) 0x439568 LDP	X15, X13, [X29, #816]

    (819) 0x43956c ORR	X6, XZR, X5

    (819) 0x439570 ORR	X1, XZR, X9

    (819) 0x439574 LDR	X16, [X13]

    (819) 0x439578 LDUR	X13, [X29, #336]

    (819) 0x43957c LDR	X14, [X15]

    (819) 0x439580 LDR	X2, [X13]

    (819) 0x439584 LDUR	X13, [X29, #408]

    (819) 0x439588 LDR	X3, [X13]

    (819) 0x43958c LDUR	X13, [X29, #392]

    (819) 0x439590 LDR	X4, [X13]

    (819) 0x439594 LDUR	X13, [X29, #432]

    (819) 0x439598 LDR	X19, [X13]

    (819) 0x43959c B	4395b4

      (830) 0x4395a0 LDUR	X26, [X29, #416]

      (830) 0x4395a4 LDR	X13, [X11, X30,LSL #3]

      (830) 0x4395a8 ADD	X8, X8, #1

      (830) 0x4395ac CMP	X8, X13

      (830) 0x4395b0 B.GE	439718

      (830) 0x4395b4 LDR	X21, [X12, X8,LSL #3]

      (830) 0x4395b8 LDR	X13, [X10, X21,LSL #3]

      (830) 0x4395bc TBNZ	X13, #63, 4395ec

      (830) 0x4395c0 LDR	X13, [X22, X21,LSL #3]

      (830) 0x4395c4 CMP	X13, X5

      (830) 0x4395c8 B.GE	4395a4

      (830) 0x4395cc STR	X6, [X22, X21,LSL #3]

      (830) 0x4395d0 LDR	X13, [X3, X21,LSL #3]

      (830) 0x4395d4 STR	X13, [X4, X6,LSL #3]

      (830) 0x4395d8 LDUR	X13, [X29, #496]

      (830) 0x4395dc LDR	D2, [X13]

      (830) 0x4395e0 STR	D2, [X19, X6,LSL #3]

      (830) 0x4395e4 ADD	X6, X6, #1

      (830) 0x4395e8 B	4395a4

      (830) 0x4395ec CMN	X13, #3

      (830) 0x4395f0 B.EQ	4395a4

      (830) 0x4395f4 STR	X7, [X22, X21,LSL #3]

      (830) 0x4395f8 ADD	X20, X21, #1

      (830) 0x4395fc LDR	X13, [X11, X21,LSL #3]

      (830) 0x439600 LDR	X26, [X11, X20,LSL #3]

      (830) 0x439604 CMP	X13, X26

      (830) 0x439608 B.GE	439670

      (830) 0x43960c LDUR	X17, [X29, #392]

      (830) 0x439610 LDUR	X15, [X29, #408]

      (830) 0x439614 LDR	X18, [X17]

      (830) 0x439618 LDUR	X17, [X29, #432]

      (830) 0x43961c LDR	X15, [X15]

      (830) 0x439620 LDR	X0, [X17]

      (830) 0x439624 B	439634

        (832) 0x439628 ADD	X13, X13, #1

        (832) 0x43962c CMP	X13, X26

        (832) 0x439630 B.GE	439670

        (832) 0x439634 LDR	X17, [X12, X13,LSL #3]

        (832) 0x439638 LDR	X25, [X10, X17,LSL #3]

        (832) 0x43963c TBNZ	X25, #63, 439628

        (832) 0x439640 LDR	X25, [X22, X17,LSL #3]

        (832) 0x439644 CMP	X25, X5

        (832) 0x439648 B.GE	439628

        (832) 0x43964c STR	X6, [X22, X17,LSL #3]

        (832) 0x439650 LDR	X17, [X15, X17,LSL #3]

        (832) 0x439654 STR	X17, [X18, X6,LSL #3]

        (832) 0x439658 LDUR	X17, [X29, #496]

        (832) 0x43965c LDR	X26, [X11, X20,LSL #3]

        (832) 0x439660 LDR	D2, [X17]

        (832) 0x439664 STR	D2, [X0, X6,LSL #3]

        (832) 0x439668 ADD	X6, X6, #1

        (832) 0x43966c B	439628

      (830) 0x439670 LDUR	X13, [X29, #480]

      (830) 0x439674 LDR	X13, [X13]

      (830) 0x439678 CMP	X13, #2

      (830) 0x43967c B.LT	4395a0

      (830) 0x439680 LDR	X13, [X14, X21,LSL #3]

      (830) 0x439684 LDR	X18, [X14, X20,LSL #3]

      (830) 0x439688 CMP	X13, X18

      (830) 0x43968c B.GE	4395a0

      (830) 0x439690 LDUR	X15, [X29, #352]

      (830) 0x439694 LDUR	X0, [X29, #400]

      (830) 0x439698 LDR	X17, [X15]

      (830) 0x43969c LDUR	X15, [X29, #344]

      (830) 0x4396a0 LDR	X21, [X0]

      (830) 0x4396a4 LDR	X15, [X15]

      (830) 0x4396a8 ADD	X26, X17, X13,LSL #3

      (830) 0x4396ac B	4396d0

0x4396b0 HINT	#0

0x4396b4 HINT	#0

0x4396b8 HINT	#0

0x4396bc HINT	#0

        (831) 0x4396c0 ADD	X13, X13, #1

        (831) 0x4396c4 ADD	X26, X26, #8

        (831) 0x4396c8 CMP	X13, X18

        (831) 0x4396cc B.GE	4395a0

        (831) 0x4396d0 ORR	X17, XZR, X26

        (831) 0x4396d4 CBZ	X16, 4396e0

        (831) 0x4396d8 LDR	X17, [X26]

        (831) 0x4396dc ADD	X17, X16, X17,LSL #3

        (831) 0x4396e0 LDR	X17, [X17]

        (831) 0x4396e4 LDR	X0, [X2, X17,LSL #3]

        (831) 0x4396e8 TBNZ	X0, #63, 4396c0

        (831) 0x4396ec LDR	X0, [X23, X17,LSL #3]

        (831) 0x4396f0 CMP	X0, X9

        (831) 0x4396f4 B.GE	4396c0

        (831) 0x4396f8 STR	X1, [X23, X17,LSL #3]

        (831) 0x4396fc STR	X17, [X15, X1,LSL #3]

        (831) 0x439700 LDUR	X17, [X29, #496]

        (831) 0x439704 LDR	X18, [X14, X20,LSL #3]

        (831) 0x439708 LDR	D2, [X17]

        (831) 0x43970c STR	D2, [X21, X1,LSL #3]

        (831) 0x439710 ADD	X1, X1, #1

        (831) 0x439714 B	4396c0

    (819) 0x439718 LDUR	X8, [X29, #480]

    (819) 0x43971c LDR	X19, [X8]

    (819) 0x439720 CMP	X19, #2

    (819) 0x439724 B.LT	439894

    (819) 0x439728 LDR	X8, [X26, X27,LSL #3]

    (819) 0x43972c LDR	X13, [X26, X30,LSL #3]

    (819) 0x439730 CMP	X8, X13

    (819) 0x439734 B.GE	439894

    (819) 0x439738 LDP	X15, X13, [SP, #112]

    (819) 0x43973c LDR	X16, [X13]

    (819) 0x439740 LDUR	X13, [X29, #344]

    (819) 0x439744 LDR	X14, [X15]

    (819) 0x439748 LDR	X2, [X13]

    (819) 0x43974c LDUR	X13, [X29, #400]

    (819) 0x439750 LDR	X3, [X13]

    (819) 0x439754 B	439770

0x439758 HINT	#0

0x43975c HINT	#0

      (828) 0x439760 LDR	X13, [X26, X30,LSL #3]

      (828) 0x439764 ADD	X8, X8, #1

      (828) 0x439768 CMP	X8, X13

      (828) 0x43976c B.GE	43988c

      (828) 0x439770 LDP	X15, X13, [X29, #976]

      (828) 0x439774 LDR	X13, [X13, X8,LSL #3]

      (828) 0x439778 CBZ	X15, 439780

      (828) 0x43977c LDR	X13, [X15, X13,LSL #3]

      (828) 0x439780 LDUR	X15, [X29, #456]

      (828) 0x439784 LDR	X15, [X15, X13,LSL #3]

      (828) 0x439788 TBNZ	X15, #63, 4397c0

      (828) 0x43978c LDR	X15, [X23, X13,LSL #3]

      (828) 0x439790 CMP	X15, X9

      (828) 0x439794 B.GE	439760

      (828) 0x439798 STR	X1, [X23, X13,LSL #3]

      (828) 0x43979c STR	X13, [X2, X1,LSL #3]

      (828) 0x4397a0 LDUR	X13, [X29, #496]

      (828) 0x4397a4 LDR	D2, [X13]

      (828) 0x4397a8 STR	D2, [X3, X1,LSL #3]

      (828) 0x4397ac ADD	X1, X1, #1

      (828) 0x4397b0 B	439760

0x4397b4 HINT	#0

0x4397b8 HINT	#0

0x4397bc HINT	#0

      (828) 0x4397c0 CMN	X15, #3

      (828) 0x4397c4 B.EQ	439760

      (828) 0x4397c8 UBFM	X15, X13, #61, #60

      (828) 0x4397cc ADD	X4, X14, X13,LSL #3

      (828) 0x4397d0 STR	X7, [X23, X15]

      (828) 0x4397d4 LDP	X19, X13, [X4]

      (828) 0x4397d8 CMP	X19, X13

      (828) 0x4397dc B.GE	439760

      (828) 0x4397e0 LDUR	X13, [X29, #344]

      (828) 0x4397e4 LDR	X20, [X13]

      (828) 0x4397e8 LDP	X15, X13, [X29, #912]

      (828) 0x4397ec LDR	X21, [X15]

      (828) 0x4397f0 LDUR	X15, [X29, #392]

      (828) 0x4397f4 LDR	X13, [X13]

      (828) 0x4397f8 LDR	X18, [X15]

      (828) 0x4397fc LDUR	X15, [X29, #432]

      (828) 0x439800 LDR	X15, [X15]

      (828) 0x439804 B	439818

        (829) 0x439808 LDR	X17, [X4, #8]

        (829) 0x43980c ADD	X19, X19, #1

        (829) 0x439810 CMP	X19, X17

        (829) 0x439814 B.GE	439760

        (829) 0x439818 LDR	X17, [X16, X19,LSL #3]

        (829) 0x43981c LDR	X0, [X28]

        (829) 0x439820 LDR	X25, [X24]

        (829) 0x439824 SUBS	X0, X17, X0

        (829) 0x439828 CCMP	X17, X25, #0, #10

        (829) 0x43982c B.LT	439860

        (829) 0x439830 ORN	X17, XZR, X17

        (829) 0x439834 LDR	X0, [X23, X17,LSL #3]

        (829) 0x439838 CMP	X0, X9

        (829) 0x43983c B.GE	439808

        (829) 0x439840 STR	X1, [X23, X17,LSL #3]

        (829) 0x439844 STR	X17, [X20, X1,LSL #3]

        (829) 0x439848 LDUR	X17, [X29, #496]

        (829) 0x43984c LDR	D2, [X17]

        (829) 0x439850 STR	D2, [X21, X1,LSL #3]

        (829) 0x439854 ADD	X1, X1, #1

        (829) 0x439858 B	439808

0x43985c HINT	#0

        (829) 0x439860 LDR	X17, [X22, X0,LSL #3]

        (829) 0x439864 CMP	X17, X5

        (829) 0x439868 B.GE	439808

        (829) 0x43986c STR	X6, [X22, X0,LSL #3]

        (829) 0x439870 LDR	X17, [X13, X0,LSL #3]

        (829) 0x439874 STR	X17, [X18, X6,LSL #3]

        (829) 0x439878 LDUR	X17, [X29, #496]

        (829) 0x43987c LDR	D2, [X17]

        (829) 0x439880 STR	D2, [X15, X6,LSL #3]

        (829) 0x439884 ADD	X6, X6, #1

        (829) 0x439888 B	439808

    (819) 0x43988c LDUR	X8, [X29, #480]

    (819) 0x439890 LDR	X19, [X8]

    (819) 0x439894 LDUR	X14, [X29, #424]

    (819) 0x439898 LDUR	X13, [X29, #488]

    (819) 0x43989c LDUR	X15, [X29, #440]

    (819) 0x4398a0 LDR	X8, [X14, X27,LSL #3]

    (819) 0x4398a4 LDR	X4, [X14, X30,LSL #3]

    (819) 0x4398a8 LDR	D2, [X13, X8,LSL #3]

    (819) 0x4398ac ADD	X3, X8, #1

    (819) 0x4398b0 CMP	X3, X4

    (819) 0x4398b4 B.GE	439cec

    (819) 0x4398b8 LDP	X14, X13, [SP, #144]

    (819) 0x4398bc LDUR	X8, [X29, #432]

    (819) 0x4398c0 LDR	X25, [X14]

    (819) 0x4398c4 LDR	X14, [X13]

    (819) 0x4398c8 LDR	X13, [SP, #128]

    (819) 0x4398cc LDR	X8, [X8]

    (819) 0x4398d0 LDR	X26, [X13]

    (819) 0x4398d4 LDR	X13, [SP, #136]

    (819) 0x4398d8 LDR	X13, [X13]

    (819) 0x4398dc STP	X13, X14, [SP, #208]

    (819) 0x4398e0 ADD	X13, X13, #8

    (819) 0x4398e4 STR	X13, [SP, #200]

    (819) 0x4398e8 B	43990c

      (823) 0x4398ec LDUR	X14, [X29, #488]

      (823) 0x4398f0 LDR	D4, [X8, X13,LSL #3]

      (823) 0x4398f4 LDR	D3, [X14, X3,LSL #3]

      (823) 0x4398f8 FADD	D3, D4, D3

      (823) 0x4398fc STR	D3, [X8, X13,LSL #3]

      (823) 0x439900 ADD	X3, X3, #1

      (823) 0x439904 CMP	X3, X4

      (823) 0x439908 B.EQ	439cec

      (823) 0x43990c LDR	X20, [X15, X3,LSL #3]

      (823) 0x439910 LDR	X13, [X22, X20,LSL #3]

      (823) 0x439914 CMP	X13, X5

      (823) 0x439918 B.GE	4398ec

      (823) 0x43991c CMP	X13, X7

      (823) 0x439920 B.NE	4399a0

      (823) 0x439924 LDUR	X13, [X29, #496]

      (823) 0x439928 LDUR	X15, [X29, #424]

      (823) 0x43992c ADD	X21, X20, #1

      (823) 0x439930 LDR	D4, [X13]

      (823) 0x439934 LDR	X14, [X15, X20,LSL #3]

      (823) 0x439938 LDUR	X13, [X29, #488]

      (823) 0x43993c LDR	X16, [X15, X21,LSL #3]

      (823) 0x439940 LDR	D3, [X13, X14,LSL #3]

      (823) 0x439944 ADD	X2, X14, #1

      (823) 0x439948 FCMP	D3, #0

      (823) 0x43994c FCSEL	D3, D1, D0, #11

      (823) 0x439950 CMP	X2, X16

      (823) 0x439954 B.GE	4399e8

      (823) 0x439958 SUB	W13, W14, W16

      (823) 0x43995c TBNZ	W13, #0, 4399d8

      (823) 0x439960 LDUR	X13, [X29, #440]

      (823) 0x439964 LDR	X13, [X13, X2,LSL #3]

      (823) 0x439968 LDR	X15, [X22, X13,LSL #3]

      (823) 0x43996c CMP	X13, X27

      (823) 0x439970 CCMP	X15, X5, #0, #1

      (823) 0x439974 B.LT	439990

      (823) 0x439978 LDUR	X13, [X29, #488]

      (823) 0x43997c LDR	D5, [X13, X2,LSL #3]

      (823) 0x439980 FMUL	D6, D5, D3

      (823) 0x439984 FCMP	D6, #0

      (823) 0x439988 B.GE	439990

      (823) 0x43998c FADD	D4, D5, D4

      (823) 0x439990 ADD	X18, X14, #2

      (823) 0x439994 B	4399dc

0x439998 HINT	#0

0x43999c HINT	#0

      (823) 0x4399a0 LDR	X13, [X10, X20,LSL #3]

      (823) 0x4399a4 CMN	X13, #3

      (823) 0x4399a8 B.EQ	439900

      (823) 0x4399ac CMP	X25, #1

      (823) 0x4399b0 B.EQ	4399c8

      (823) 0x4399b4 LDR	X14, [SP, #216]

      (823) 0x4399b8 LDR	X13, [X14, X27,LSL #3]

      (823) 0x4399bc LDR	X14, [X14, X20,LSL #3]

      (823) 0x4399c0 CMP	X13, X14

      (823) 0x4399c4 B.NE	439900

      (823) 0x4399c8 LDUR	X13, [X29, #488]

      (823) 0x4399cc LDR	D3, [X13, X3,LSL #3]

      (823) 0x4399d0 FADD	D2, D3, D2

      (823) 0x4399d4 B	439900

      (823) 0x4399d8 ORR	X18, XZR, X2

      (823) 0x4399dc SUB	X13, X16, #2

      (823) 0x4399e0 CMP	X13, X14

      (823) 0x4399e4 B.NE	439a18

      (823) 0x4399e8 CMP	X19, #2

      (823) 0x4399ec B.LT	439ac8

      (823) 0x4399f0 LDR	X15, [X26, X20,LSL #3]

      (823) 0x4399f4 LDR	X13, [X26, X21,LSL #3]

      (823) 0x4399f8 CMP	X13, X15

      (823) 0x4399fc B.LE	439ac8

      (823) 0x439a00 LDUR	X17, [X29, #360]

      (823) 0x439a04 LDR	X18, [X17]

      (823) 0x439a08 SUB	W17, W13, W15

      (823) 0x439a0c TBNZ	W17, #0, 439a90

      (823) 0x439a10 ORR	X0, XZR, X15

      (823) 0x439a14 B	439abc

      (823) 0x439a18 LDP	X17, X15, [X29, #880]

      (823) 0x439a1c SUB	X13, X16, X18

      (823) 0x439a20 ADD	X15, X15, X18,LSL #3

      (823) 0x439a24 ADD	X18, X17, X18,LSL #3

      (823) 0x439a28 B	439a3c

        (827) 0x439a2c ADD	X18, X18, #16

        (827) 0x439a30 SUBS	X13, X13, #2

        (827) 0x439a34 ADD	X15, X15, #16

        (827) 0x439a38 B.EQ	4399e8

        (827) 0x439a3c LDUR	X17, [X18, #504]

        (827) 0x439a40 LDR	X0, [X22, X17,LSL #3]

        (827) 0x439a44 CMP	X17, X27

        (827) 0x439a48 CCMP	X0, X5, #0, #1

        (827) 0x439a4c B.LT	439a64

        (827) 0x439a50 LDUR	D5, [X15, #504]

        (827) 0x439a54 FMUL	D6, D5, D3

        (827) 0x439a58 FCMP	D6, #0

        (827) 0x439a5c B.GE	439a64

        (827) 0x439a60 FADD	D4, D5, D4

        (827) 0x439a64 LDR	X17, [X18]

        (827) 0x439a68 LDR	X0, [X22, X17,LSL #3]

        (827) 0x439a6c CMP	X17, X27

        (827) 0x439a70 CCMP	X0, X5, #0, #1

        (827) 0x439a74 B.LT	439a2c

        (827) 0x439a78 LDR	D5, [X15]

        (827) 0x439a7c FMUL	D6, D5, D3

        (827) 0x439a80 FCMP	D6, #0

        (827) 0x439a84 B.GE	439a2c

        (827) 0x439a88 FADD	D4, D5, D4

        (827) 0x439a8c B	439a2c

      (823) 0x439a90 LDR	X17, [SP, #208]

      (823) 0x439a94 LDR	X17, [X17, X15,LSL #3]

      (823) 0x439a98 LDR	X17, [X23, X17,LSL #3]

      (823) 0x439a9c CMP	X17, X9

      (823) 0x439aa0 B.LT	439ab8

      (823) 0x439aa4 LDR	D5, [X18, X15,LSL #3]

      (823) 0x439aa8 FMUL	D6, D5, D3

      (823) 0x439aac FCMP	D6, #0

      (823) 0x439ab0 B.GE	439ab8

      (823) 0x439ab4 FADD	D4, D5, D4

      (823) 0x439ab8 ADD	X0, X15, #1

      (823) 0x439abc ADD	X15, X15, #1

      (823) 0x439ac0 CMP	X13, X15

      (823) 0x439ac4 B.NE	439ba0

      (823) 0x439ac8 LDUR	X13, [X29, #488]

      (823) 0x439acc FCMP	D4, #0

      (823) 0x439ad0 LDR	D5, [X13, X3,LSL #3]

      (823) 0x439ad4 B.EQ	439b94

      (823) 0x439ad8 FDIV	D4, D5, D4

      (823) 0x439adc CMP	X2, X16

      (823) 0x439ae0 B.GE	439b5c

      (823) 0x439ae4 LDUR	X13, [X29, #432]

      (823) 0x439ae8 ORN	X15, XZR, X14

      (823) 0x439aec ADD	X15, X15, X16

      (823) 0x439af0 LDP	X16, X17, [X29, #880]

      (823) 0x439af4 LDR	X13, [X13]

      (823) 0x439af8 ADD	X16, X16, X14,LSL #3

      (823) 0x439afc ADD	X14, X17, X14,LSL #3

      (823) 0x439b00 B	439b10

        (825) 0x439b04 SUBS	X15, X15, #1

        (825) 0x439b08 ADD	X14, X14, #8

        (825) 0x439b0c B.EQ	439b5c

        (825) 0x439b10 LDR	X18, [X16], #8

        (825) 0x439b14 LDR	X0, [X22, X18,LSL #3]

        (825) 0x439b18 CMP	X0, X5

        (825) 0x439b1c B.LT	439b3c

        (825) 0x439b20 LDR	D5, [X14]

        (825) 0x439b24 FMUL	D6, D5, D3

        (825) 0x439b28 FCMP	D6, #0

        (825) 0x439b2c B.GE	439b3c

        (825) 0x439b30 LDR	D6, [X13, X0,LSL #3]

        (825) 0x439b34 FMADD	D5, D5, D4, D6

        (825) 0x439b38 STR	D5, [X13, X0,LSL #3]

        (825) 0x439b3c CMP	X18, X27

        (825) 0x439b40 B.NE	439b04

        (825) 0x439b44 LDR	D5, [X14]

        (825) 0x439b48 FMUL	D6, D5, D3

        (825) 0x439b4c FCMP	D6, #0

        (825) 0x439b50 B.GE	439b04

        (825) 0x439b54 FMADD	D2, D5, D4, D2

        (825) 0x439b58 B	439b04

      (823) 0x439b5c CMP	X19, #2

      (823) 0x439b60 B.LT	439c5c

      (823) 0x439b64 LDR	X15, [X26, X20,LSL #3]

      (823) 0x439b68 LDR	X13, [X26, X21,LSL #3]

      (823) 0x439b6c CMP	X13, X15

      (823) 0x439b70 B.LE	439c5c

      (823) 0x439b74 LDUR	X14, [X29, #360]

      (823) 0x439b78 SUB	W17, W13, W15

      (823) 0x439b7c LDR	X16, [X14]

      (823) 0x439b80 LDUR	X14, [X29, #400]

      (823) 0x439b84 LDR	X14, [X14]

      (823) 0x439b88 TBNZ	W17, #0, 439c1c

      (823) 0x439b8c ORR	X18, XZR, X15

      (823) 0x439b90 B	439c50

      (823) 0x439b94 LDUR	X15, [X29, #440]

      (823) 0x439b98 FADD	D2, D5, D2

      (823) 0x439b9c B	439900

      (823) 0x439ba0 LDR	X15, [SP, #200]

      (823) 0x439ba4 ADD	X17, X18, X0,LSL #3

      (823) 0x439ba8 SUB	X13, X13, X0

      (823) 0x439bac ADD	X18, X17, #8

      (823) 0x439bb0 ADD	X15, X15, X0,LSL #3

      (823) 0x439bb4 B	439bd0

0x439bb8 HINT	#0

0x439bbc HINT	#0

        (826) 0x439bc0 SUBS	X13, X13, #2

        (826) 0x439bc4 ADD	X15, X15, #16

        (826) 0x439bc8 ADD	X18, X18, #16

        (826) 0x439bcc B.EQ	439ac8

        (826) 0x439bd0 LDUR	X17, [X15, #504]

        (826) 0x439bd4 LDR	X17, [X23, X17,LSL #3]

        (826) 0x439bd8 CMP	X17, X9

        (826) 0x439bdc B.LT	439bf4

        (826) 0x439be0 LDUR	D5, [X18, #504]

        (826) 0x439be4 FMUL	D6, D5, D3

        (826) 0x439be8 FCMP	D6, #0

        (826) 0x439bec B.GE	439bf4

        (826) 0x439bf0 FADD	D4, D5, D4

        (826) 0x439bf4 LDR	X17, [X15]

        (826) 0x439bf8 LDR	X17, [X23, X17,LSL #3]

        (826) 0x439bfc CMP	X17, X9

        (826) 0x439c00 B.LT	439bc0

        (826) 0x439c04 LDR	D5, [X18]

        (826) 0x439c08 FMUL	D6, D5, D3

        (826) 0x439c0c FCMP	D6, #0

        (826) 0x439c10 B.GE	439bc0

        (826) 0x439c14 FADD	D4, D5, D4

        (826) 0x439c18 B	439bc0

      (823) 0x439c1c LDR	X17, [SP, #208]

      (823) 0x439c20 LDR	X17, [X17, X15,LSL #3]

      (823) 0x439c24 LDR	X18, [X23, X17,LSL #3]

      (823) 0x439c28 CMP	X18, X9

      (823) 0x439c2c B.LT	439c4c

      (823) 0x439c30 LDR	D5, [X16, X15,LSL #3]

      (823) 0x439c34 FMUL	D6, D5, D3

      (823) 0x439c38 FCMP	D6, #0

      (823) 0x439c3c B.GE	439c4c

      (823) 0x439c40 LDR	D6, [X14, X18,LSL #3]

      (823) 0x439c44 FMADD	D5, D5, D4, D6

      (823) 0x439c48 STR	D5, [X14, X18,LSL #3]

      (823) 0x439c4c ADD	X18, X15, #1

      (823) 0x439c50 ADD	X15, X15, #1

      (823) 0x439c54 CMP	X13, X15

      (823) 0x439c58 B.NE	439c64

      (823) 0x439c5c LDUR	X15, [X29, #440]

      (823) 0x439c60 B	439900

      (823) 0x439c64 LDR	X15, [SP, #200]

      (823) 0x439c68 ADD	X16, X16, X18,LSL #3

      (823) 0x439c6c SUB	X13, X13, X18

      (823) 0x439c70 ADD	X16, X16, #8

      (823) 0x439c74 ADD	X15, X15, X18,LSL #3

      (823) 0x439c78 B	439c90

0x439c7c HINT	#0

        (824) 0x439c80 SUBS	X13, X13, #2

        (824) 0x439c84 ADD	X15, X15, #16

        (824) 0x439c88 ADD	X16, X16, #16

        (824) 0x439c8c B.EQ	439c5c

        (824) 0x439c90 LDUR	X17, [X15, #504]

        (824) 0x439c94 LDR	X18, [X23, X17,LSL #3]

        (824) 0x439c98 CMP	X18, X9

        (824) 0x439c9c B.LT	439cbc

        (824) 0x439ca0 LDUR	D5, [X16, #504]

        (824) 0x439ca4 FMUL	D6, D5, D3

        (824) 0x439ca8 FCMP	D6, #0

        (824) 0x439cac B.GE	439cbc

        (824) 0x439cb0 LDR	D6, [X14, X18,LSL #3]

        (824) 0x439cb4 FMADD	D5, D5, D4, D6

        (824) 0x439cb8 STR	D5, [X14, X18,LSL #3]

        (824) 0x439cbc LDR	X17, [X15]

        (824) 0x439cc0 LDR	X18, [X23, X17,LSL #3]

        (824) 0x439cc4 CMP	X18, X9

        (824) 0x439cc8 B.LT	439c80

        (824) 0x439ccc LDR	D5, [X16]

        (824) 0x439cd0 FMUL	D6, D5, D3

        (824) 0x439cd4 FCMP	D6, #0

        (824) 0x439cd8 B.GE	439c80

        (824) 0x439cdc LDR	D6, [X14, X18,LSL #3]

        (824) 0x439ce0 FMADD	D5, D5, D4, D6

        (824) 0x439ce4 STR	D5, [X14, X18,LSL #3]

        (824) 0x439ce8 B	439c80

    (819) 0x439cec CMP	X19, #2

    (819) 0x439cf0 B.LT	439f20

    (819) 0x439cf4 LDR	X13, [SP, #104]

    (819) 0x439cf8 LDR	X8, [X13, X27,LSL #3]

    (819) 0x439cfc LDR	X14, [X13, X30,LSL #3]

    (819) 0x439d00 CMP	X8, X14

    (819) 0x439d04 B.GE	439f20

  (820) 0x439d08 LDUR	X13, [X29, #360]

  (820) 0x439d0c LDR	X19, [X28]

  (820) 0x439d10 LDR	X16, [X13]

  (820) 0x439d14 LDUR	X13, [X29, #400]

  (820) 0x439d18 LDR	X2, [X13]

  (820) 0x439d1c LDUR	X13, [X29, #336]

  (820) 0x439d20 LDR	X3, [X13]

  (820) 0x439d24 LDR	X13, [SP, #144]

  (820) 0x439d28 LDR	X15, [X13]

  (820) 0x439d2c LDR	X13, [SP, #152]

  (820) 0x439d30 LDR	X13, [X13]

  (820) 0x439d34 STP	X13, X15, [SP, #208]

  (820) 0x439d38 LDR	X13, [SP, #96]

  (820) 0x439d3c LDR	X13, [X13]

  (820) 0x439d40 STR	X13, [SP, #200]

  (820) 0x439d44 LDP	X15, X13, [SP, #80]

  (820) 0x439d48 LDR	X21, [X15]

  (820) 0x439d4c LDR	X30, [X13]

  (820) 0x439d50 ADD	X26, X21, #8

  (820) 0x439d54 B	439d7c

0x439d58 HINT	#0

0x439d5c HINT	#0

  (820) 0x439d60 LDR	D3, [X16, X8,LSL #3]

  (820) 0x439d64 LDR	D4, [X2, X15,LSL #3]

  (820) 0x439d68 FADD	D3, D4, D3

  (820) 0x439d6c STR	D3, [X2, X15,LSL #3]

  (820) 0x439d70 ADD	X8, X8, #1

  (820) 0x439d74 CMP	X8, X14

  (820) 0x439d78 B.EQ	439f20

  (820) 0x439d7c LDUR	X13, [X29, #448]

  (820) 0x439d80 LDR	X13, [X13, X8,LSL #3]

  (820) 0x439d84 LDR	X15, [X23, X13,LSL #3]

  (820) 0x439d88 CMP	X15, X9

  (820) 0x439d8c B.GE	439d60

  (820) 0x439d90 CMP	X15, X7

  (820) 0x439d94 B.NE	439e20

  (820) 0x439d98 LDUR	X15, [X29, #496]

  (820) 0x439d9c LDR	D3, [X15]

  (820) 0x439da0 LDR	X15, [X21, X13,LSL #3]

  (820) 0x439da4 LDR	X13, [X26, X13,LSL #3]

  (820) 0x439da8 CMP	X13, X15

  (820) 0x439dac B.LE	439e50

  (820) 0x439db0 LDUR	X17, [X29, #296]

  (820) 0x439db4 LDR	X18, [X24]

  (820) 0x439db8 ORR	X4, XZR, X15

  (820) 0x439dbc LDR	X0, [X17]

  (820) 0x439dc0 B	439dd8

    (822) 0x439dc4 LDR	D4, [X0, X4,LSL #3]

    (822) 0x439dc8 FADD	D3, D4, D3

    (822) 0x439dcc ADD	X4, X4, #1

    (822) 0x439dd0 CMP	X13, X4

    (822) 0x439dd4 B.EQ	439e5c

    (822) 0x439dd8 LDR	X17, [X30, X4,LSL #3]

    (822) 0x439ddc SUBS	X20, X17, X19

    (822) 0x439de0 CCMP	X17, X18, #0, #10

    (822) 0x439de4 B.LT	439e00

    (822) 0x439de8 ORN	X17, XZR, X17

    (822) 0x439dec LDR	X17, [X23, X17,LSL #3]

    (822) 0x439df0 CMP	X17, X9

    (822) 0x439df4 B.GE	439dc4

    (822) 0x439df8 B	439dcc

0x439dfc HINT	#0

    (822) 0x439e00 LDR	X17, [X22, X20,LSL #3]

    (822) 0x439e04 CMP	X20, X27

    (822) 0x439e08 CCMP	X17, X5, #0, #1

    (822) 0x439e0c B.LT	439dcc

    (822) 0x439e10 B	439dc4

0x439e14 HINT	#0

0x439e18 HINT	#0

0x439e1c HINT	#0

  (820) 0x439e20 LDR	X15, [X3, X13,LSL #3]

  (820) 0x439e24 CMN	X15, #3

  (820) 0x439e28 B.EQ	439d70

  (820) 0x439e2c LDR	X15, [SP, #216]

  (820) 0x439e30 CMP	X15, #1

  (820) 0x439e34 B.EQ	439f14

  (820) 0x439e38 LDP	X17, X15, [SP, #200]

  (820) 0x439e3c LDR	X15, [X15, X27,LSL #3]

  (820) 0x439e40 LDR	X13, [X17, X13,LSL #3]

  (820) 0x439e44 CMP	X15, X13

  (820) 0x439e48 B.NE	439d70

  (820) 0x439e4c B	439f14

  (820) 0x439e50 FCMP	D3, #0

  (820) 0x439e54 B.NE	439d70

  (820) 0x439e58 B	439f14

  (820) 0x439e5c FCMP	D3, #0

  (820) 0x439e60 B.EQ	439f14

  (820) 0x439e64 SUBS	X20, X13, X15

  (820) 0x439e68 B.LE	439d70

(821) 0x439e6c LDR	D4, [X16, X8,LSL #3]

(821) 0x439e70 LDUR	X13, [X29, #296]

(821) 0x439e74 ADD	X18, X30, X15,LSL #3

(821) 0x439e78 LDR	X17, [X13]

(821) 0x439e7c LDUR	X13, [X29, #400]

(821) 0x439e80 FDIV	D3, D4, D3

(821) 0x439e84 LDR	X4, [X13]

(821) 0x439e88 LDUR	X13, [X29, #432]

(821) 0x439e8c ADD	X15, X17, X15,LSL #3

(821) 0x439e90 LDR	X13, [X13]

(821) 0x439e94 B	439eac

0x439e98 HINT	#0

0x439e9c HINT	#0

(821) 0x439ea0 ADD	X15, X15, #8

(821) 0x439ea4 SUBS	X20, X20, #1

(821) 0x439ea8 B.EQ	439d70

(821) 0x439eac LDR	X17, [X18], #8

(821) 0x439eb0 LDR	X25, [X24]

(821) 0x439eb4 SUBS	X0, X17, X19

(821) 0x439eb8 CCMP	X17, X25, #0, #10

(821) 0x439ebc B.LT	439ee4

(821) 0x439ec0 ORN	X17, XZR, X17

(821) 0x439ec4 LDR	X17, [X23, X17,LSL #3]

(821) 0x439ec8 CMP	X17, X9

(821) 0x439ecc B.LT	439ea0

(821) 0x439ed0 LDR	D4, [X15]

(821) 0x439ed4 LDR	D5, [X4, X17,LSL #3]

(821) 0x439ed8 FMADD	D4, D4, D3, D5

(821) 0x439edc STR	D4, [X4, X17,LSL #3]

(821) 0x439ee0 B	439ea0

(821) 0x439ee4 LDR	X17, [X22, X0,LSL #3]

(821) 0x439ee8 CMP	X17, X5

(821) 0x439eec B.LT	439f00

(821) 0x439ef0 LDR	D4, [X15]

(821) 0x439ef4 LDR	D5, [X13, X17,LSL #3]

(821) 0x439ef8 FMADD	D4, D4, D3, D5

(821) 0x439efc STR	D4, [X13, X17,LSL #3]

(821) 0x439f00 CMP	X0, X27

(821) 0x439f04 B.NE	439ea0

(821) 0x439f08 LDR	D4, [X15]

(821) 0x439f0c FMADD	D2, D4, D3, D2

(821) 0x439f10 B	439ea0

  (820) 0x439f14 LDR	D3, [X16, X8,LSL #3]

  (820) 0x439f18 FADD	D2, D3, D2

  (820) 0x439f1c B	439d70

    (819) 0x439f20 FCMP	D2, #0

    (819) 0x439f24 B.EQ	43a048

    (819) 0x439f28 LDUR	X19, [X29, #328]

    (819) 0x439f2c LDUR	X26, [X29, #416]

    (819) 0x439f30 LDR	X17, [SP, #176]

    (819) 0x439f34 SUBS	X8, X6, X5

    (819) 0x439f38 B.LE	439fb4

    (819) 0x439f3c CMP	X8, #3

    (819) 0x439f40 B.LS	439f94

    (819) 0x439f44 DUP	V3.2D, V2.D[0]

    (819) 0x439f48 FMOV	V4.2D, #1.0000000

    (819) 0x439f4c LDR	X15, [SP, #64]

    (819) 0x439f50 AND	X13, X8, #8062

    (819) 0x439f54 ADD	X14, X5, X13

    (819) 0x439f58 ORR	X16, XZR, X13

    (819) 0x439f5c FDIV	V3.2D, V4.2D, V3.2D

    (819) 0x439f60 ADD	X15, X15, X5,LSL #3

      (843) 0x439f64 LDP	Q4, Q5, [X15, #2032]

      (843) 0x439f68 SUBS	X16, X16, #4

      (843) 0x439f6c FNEG	V5.2D, V5.2D

      (843) 0x439f70 FNEG	V4.2D, V4.2D

      (843) 0x439f74 FMUL	V5.2D, V5.2D, V3.2D

      (843) 0x439f78 FMUL	V4.2D, V4.2D, V3.2D

      (843) 0x439f7c STP	Q4, Q5, [X15, #2032]

      (843) 0x439f80 ADD	X15, X15, #32

      (843) 0x439f84 B.NE	439f64

    (819) 0x439f88 ORR	X5, XZR, X14

    (819) 0x439f8c CMP	X8, X13

    (819) 0x439f90 B.EQ	439fb4

    (819) 0x439f94 FDIV	D3, D0, D2

    (819) 0x439f98 ADD	X8, X17, X5,LSL #3

    (819) 0x439f9c SUB	X13, X6, X5

      (842) 0x439fa0 LDR	D4, [X8]

      (842) 0x439fa4 SUBS	X13, X13, #1

      (842) 0x439fa8 FNMUL	D4, D4, D3

      (842) 0x439fac STR	D4, [X8], #8

      (842) 0x439fb0 B.NE	439fa0

    (819) 0x439fb4 SUBS	X8, X1, X9

    (819) 0x439fb8 B.LE	43a038

    (819) 0x439fbc CMP	X8, #3

    (819) 0x439fc0 B.LS	43a014

    (819) 0x439fc4 DUP	V3.2D, V2.D[0]

    (819) 0x439fc8 FMOV	V4.2D, #1.0000000

    (819) 0x439fcc LDR	X15, [SP, #56]

    (819) 0x439fd0 AND	X13, X8, #8062

    (819) 0x439fd4 ADD	X14, X9, X13

    (819) 0x439fd8 FDIV	V3.2D, V4.2D, V3.2D

    (819) 0x439fdc ADD	X9, X15, X9,LSL #3

    (819) 0x439fe0 ORR	X15, XZR, X13

      (841) 0x439fe4 LDP	Q4, Q5, [X9, #2032]

      (841) 0x439fe8 SUBS	X15, X15, #4

      (841) 0x439fec FNEG	V5.2D, V5.2D

      (841) 0x439ff0 FNEG	V4.2D, V4.2D

      (841) 0x439ff4 FMUL	V5.2D, V5.2D, V3.2D

      (841) 0x439ff8 FMUL	V4.2D, V4.2D, V3.2D

      (841) 0x439ffc STP	Q4, Q5, [X9, #2032]

      (841) 0x43a000 ADD	X9, X9, #32

      (841) 0x43a004 B.NE	439fe4

    (819) 0x43a008 ORR	X9, XZR, X14

    (819) 0x43a00c CMP	X8, X13

    (819) 0x43a010 B.EQ	43a038

    (819) 0x43a014 FDIV	D2, D0, D2

    (819) 0x43a018 LDR	X8, [SP, #72]

    (819) 0x43a01c ADD	X8, X8, X9,LSL #3

    (819) 0x43a020 SUB	X9, X1, X9

      (840) 0x43a024 LDR	D3, [X8]

      (840) 0x43a028 SUBS	X9, X9, #1

      (840) 0x43a02c FNMUL	D3, D3, D2

      (840) 0x43a030 STR	D3, [X8], #8

      (840) 0x43a034 B.NE	43a024

    (819) 0x43a038 LDUR	X9, [X29, #320]

    (819) 0x43a03c LDUR	X13, [X29, #384]

    (819) 0x43a040 LDR	X14, [SP, #192]

    (819) 0x43a044 B	43a05c

    (819) 0x43a048 LDP	X9, X19, [X29, #832]

    (819) 0x43a04c LDUR	X13, [X29, #384]

    (819) 0x43a050 LDR	X14, [SP, #192]

    (819) 0x43a054 LDUR	X26, [X29, #416]

    (819) 0x43a058 LDR	X17, [SP, #176]

    (819) 0x43a05c LDP	X18, X15, [SP, #160]

    (819) 0x43a060 B	43951c

        (833) 0x43a064 ADD	SP, SP, #448

        (833) 0x43a068 LDP	X20, X19, [SP, #80]

        (833) 0x43a06c LDP	X22, X21, [SP, #64]

        (833) 0x43a070 LDP	X24, X23, [SP, #48]

        (833) 0x43a074 LDP	X26, X25, [SP, #32]

        (833) 0x43a078 LDP	X28, X27, [SP, #16]

        (833) 0x43a07c LDP	X29, X30, [SP], #96

        (833) 0x43a080 RET

        (833) 0x43a084 LDR	X13, [SP, #72]

        (833) 0x43a088 UBFM	X17, X1, #61, #60

        (833) 0x43a08c ADD	X15, X15, X25,LSL #3

        (833) 0x43a090 ADD	X3, X16, X25,LSL #3

        (833) 0x43a094 ADD	X17, X17, #8

        (833) 0x43a098 ADD	X1, X11, X17

        (833) 0x43a09c ADD	X2, X12, X17

        (833) 0x43a0a0 MADD	X13, X25, X13, XZR

        (833) 0x43a0a4 UBFM	X14, X13, #61, #60

        (833) 0x43a0a8 ADD	X13, X14, #8

        (833) 0x43a0ac ADD	X0, X11, X13

        (833) 0x43a0b0 ADD	X13, X12, X13

        (833) 0x43a0b4 CMP	X0, X15

        (833) 0x43a0b8 CCMP	X9, X1, #2, #3

        (833) 0x43a0bc CSINC	W18, WZR, WZR, #2

        (833) 0x43a0c0 CMP	X0, X3

        (833) 0x43a0c4 CCMP	X10, X1, #2, #3

        (833) 0x43a0c8 CSINC	W17, WZR, WZR, #2

        (833) 0x43a0cc CMP	X13, X15

        (833) 0x43a0d0 CCMP	X9, X2, #2, #3

        (833) 0x43a0d4 CSINC	W16, WZR, WZR, #2

        (833) 0x43a0d8 CMP	X13, X3

        (833) 0x43a0dc CCMP	X10, X2, #2, #3

        (833) 0x43a0e0 CSINC	W15, WZR, WZR, #2

        (833) 0x43a0e4 CMP	X13, X1

        (833) 0x43a0e8 LDUR	X1, [X29, #384]

        (833) 0x43a0ec ORR	X13, XZR, X27

        (833) 0x43a0f0 CCMP	X0, X2, #2, #3

        (833) 0x43a0f4 B.CC	439148

        (833) 0x43a0f8 ORR	X13, XZR, X27

        (833) 0x43a0fc TBNZ	W18, #0, 439148

        (833) 0x43a100 ORR	X13, XZR, X27

        (833) 0x43a104 TBNZ	W17, #0, 439148

        (833) 0x43a108 ORR	X13, XZR, X27

        (833) 0x43a10c TBNZ	W16, #0, 439148

        (833) 0x43a110 ORR	X13, XZR, X27

        (833) 0x43a114 TBNZ	W15, #0, 439148

        (833) 0x43a118 LD1R	{V0.2D}, [X9]

        (833) 0x43a11c LD1R	{V1.2D}, [X10]

        (833) 0x43a120 AND	X15, X8, #8127

        (833) 0x43a124 ADD	X16, X14, #8

        (833) 0x43a128 ADD	X13, X27, X15

        (833) 0x43a12c ADD	X14, X12, X16

        (833) 0x43a130 ADD	X16, X11, X16

        (833) 0x43a134 ORR	X17, XZR, X15

        (833) 0x43a138 HINT	#0

        (833) 0x43a13c HINT	#0

          (839) 0x43a140 LDR	Q2, [X16]

          (839) 0x43a144 SUBS	X17, X17, #2

          (839) 0x43a148 ADD	V2.2D, V2.2D, V0.2D

          (839) 0x43a14c STR	Q2, [X16], #16

          (839) 0x43a150 LDR	Q2, [X14]

          (839) 0x43a154 ADD	V2.2D, V2.2D, V1.2D

          (839) 0x43a158 STR	Q2, [X14], #16

          (839) 0x43a15c B.NE	43a140

        (833) 0x43a160 CMP	X8, X15

        (833) 0x43a164 B.NE	439148

        (833) 0x43a168 B	439188

        (833) 0x43a16c LDUR	X9, [X29, #408]

        (833) 0x43a170 LDR	X11, [SP, #72]

        (833) 0x43a174 LDR	X10, [X9]

        (833) 0x43a178 LDR	X9, [X21]

        (833) 0x43a17c MADD	X11, X25, X11, XZR

        (833) 0x43a180 ADD	X9, X9, X25,LSL #3

        (833) 0x43a184 ADD	X10, X10, X11,LSL #3

        (833) 0x43a188 B	43a198

          (838) 0x43a18c ADD	X10, X10, #8

          (838) 0x43a190 SUBS	X8, X8, #1

          (838) 0x43a194 B.EQ	439190

          (838) 0x43a198 LDR	X11, [X10]

          (838) 0x43a19c TBNZ	X11, #63, 43a18c

          (838) 0x43a1a0 LDUR	X12, [X9, #504]

          (838) 0x43a1a4 ADD	X11, X12, X11

          (838) 0x43a1a8 STR	X11, [X10]

          (838) 0x43a1ac B	43a18c

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

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Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	par_lr_interp.c:1196-1757
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1196,1219-1238,1244-1254,1262-1303,1311-1350,1363-1417,1423-1459,1467-1471,1480-1483,1491-1496,1503-1545,1553-1596,1607-1660,1667-1724,1733-1748,1754-1757.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 51.83 to 41.08 cycles (1.26x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 51.83 to 3.50 cycles (14.81x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 908 bytes. The binary function is storing 576 bytes.

General properties

nb instructions	289
loop length	1156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	12.50	12.50	12.00	12.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	51.83	51.50	51.67	30.50	30.50
cycles	12.50	12.50	12.00	12.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	51.83	51.50	51.67	30.50	30.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	30.13
Overall L1	51.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 51.83 cycles. At this rate:

18% of peak load performance is reached (17.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 438a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X7, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X6, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X21, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X28, X24, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X10, [X29, #816]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X11, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 438b7c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 438b74 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 438b7c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X26, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 438bd8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 438bd8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
B 438bd8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X19, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X27, X10, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X14, X8, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X14, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X14, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 438d34 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X28, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dcc28>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W28, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4dcc4c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W20, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X19, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 4390ec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 4390ec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X9, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X11, X14, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W12, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X11, X15, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W13, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X9, X15, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 4390a8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W12, #0, 4390a8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W13, 4390a8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X9], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X11], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X10], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4390ec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X16, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 438dc0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD X11, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <4dc0ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X1, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X25, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439190 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X1, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 439190 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X13, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X16, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X16, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 43a084 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD SP, SP, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 4a6d90 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	par_lr_interp.c:1196-1757
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 51.83 to 3.50 cycles (14.81x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 908 bytes. The binary function is storing 576 bytes.

General properties

nb instructions	289
loop length	1156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	12.50	12.50	12.00	12.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	51.83	51.50	51.67	30.50	30.50
cycles	12.50	12.50	12.00	12.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	51.83	51.50	51.67	30.50	30.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	30.13
Overall L1	51.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 51.83 cycles. At this rate:

18% of peak load performance is reached (17.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 438a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X7, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X6, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X21, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X28, X24, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X10, [X29, #816]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X11, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 438b7c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 438b74 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 438b7c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X26, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 438bd8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 438bd8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
B 438bd8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4a8a10 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a89f0 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X19, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X27, X10, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X14, X8, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X14, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X14, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 438d34 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X28, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dcc28>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W28, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4dcc4c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W20, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X19, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 4390ec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 4390ec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X9, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X11, X14, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W12, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X11, X15, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W13, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X9, X15, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 4390a8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W12, #0, 4390a8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W13, 4390a8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X9], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X11], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X10], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4390ec <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X16, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 438dc0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD X11, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <4dc0ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f440 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X1, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X25, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 439190 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X1, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 439190 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X13, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X16, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X16, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 43a084 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1684>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD SP, SP, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 4a6d90 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildExtPIInterp.omp_outlined–	0.23	0.05
○Loop 855 - par_lr_interp.c:1224-1225 - exec	0.01	0.00
▼Loop 849 - par_lr_interp.c:1244-1350 - exec–	0.00	0.00
▼Loop 850 - par_lr_interp.c:1244-1350 - exec–	0.00	0.00
▼Loop 848 - par_lr_interp.c:1244-1341 - exec–	0.00	0.00
▼Loop 847 - par_lr_interp.c:1244-1341 - exec–	0.00	0.00
▼Loop 851 - par_lr_interp.c:1264-1303 - exec–	0.00	0.01
○Loop 853 - par_lr_interp.c:1277-1285 - exec	0.02	0.01
○Loop 852 - par_lr_interp.c:1291-1303 - exec	0.00	0.00
○Loop 846 - par_lr_interp.c:1244-1262 - exec	0.00	0.00
▼Loop 821 - par_lr_interp.c:1196-1757 - exec–	0.00	0.00
▼Loop 820 - par_lr_interp.c:1196-1757 - exec–	0.00	0.00
▼Loop 819 - par_lr_interp.c:1196-1757 - exec–	0.00	0.00
▼Loop 823 - par_lr_interp.c:1609-1675 - exec–	0.05	0.01
○Loop 827 - par_lr_interp.c:1624-1628 - exec	0.06	0.01
○Loop 825 - par_lr_interp.c:1644-1651 - exec	0.04	0.01
○Loop 826 - par_lr_interp.c:1632-1637 - exec	0.00	0.00
○Loop 824 - par_lr_interp.c:1655-1660 - exec	0.00	0.00
▼Loop 830 - par_lr_interp.c:1494-1545 - exec–	0.00	0.00
○Loop 832 - par_lr_interp.c:1516-1526 - exec	0.03	0.01
○Loop 831 - par_lr_interp.c:1532-1545 - exec	0.00	0.00
▼Loop 818 - par_lr_interp.c:1196-1757 - exec–	0.00	0.00
▼Loop 833 - par_lr_interp.c:1196-1756 - exec–	0.00	0.00
○Loop 835 - par_lr_interp.c:1455-1456 - exec	0.01	0.00
○Loop 836 - par_lr_interp.c:1451-1452 - exec	0.00	0.00
○Loop 838 - par_lr_interp.c:1400-1403 - exec	0.00	0.00
○Loop 817 - par_lr_interp.c:1393-1396 - exec	0.00	0.00
○Loop 839 - par_lr_interp.c:1393-1396 - exec	0.00	0.00
○Loop 837 - par_lr_interp.c:1444-1445 - exec	0.00	0.00
○Loop 834 - par_lr_interp.c:1458-1459 - exec	0.00	0.00
○Loop 842 - par_lr_interp.c:1742-1743 - exec	0.00	0.00
○Loop 843 - par_lr_interp.c:1743-1743 - exec	0.00	0.00
▼Loop 828 - par_lr_interp.c:1555-1596 - exec–	0.00	0.00
○Loop 829 - par_lr_interp.c:1573-1596 - exec	0.00	0.00
○Loop 841 - par_lr_interp.c:1745-1745 - exec	0.00	0.00
○Loop 840 - par_lr_interp.c:1744-1745 - exec	0.00	0.00
○Loop 822 - par_lr_interp.c:1688-1700 - exec	0.00	0.00
○Loop 854 - par_lr_interp.c:1230-1231 - exec	0.00	0.00
○Loop 844 - par_lr_interp.c:1378-1382 - exec	0.00	0.00
○Loop 845 - par_lr_interp.c:1378-1382 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code