OV - exec - Function hypre_BoomerAMGBuildMultipass

	Function: hypre_BoomerAMGBuildMultipass	Module: exec	Source: par_multi_interp.c:41-2060 [...]	Coverage (incl. loops): 0.26% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 41 - 2060

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41: {

42: #ifdef HYPRE_PROFILE

43:    hypre_profile_times[HYPRE_TIMER_ID_MULTIPASS_INTERP] -= hypre_MPI_Wtime();

44: #endif

45:

46:    MPI_Comm	           comm = hypre_ParCSRMatrixComm(A);

47:    hypre_ParCSRCommPkg    *comm_pkg = hypre_ParCSRMatrixCommPkg(S);

48:    hypre_ParCSRCommHandle *comm_handle;

49:    hypre_ParCSRCommPkg    *tmp_comm_pkg;

50:

51:    hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A);

52:    HYPRE_Real      *A_diag_data = hypre_CSRMatrixData(A_diag);

53:    HYPRE_Int             *A_diag_i = hypre_CSRMatrixI(A_diag);

54:    HYPRE_Int             *A_diag_j = hypre_CSRMatrixJ(A_diag);

55:

56:    hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A);

57:    HYPRE_Real      *A_offd_data = NULL;

58:    HYPRE_Int             *A_offd_i = hypre_CSRMatrixI(A_offd);

59:    HYPRE_Int             *A_offd_j = NULL;

60:    HYPRE_Int		   *col_map_offd_A = hypre_ParCSRMatrixColMapOffd(A);

61:    HYPRE_Int		    num_cols_offd_A = hypre_CSRMatrixNumCols(A_offd);

62:

63:    hypre_CSRMatrix *S_diag = hypre_ParCSRMatrixDiag(S);

64:    HYPRE_Int             *S_diag_i = hypre_CSRMatrixI(S_diag);

65:    HYPRE_Int             *S_diag_j = hypre_CSRMatrixJ(S_diag);

66:

67:    hypre_CSRMatrix *S_offd = hypre_ParCSRMatrixOffd(S);

68:    HYPRE_Int             *S_offd_i = hypre_CSRMatrixI(S_offd);

69:    HYPRE_Int             *S_offd_j = NULL;

70:    HYPRE_Int		   *col_map_offd_S = hypre_ParCSRMatrixColMapOffd(S);

71:    HYPRE_Int		    num_cols_offd_S = hypre_CSRMatrixNumCols(S_offd);

[...]

83:    HYPRE_Real      *P_offd_data = NULL;

84:    HYPRE_Int             *P_offd_i; /*at first counter of nonzero cols for each row,

85: 				finally will be pointer to start of row */

86:    HYPRE_Int             *P_offd_j = NULL;

87:

88:    HYPRE_Int              num_sends = 0;

[...]

99:    HYPRE_Int             *Pext_start = NULL;

100:    HYPRE_Int             *P_ncols = NULL;

101:

102:    HYPRE_Int             *CF_marker_offd = NULL;

103:    HYPRE_Int             *dof_func_offd = NULL;

104:    HYPRE_Int             *P_marker;

105:    HYPRE_Int             *P_marker_offd = NULL;

106:    HYPRE_Int             *C_array;

107:    HYPRE_Int             *C_array_offd = NULL;

108:    HYPRE_Int             *pass_array = NULL; /* contains points ordered according to pass */

109:    HYPRE_Int             *pass_pointer = NULL; /* pass_pointer[j] contains pointer to first

110: 				point of pass j contained in pass_array */

111:    HYPRE_Int             *P_diag_start;

112:    HYPRE_Int             *P_offd_start = NULL;

113:    HYPRE_Int            **P_diag_pass;

114:    HYPRE_Int            **P_offd_pass = NULL;

115:    HYPRE_Int            **Pext_pass = NULL;

116:    HYPRE_Int            **new_elmts = NULL; /* new neighbors generated in each pass */

117:    HYPRE_Int             *new_counter = NULL; /* contains no. of new neighbors for

118: 					each pass */

119:    HYPRE_Int             *loc = NULL; /* contains locations for new neighbor

120: 			connections in int_o_buffer to avoid searching */

121:    HYPRE_Int             *Pext_i = NULL; /*contains P_diag_i and P_offd_i info for nonzero

122: 				cols of off proc neighbors */

123:    HYPRE_Int             *Pext_send_buffer = NULL; /* used to collect global nonzero

124: 				col ids in P_diag for send_map_elmts */

125:

126:    HYPRE_Int             *map_S_to_new = NULL;

127:    /*HYPRE_Int             *map_A_to_new = NULL;*/

128:    HYPRE_Int             *map_A_to_S = NULL;

129:    HYPRE_Int             *new_col_map_offd = NULL;

130:    HYPRE_Int             *col_map_offd_P = NULL;

131:    HYPRE_Int             *permute = NULL;

[...]

141:    HYPRE_Int              n_coarse = 0;

142:    HYPRE_Int              n_coarse_offd = 0;

143:    HYPRE_Int              n_SF = 0;

144:    HYPRE_Int              n_SF_offd = 0;

145:

146:    HYPRE_Int             *fine_to_coarse = NULL;

147:    HYPRE_Int             *fine_to_coarse_offd = NULL;

148:

149:    HYPRE_Int             *assigned = NULL;

150:    HYPRE_Int             *assigned_offd = NULL;

151:

152:    HYPRE_Real      *Pext_send_data = NULL;

153:    HYPRE_Real      *Pext_data = NULL;

[...]

184:    HYPRE_Int              P_offd_size = 0;

185:    HYPRE_Int              local_index = -1;

186:    HYPRE_Int              new_num_cols_offd = 0;

[...]

194:    HYPRE_Int * max_num_threads = hypre_CTAlloc(HYPRE_Int, 1);

[...]

202:    max_num_threads[0] = hypre_NumThreads();

203:    cnt_nz_per_thread = hypre_CTAlloc(HYPRE_Int, max_num_threads[0]);

204:    cnt_nz_offd_per_thread = hypre_CTAlloc(HYPRE_Int, max_num_threads[0]);

205:    for(i=0; i < max_num_threads[0]; i++)

206:    {

207:        cnt_nz_offd_per_thread[i] = 0;

208:        cnt_nz_per_thread[i] = 0;

[...]

216:    hypre_MPI_Comm_size(comm,&num_procs);

217:    hypre_MPI_Comm_rank(comm,&my_id);

218:

219: #ifdef HYPRE_NO_GLOBAL_PARTITION

220:    my_first_cpt = num_cpts_global[0];

221:    /*   total_global_cpts = 0; */

222:     if (my_id == (num_procs -1)) total_global_cpts = num_cpts_global[1];

223:     hypre_MPI_Bcast(&total_global_cpts, 1, HYPRE_MPI_INT, num_procs-1, comm);

[...]

229:    if (!comm_pkg)

230:    {

231:       comm_pkg = hypre_ParCSRMatrixCommPkg(A);

232:       if (!comm_pkg)

233:       {

234:           hypre_MatvecCommPkgCreate(A);

235:

236:           comm_pkg = hypre_ParCSRMatrixCommPkg(A);

237:       }

238:       col_offd_S_to_A = NULL;

239:    }

240:

241:    if (col_offd_S_to_A)

[...]

252:    if (num_cols_offd_A)

253:    {

254:       A_offd_data = hypre_CSRMatrixData(A_offd);

255:       A_offd_j    = hypre_CSRMatrixJ(A_offd);

256:    }

257:

258:    if (num_cols_offd)

259:       S_offd_j    = hypre_CSRMatrixJ(S_offd);

260:

261:    n_fine = hypre_CSRMatrixNumRows(A_diag);

[...]

267:    if (n_fine) fine_to_coarse = hypre_CTAlloc(HYPRE_Int, n_fine);

268:

269:    n_coarse = 0;

270:    n_SF = 0;

271: #ifdef HYPRE_USING_OPENMP

272: #pragma omp parallel for private(i) reduction(+:n_coarse,n_SF ) HYPRE_SMP_SCHEDULE

[...]

278:    pass_array_size = n_fine-n_coarse-n_SF;

279:    if (pass_array_size) pass_array = hypre_CTAlloc(HYPRE_Int, pass_array_size);

280:    pass_pointer = hypre_CTAlloc(HYPRE_Int, max_num_passes+1);

281:    if (n_fine) assigned = hypre_CTAlloc(HYPRE_Int, n_fine);

282:    P_diag_i = hypre_CTAlloc(HYPRE_Int, n_fine+1);

283:    P_offd_i = hypre_CTAlloc(HYPRE_Int, n_fine+1);

284:    if (n_coarse) C_array = hypre_CTAlloc(HYPRE_Int, n_coarse);

285:

286:    if (num_cols_offd)

287:    {

288:       CF_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

289:       if (num_functions > 1) dof_func_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

290:    }

291:

292:    if (num_procs > 1)

293:    {

294:       num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

295:       send_procs = hypre_ParCSRCommPkgSendProcs(comm_pkg);

296:       send_map_start = hypre_ParCSRCommPkgSendMapStarts(comm_pkg);

297:       send_map_elmt = hypre_ParCSRCommPkgSendMapElmts(comm_pkg);

298:       num_recvs = hypre_ParCSRCommPkgNumRecvs(comm_pkg);

299:       recv_procs = hypre_ParCSRCommPkgRecvProcs(comm_pkg);

300:       recv_vec_start = hypre_ParCSRCommPkgRecvVecStarts(comm_pkg);

301:       if (send_map_start[num_sends])

302:          int_buf_data = hypre_CTAlloc(HYPRE_Int, send_map_start[num_sends]);

303:    }

304:

305:

306:    index = 0;

307:    for (i=0; i < num_sends; i++)

308:    {

309:       start = send_map_start[i];

310:       for (j = start; j < send_map_start[i+1]; j++)

311:          int_buf_data[index++] = CF_marker[send_map_elmt[j]];

312:    }

313:    if (num_procs > 1)

314:    {

315:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

316: 	 CF_marker_offd);

317:       hypre_ParCSRCommHandleDestroy(comm_handle);

318:    }

319:

320:    if (num_functions > 1)

321:    {

322:       index = 0;

323:       for (i=0; i < num_sends; i++)

324:       {

325:          start = send_map_start[i];

326:          for (j = start; j < send_map_start[i+1]; j++)

327: 	    int_buf_data[index++] = dof_func[send_map_elmt[j]];

328:       }

329:       if (num_procs > 1)

330:       {

331:          comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

332: 	    dof_func_offd);

333:          hypre_ParCSRCommHandleDestroy(comm_handle);

334:       }

335:    }

336:

337:    n_coarse_offd = 0;

338:    n_SF_offd = 0;

339: #ifdef HYPRE_USING_OPENMP

340: #pragma omp parallel for private(i) reduction(+:n_coarse_offd,n_SF_offd) HYPRE_SMP_SCHEDULE

[...]

346:    if (num_cols_offd)

347:    {

348:       assigned_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

349:       map_S_to_new = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

350:       fine_to_coarse_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

351:       new_col_map_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd);

[...]

382:    p_cnt = pass_array_size-1;

383:    P_diag_i[0] = 0;

384:    P_offd_i[0] = 0;

385:    for (i = 0; i < n_fine; i++)

386:    {

387:       if (CF_marker[i] == 1)

388:       {

389:          fine_to_coarse[i] = cnt; /* this C point is assigned index

390:                                      coarse_counter on coarse grid,

391:                                      and in column of P */

392:          C_array[cnt++] = i;

393:          assigned[i] = 0;

394:          P_diag_i[i+1] = 1; /* one element in row i1 of P */

395:          P_offd_i[i+1] = 0;

396:       }

397:       else if (CF_marker[i] == -1)

398:       {

399:          pass_array[p_cnt--] = i;

400:          P_diag_i[i+1] = 0;

[...]

415:    for (i=0; i < num_sends; i++)

416:    {

417:       start = send_map_start[i];

418:       for (j = start; j < send_map_start[i+1]; j++)

419:       {

420:          int_buf_data[index] = fine_to_coarse[send_map_elmt[j]];

421:          if (int_buf_data[index] > -1)

422:             int_buf_data[index] += my_first_cpt;

423:          index++;

424:       }

425:    }

426:    if (num_procs > 1)

427:    {

428:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

429:          fine_to_coarse_offd);

430:       hypre_ParCSRCommHandleDestroy(comm_handle);

431:    }

432:

433:    new_recv_vec_start = hypre_CTAlloc(HYPRE_Int,num_recvs+1);

434:

435:    if (n_coarse_offd)

436:       C_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);

437:

438:    cnt = 0;

439:    new_recv_vec_start[0] = 0;

440:    for (j = 0; j < num_recvs; j++)

441:    {

442:       for (i = recv_vec_start[j]; i < recv_vec_start[j+1]; i++)

443:       {

444:          if (CF_marker_offd[i] == 1)

445:          {

446:             map_S_to_new[i] = cnt;

447:             C_array_offd[cnt] = i;

448:             new_col_map_offd[cnt++] = fine_to_coarse_offd[i];

449:             assigned_offd[i] = 0;

450:          }

451:          else

452:          {

453:             assigned_offd[i] = -1;

454:             map_S_to_new[i] = -1;

455:          }

456:       }

457:       new_recv_vec_start[j+1] = cnt;

458:    }

459:

460:    cnt = 0;

461:    hypre_TFree(fine_to_coarse_offd);

462:

463:    if (col_offd_S_to_A)

464:    {

465:       map_A_to_S = hypre_CTAlloc(HYPRE_Int,num_cols_offd_A);

466:       for (i=0; i < num_cols_offd_A; i++)

467:       {

468:         if (cnt < num_cols_offd && col_map_offd_A[i] == col_map_offd[cnt])

[...]

479:    pass_pointer[0] = 0;

480:    pass_pointer[1] = 0;

481:    total_nz = n_coarse;  /* accumulates total number of nonzeros in P_diag */

482:    total_nz_offd = 0; /* accumulates total number of nonzeros in P_offd */

[...]

488:    for (i = pass_array_size-1; i > cnt-1; i--)

489:    {

490:      i1 = pass_array[i];

491:      for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

492:      {

493:         j1 = S_diag_j[j];

494:         if (CF_marker[j1] == 1)

495:         {

496:            P_diag_i[i1+1]++;

497:            cnt_nz++;

498:            assigned[i1] = 1;

499:         }

500:      }

501:      for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

502:      {

503:         j1 = S_offd_j[j];

504:         if (CF_marker_offd[j1] == 1)

505:         {

506:            P_offd_i[i1+1]++;

507:            cnt_nz_offd++;

508:            assigned[i1] = 1;

509:         }

510:      }

511:      if (assigned[i1] == 1)

512:      {

513:         pass_array[i++] = pass_array[cnt];

514:         pass_array[cnt++] = i1;

515:      }

516:    }

517:

518:    pass_pointer[2] = cnt;

[...]

526:    for (i=0; i < num_sends; i++)

527:    {

528:       start = send_map_start[i];

529:       for (j = start; j < send_map_start[i+1]; j++)

530:       {    int_buf_data[index++] = assigned[send_map_elmt[j]]; }

531:    }

532:    if (num_procs > 1)

533:    {

534:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

535:                      assigned_offd);

536:       hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

544:    pass = 2;

545:    local_pass_array_size = pass_array_size - cnt;

546:    hypre_MPI_Allreduce(&local_pass_array_size, &global_pass_array_size, 1, HYPRE_MPI_INT,

547:                        hypre_MPI_SUM, comm);

548:    while (global_pass_array_size && pass < max_num_passes)

549:    {

550:       for (i = pass_array_size-1; i > cnt-1; i--)

551:       {

552:          i1 = pass_array[i];

553:          no_break = 1;

554:          for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

555:          {

556:             j1 = S_diag_j[j];

557:             if (assigned[j1] == pass-1)

[...]

568:             for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

569:             {

570:                j1 = S_offd_j[j];

571:                if (assigned_offd[j1] == pass-1)

[...]

583:       pass++;

584:       pass_pointer[pass] = cnt;

585:

586:       local_pass_array_size = pass_array_size - cnt;

587:       hypre_MPI_Allreduce(&local_pass_array_size, &global_pass_array_size, 1, HYPRE_MPI_INT,

588:                           hypre_MPI_SUM, comm);

589:       index = 0;

590:       for (i=0; i < num_sends; i++)

591:       {

592:          start = send_map_start[i];

593:          for (j = start; j < send_map_start[i+1]; j++)

594:          {   int_buf_data[index++] = assigned[send_map_elmt[j]]; }

595:       }

596:       if (num_procs > 1)

597:       {

598:          comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

599:                        assigned_offd);

600:          hypre_ParCSRCommHandleDestroy(comm_handle);

601:       }

602:    }

603:

604:    hypre_TFree(int_buf_data);

605:

606:    num_passes = pass;

607:

608:    P_diag_pass = hypre_CTAlloc(HYPRE_Int*,num_passes); /* P_diag_pass[i] will contain

609:                                  all column numbers for points of pass i */

610:

611:    P_diag_pass[1] = hypre_CTAlloc(HYPRE_Int,cnt_nz);

612:

613:    P_diag_start = hypre_CTAlloc(HYPRE_Int, n_fine); /* P_diag_start[i] contains

614:            pointer to begin of column numbers in P_pass for point i,

615:            P_diag_i[i+1] contains number of columns for point i */

616:

617:    P_offd_start = hypre_CTAlloc(HYPRE_Int, n_fine);

618:

619:    if (num_procs > 1)

620:    {

621:       P_offd_pass = hypre_CTAlloc(HYPRE_Int*,num_passes);

622:

623:       if (cnt_nz_offd)

624:          P_offd_pass[1] = hypre_CTAlloc(HYPRE_Int,cnt_nz_offd);

625:       else

626:          P_offd_pass[1] = NULL;

627:

628:       new_elmts = hypre_CTAlloc(HYPRE_Int*,num_passes);

629:

630:       new_counter = hypre_CTAlloc(HYPRE_Int, num_passes+1);

631:

632:       new_counter[0] = 0;

633:       new_counter[1] = n_coarse_offd;

634:       new_num_cols_offd = n_coarse_offd;

635:

636:       new_elmts[0] = new_col_map_offd;

[...]

646:    for (i=pass_pointer[1]; i < pass_pointer[2]; i++)

647:    {

648:       i1 = pass_array[i];

649:       P_diag_start[i1] = cnt_nz;

650:       P_offd_start[i1] = cnt_nz_offd;

651:       for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

652:       {

653:          j1 = S_diag_j[j];

654:          if (CF_marker[j1] == 1)

655:          {   P_diag_pass[1][cnt_nz++] = fine_to_coarse[j1]; }

656:       }

657:       for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

658:       {

659:          j1 = S_offd_j[j];

660:          if (CF_marker_offd[j1] == 1)

661:          {   P_offd_pass[1][cnt_nz_offd++] = map_S_to_new[j1]; }

662:       }

663:    }

664:

665:

666:    total_nz += cnt_nz;

667:    total_nz_offd += cnt_nz_offd;

668:

669:    if (num_procs > 1)

670:    {

671:       tmp_comm_pkg = hypre_CTAlloc(hypre_ParCSRCommPkg,1);

672:       Pext_send_map_start = hypre_CTAlloc(HYPRE_Int*,num_passes);

673:       Pext_recv_vec_start = hypre_CTAlloc(HYPRE_Int*,num_passes);

674:       Pext_pass = hypre_CTAlloc(HYPRE_Int*,num_passes);

675:       Pext_i = hypre_CTAlloc(HYPRE_Int, num_cols_offd+1);

676:       if (num_cols_offd) Pext_start = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

677:       if (send_map_start[num_sends])

678:          P_ncols = hypre_CTAlloc(HYPRE_Int,send_map_start[num_sends]);

679: #ifdef HYPRE_USING_OPENMP

680: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

681: #endif

682:       for (i=0; i < num_cols_offd+1; i++)

683:       {   Pext_i[i] = 0; }

684: #ifdef HYPRE_USING_OPENMP

685: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

693:    for (pass=2; pass < num_passes; pass++)

694:    {

695:

696:       if (num_procs > 1)

697:       {

698:          Pext_send_map_start[pass] = hypre_CTAlloc(HYPRE_Int, num_sends+1);

699:          Pext_recv_vec_start[pass] = hypre_CTAlloc(HYPRE_Int, num_recvs+1);

700:          Pext_send_size = 0;

701:          Pext_send_map_start[pass][0] = 0;

702:

703:          for (i=0; i < num_sends; i++)

704:          {

705: #ifdef HYPRE_USING_OPENMP

706: #pragma omp parallel for private(j,j1) reduction(+:Pext_send_size) HYPRE_SMP_SCHEDULE

[...]

717:             Pext_send_map_start[pass][i+1] = Pext_send_size;

718:          }

719:

720:          comm_handle = hypre_ParCSRCommHandleCreate (11, comm_pkg,

721:                                               P_ncols, &Pext_i[1]);

722:          hypre_ParCSRCommHandleDestroy(comm_handle);

723:

724:          if (Pext_send_size > old_Pext_send_size)

725:          {

726:             hypre_TFree(Pext_send_buffer);

727:             Pext_send_buffer = hypre_CTAlloc(HYPRE_Int, Pext_send_size);

728:          }

729:          old_Pext_send_size = Pext_send_size;

730:       }

731:

732:       cnt_offd = 0;

733:       for (i=0; i < num_sends; i++)

734:       {

735:          for (j=send_map_start[i]; j < send_map_start[i+1]; j++)

736:          {

737:             j1 = send_map_elmt[j];

738:             if (assigned[j1] == pass-1)

739:             {

740:                j_start = P_diag_start[j1];

741:                j_end = j_start+P_diag_i[j1+1];

742:                for (k=j_start; k < j_end; k++)

743:                {

744:                 Pext_send_buffer[cnt_offd++] = my_first_cpt

745:                     +P_diag_pass[pass-1][k];

746:                }

747:                j_start = P_offd_start[j1];

748:                j_end = j_start+P_offd_i[j1+1];

749:                for (k=j_start; k < j_end; k++)

750:                {

751:                  k1 = P_offd_pass[pass-1][k];

752:                  k3 = 0;

753:                  while (k3 < pass-1)

754:                  {

755:                     if (k1 < new_counter[k3+1])

756:                     {

757:                        k2 = k1-new_counter[k3];

758:                        Pext_send_buffer[cnt_offd++] = new_elmts[k3][k2];

[...]

768:       if (num_procs > 1)

769:       {

770:          Pext_recv_size = 0;

771:          Pext_recv_vec_start[pass][0] = 0;

772:          cnt_offd = 0;

773:          for (i=0; i < num_recvs; i++)

774:          {

775:             for (j=recv_vec_start[i]; j<recv_vec_start[i+1]; j++)

776:             {

777:                if (assigned_offd[j] == pass-1)

778:                {

779:                   Pext_start[j] = cnt_offd;

780:                   cnt_offd += Pext_i[j+1];

781:                }

782:             }

783:             Pext_recv_size = cnt_offd;

784:             Pext_recv_vec_start[pass][i+1] = Pext_recv_size;

785:          }

786:

787:          hypre_ParCSRCommPkgComm(tmp_comm_pkg) = comm;

788:          hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends;

789:          hypre_ParCSRCommPkgSendProcs(tmp_comm_pkg) = send_procs;

790:          hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) =

791:             Pext_send_map_start[pass];

792:          hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs;

793:          hypre_ParCSRCommPkgRecvProcs(tmp_comm_pkg) = recv_procs;

794:          hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) =

795:             Pext_recv_vec_start[pass];

796:

797:          if (Pext_recv_size)

798:          {

799:             Pext_pass[pass] = hypre_CTAlloc(HYPRE_Int, Pext_recv_size);

800:             new_elmts[pass-1] = hypre_CTAlloc(HYPRE_Int,Pext_recv_size);

801:          }

802:          else

803:          {

804:             Pext_pass[pass] = NULL;

805:             new_elmts[pass-1] = NULL;

806:          }

807:

808:          comm_handle = hypre_ParCSRCommHandleCreate (11, tmp_comm_pkg,

809:             Pext_send_buffer, Pext_pass[pass]);

810:          hypre_ParCSRCommHandleDestroy(comm_handle);

811:

812:          if (Pext_recv_size > old_Pext_recv_size)

813:          {

814:             hypre_TFree(loc);

815:             loc = hypre_CTAlloc(HYPRE_Int,Pext_recv_size);

[...]

823:       for (i=0; i < num_recvs; i++)

824:       {

825:          for (j=recv_vec_start[i]; j < recv_vec_start[i+1]; j++)

826:          {

827:             if (assigned_offd[j] == pass-1)

828:             {

829:                for (j1 = cnt_offd; j1 < cnt_offd+Pext_i[j+1]; j1++)

830:                {

831:                   k1 = Pext_pass[pass][j1];

832:                   k2 = k1 - my_first_cpt;

833:                   if (k2 > -1 && k2 < n_coarse)

834:                   {  Pext_pass[pass][j1] = -k2-1; }

835:                   else

836:                   {

837:                      not_found = 1;

838:                      k3 = 0;

839:                      while (k3 < pass-1 && not_found)

840:                      {

841:                         k2 = hypre_BinarySearch(new_elmts[k3], k1,

842:                                 (new_counter[k3+1]-new_counter[k3]));

843:                         if (k2 > -1)

844:                         {

845:                             Pext_pass[pass][j1] = k2 + new_counter[k3];

[...]

855:                          new_elmts[pass-1][cnt_new] = Pext_pass[pass][j1];

856:                          loc[cnt_new++] = j1;

[...]

865:       if (cnt_new)

866:       {

867:          hypre_qsort2i(new_elmts[pass-1],loc,0,cnt_new-1);

868:          cnt = 0;

869:          local_index = new_counter[pass-1];

870:          Pext_pass[pass][loc[0]] = local_index;

871:

872:          for (i=1; i < cnt_new; i++)

873:          {

874:             if (new_elmts[pass-1][i] > new_elmts[pass-1][cnt])

875:             {

876:                new_elmts[pass-1][++cnt] = new_elmts[pass-1][i];

877:                local_index++;

878:             }

879:             Pext_pass[pass][loc[i]] = local_index;

880:          }

881:          new_counter[pass] = local_index+1;

882:       }

883:       else if (num_procs > 1)

884:          new_counter[pass] = new_counter[pass-1];

885:

886:       if (new_num_cols_offd < local_index+1)

887:       {    new_num_cols_offd = local_index+1; }

888:

889:       pass_length = pass_pointer[pass+1] - pass_pointer[pass];

890:       #ifdef HYPRE_USING_OPENMP

891:       #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd)

[...]

1140:    hypre_TFree(loc);

1141:    hypre_TFree(P_ncols);

1142:    hypre_TFree(Pext_send_buffer);

1143:    hypre_TFree(new_recv_vec_start);

1144:    hypre_TFree(cnt_nz_per_thread);

1145:    hypre_TFree(cnt_nz_offd_per_thread);

1146:    hypre_TFree(max_num_threads);

1147:

1148:    P_diag_j = hypre_CTAlloc(HYPRE_Int,total_nz);

1149:    P_diag_data = hypre_CTAlloc(HYPRE_Real,total_nz);

1150:

1151:

1152:    if (total_nz_offd)

1153:    {

1154:       P_offd_j = hypre_CTAlloc(HYPRE_Int,total_nz_offd);

1155:       P_offd_data = hypre_CTAlloc(HYPRE_Real,total_nz_offd);

1156:    }

1157:

1158:    for (i=0; i < n_fine; i++)

1159:    {

1160:       P_diag_i[i+1] += P_diag_i[i];

1161:       P_offd_i[i+1] += P_offd_i[i];

[...]

1167: #pragma omp parallel for private(i,i1) HYPRE_SMP_SCHEDULE

[...]

1177:    if (weight_option) /*if this is set, weights are separated into

[...]

1184: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,P_marker,P_marker_offd,i,i1,sum_C_pos,sum_C_neg,sum_N_pos,sum_N_neg,j_start,j_end,j,k1,cnt,j1,cnt_offd,diagonal,alfa,beta)

[...]

1304:       if (n_coarse) hypre_TFree(C_array);

1305:       hypre_TFree(C_array_offd);

1306:       hypre_TFree(P_diag_pass[1]);

1307:       if (num_procs > 1) hypre_TFree(P_offd_pass[1]);

1308:

1309:

1310:       for (pass = 2; pass < num_passes; pass++)

1311:       {

1312:

1313:          if (num_procs > 1)

1314:          {

1315:             Pext_send_size = Pext_send_map_start[pass][num_sends];

1316:             if (Pext_send_size > old_Pext_send_size)

1317:             {

1318:                hypre_TFree(Pext_send_data);

1319:                Pext_send_data = hypre_CTAlloc(HYPRE_Real, Pext_send_size);

1320:             }

1321:             old_Pext_send_size = Pext_send_size;

1322:

1323:             cnt_offd = 0;

1324:             for (i=0; i < num_sends; i++)

1325:             {

1326:                for (j=send_map_start[i]; j < send_map_start[i+1]; j++)

1327:                {

1328:                   j1 = send_map_elmt[j];

1329:                   if (assigned[j1] == pass-1)

1330:                   {

1331:                      j_start = P_diag_i[j1];

1332:                      j_end = P_diag_i[j1+1];

1333:                      for (k=j_start; k < j_end; k++)

1334:                      {   Pext_send_data[cnt_offd++] = P_diag_data[k]; }

1335:                      j_start = P_offd_i[j1];

1336:                      j_end = P_offd_i[j1+1];

1337:                      for (k=j_start; k < j_end; k++)

1338:                      {  Pext_send_data[cnt_offd++] = P_offd_data[k]; }

1339:                   }

1340:                }

1341:             }

1342:

1343:             hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends;

1344:             hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) =

1345:                 Pext_send_map_start[pass];

1346:             hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs;

1347:             hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) =

1348:                 Pext_recv_vec_start[pass];

1349:

1350:             Pext_recv_size = Pext_recv_vec_start[pass][num_recvs];

1351:

1352:             if (Pext_recv_size > old_Pext_recv_size)

1353:             {

1354:                hypre_TFree(Pext_data);

1355:                Pext_data = hypre_CTAlloc(HYPRE_Real, Pext_recv_size);

1356:             }

1357:             old_Pext_recv_size = Pext_recv_size;

1358:

1359:             comm_handle = hypre_ParCSRCommHandleCreate (1, tmp_comm_pkg,

1360:                 Pext_send_data, Pext_data);

1361:             hypre_ParCSRCommHandleDestroy(comm_handle);

1362:

1363:             hypre_TFree(Pext_send_map_start[pass]);

1364:             hypre_TFree(Pext_recv_vec_start[pass]);

1365:          }

1366:

1367:          pass_length = pass_pointer[pass+1]-pass_pointer[pass];

1368: #ifdef HYPRE_USING_OPENMP

1369: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,P_marker,P_marker_offd,i,i1,sum_C_neg,sum_C_pos,sum_N_neg,sum_N_pos,j_start,j_end,cnt,j,k1,cnt_offd,j1,k,alfa,beta,diagonal,C_array,C_array_offd)

[...]

1562:          hypre_TFree(P_diag_pass[pass]);

1563:          if (num_procs > 1)

1564:          {

1565:             hypre_TFree(P_offd_pass[pass]);

1566:             hypre_TFree(Pext_pass[pass]);

[...]

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1669:       if (n_coarse) hypre_TFree(C_array);

1670:       hypre_TFree(C_array_offd);

1671:       hypre_TFree(P_diag_pass[1]);

1672:       if (num_procs > 1) hypre_TFree(P_offd_pass[1]);

1673:

1674:       for (pass = 2; pass < num_passes; pass++)

1675:       {

1676:

1677:          if (num_procs > 1)

1678:          {

1679:             Pext_send_size = Pext_send_map_start[pass][num_sends];

1680:             if (Pext_send_size > old_Pext_send_size)

1681:             {

1682:                hypre_TFree(Pext_send_data);

1683:                Pext_send_data = hypre_CTAlloc(HYPRE_Real, Pext_send_size);

1684:             }

1685:             old_Pext_send_size = Pext_send_size;

1686:

1687:             cnt_offd = 0;

1688:             for (i=0; i < num_sends; i++)

1689:             {

1690:                for (j=send_map_start[i]; j < send_map_start[i+1]; j++)

1691:                {

1692:                   j1 = send_map_elmt[j];

1693:                   if (assigned[j1] == pass-1)

1694:                   {

1695:                      j_start = P_diag_i[j1];

1696:                      j_end = P_diag_i[j1+1];

1697:                      for (k=j_start; k < j_end; k++)

1698:                      {

1699:                         Pext_send_data[cnt_offd++] = P_diag_data[k];

1700:                      }

1701:                      j_start = P_offd_i[j1];

1702:                      j_end = P_offd_i[j1+1];

1703:                      for (k=j_start; k < j_end; k++)

1704:                      {

1705:                         Pext_send_data[cnt_offd++] = P_offd_data[k];

[...]

1711:             hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends;

1712:             hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) =

1713:                 Pext_send_map_start[pass];

1714:             hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs;

1715:             hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) =

1716:                 Pext_recv_vec_start[pass];

1717:

1718:             Pext_recv_size = Pext_recv_vec_start[pass][num_recvs];

1719:

1720:             if (Pext_recv_size > old_Pext_recv_size)

1721:             {

1722:                hypre_TFree(Pext_data);

1723:                Pext_data = hypre_CTAlloc(HYPRE_Real, Pext_recv_size);

1724:             }

1725:             old_Pext_recv_size = Pext_recv_size;

1726:

1727:             comm_handle = hypre_ParCSRCommHandleCreate (1, tmp_comm_pkg,

1728:                 Pext_send_data, Pext_data);

1729:             hypre_ParCSRCommHandleDestroy(comm_handle);

1730:

1731:             hypre_TFree(Pext_send_map_start[pass]);

1732:             hypre_TFree(Pext_recv_vec_start[pass]);

1733:          }

1734:

1735:          pass_length = pass_pointer[pass+1]-pass_pointer[pass];

1736: #ifdef HYPRE_USING_OPENMP

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1884:          hypre_TFree(P_diag_pass[pass]);

1885:          if (num_procs > 1)

1886:          {

1887:             hypre_TFree(P_offd_pass[pass]);

1888:             hypre_TFree(Pext_pass[pass]);

1889:          }

1890:       }

1891:    }

1892:

1893:    hypre_TFree(CF_marker_offd);

1894:    hypre_TFree(Pext_send_map_start);

1895:    hypre_TFree(Pext_recv_vec_start);

1896:    hypre_TFree(dof_func_offd);

1897:    hypre_TFree(Pext_send_data);

1898:    hypre_TFree(Pext_data);

1899:    hypre_TFree(P_diag_pass);

1900:    hypre_TFree(P_offd_pass);

1901:    hypre_TFree(Pext_pass);

1902:    hypre_TFree(P_diag_start);

1903:    hypre_TFree(P_offd_start);

1904:    hypre_TFree(Pext_start);

1905:    hypre_TFree(Pext_i);

1906:    hypre_TFree(fine_to_coarse);

1907:    hypre_TFree(assigned);

1908:    hypre_TFree(assigned_offd);

1909:    hypre_TFree(pass_pointer);

1910:    hypre_TFree(pass_array);

1911:    hypre_TFree(map_S_to_new);

1912:    hypre_TFree(map_A_to_S);

1913:    if (num_procs > 1) hypre_TFree(tmp_comm_pkg);

1914:

1915:     P = hypre_ParCSRMatrixCreate(comm,

1916:                                 hypre_ParCSRMatrixGlobalNumRows(A),

1917:                                 total_global_cpts,

1918:                                 hypre_ParCSRMatrixColStarts(A),

1919:                                 num_cpts_global,

1920:                                 0,

1921:                                 P_diag_i[n_fine],

1922:                                 P_offd_i[n_fine]);

1923:    P_diag = hypre_ParCSRMatrixDiag(P);

1924:    hypre_CSRMatrixData(P_diag) = P_diag_data;

1925:    hypre_CSRMatrixI(P_diag) = P_diag_i;

1926:    hypre_CSRMatrixJ(P_diag) = P_diag_j;

1927:    P_offd = hypre_ParCSRMatrixOffd(P);

1928:    hypre_CSRMatrixData(P_offd) = P_offd_data;

1929:    hypre_CSRMatrixI(P_offd) = P_offd_i;

1930:    hypre_CSRMatrixJ(P_offd) = P_offd_j;

1931:    hypre_ParCSRMatrixOwnsRowStarts(P) = 0;

1932:

1933:    /* Compress P, removing coefficients smaller than trunc_factor * Max

1934:       and/or keep yat most <P_max_elmts> per row absolutely maximal coefficients */

1935:

1936:    if (trunc_factor != 0.0 || P_max_elmts != 0)

1937:    {

1938:       hypre_BoomerAMGInterpTruncation(P, trunc_factor, P_max_elmts);

1939:       P_diag_data = hypre_CSRMatrixData(P_diag);

1940:       P_diag_i = hypre_CSRMatrixI(P_diag);

1941:       P_diag_j = hypre_CSRMatrixJ(P_diag);

1942:       P_offd_data = hypre_CSRMatrixData(P_offd);

1943:       P_offd_i = hypre_CSRMatrixI(P_offd);

1944:       P_offd_j = hypre_CSRMatrixJ(P_offd);

1945:    }

1946:    P_offd_size = P_offd_i[n_fine];

1947:

1948:    num_cols_offd_P = 0;

1949:    if (P_offd_size)

1950:    {

1951:       if (new_num_cols_offd > num_cols_offd)

1952:       {   P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1953:       else

1954:       {   P_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1955: #ifdef HYPRE_USING_OPENMP

1956: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

1957: #endif

1958:       for (i=0; i < new_num_cols_offd; i++)

1959:       {   P_marker_offd[i] = 0; }

1960:

1961:       num_cols_offd_P = 0;

1962:       for (i=0; i < P_offd_size; i++)

1963:       {

1964:          index = P_offd_j[i];

1965:          if (!P_marker_offd[index])

1966:          {

1967:             num_cols_offd_P++;

1968:             P_marker_offd[index] = 1;

1969:          }

1970:       }

1971:

1972:       col_map_offd_P = hypre_CTAlloc(HYPRE_Int,num_cols_offd_P);

1973:       permute = hypre_CTAlloc(HYPRE_Int, new_counter[num_passes-1]);

1974:

1975: #ifdef HYPRE_USING_OPENMP

1976: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

1982:       for (i=0; i < num_passes-1; i++)

1983:       {

1984:          for (j=new_counter[i]; j < new_counter[i+1]; j++)

1985:          {

1986:             if (P_marker_offd[j])

1987:             {

1988:                col_map_offd_P[cnt] = new_elmts[i][j-new_counter[i]];

1989:                permute[j] = col_map_offd_P[cnt++];

1990:             }

1991:          }

1992:       }

1993:

1994:       hypre_qsort0(col_map_offd_P,0,num_cols_offd_P-1);

1995:

1996: #ifdef HYPRE_USING_OPENMP

1997: #pragma omp parallel for private(i,k1) HYPRE_SMP_SCHEDULE

[...]

2007: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

2008: #endif

2009:       for (i=0; i < P_offd_size; i++)

2010:       {   P_offd_j[i] = permute[P_offd_j[i]]; }

2011:

2012:       hypre_TFree(P_marker_offd);

2013:    }

2014:    if (num_procs > 1)

2015:    {

2016:       for (i=0; i < num_passes-1; i++)

2017:          hypre_TFree(new_elmts[i]);

2018:    }

2019:    hypre_TFree(permute);

2020:    hypre_TFree(new_elmts);

2021:    hypre_TFree(new_counter);

2022:

2023:    if (num_cols_offd_P)

2024:    {

2025:         hypre_ParCSRMatrixColMapOffd(P) = col_map_offd_P;

2026:         hypre_CSRMatrixNumCols(P_offd) = num_cols_offd_P;

2027:    }

2028:

2029:    if (n_SF)

2030:    {

2031: #ifdef HYPRE_USING_OPENMP

2032: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2038:    if (num_procs > 1)

2039:    {

2040:         hypre_MatvecCommPkgCreate(P);

2041:    }

2042:

2043:    *P_ptr = P;

[...]

2060:    return(0);

0x42fe80 STR	D8, [SP, #400]!

0x42fe84 STP	X29, X30, [SP, #16]

0x42fe88 STP	X28, X27, [SP, #32]

0x42fe8c STP	X26, X25, [SP, #48]

0x42fe90 STP	X24, X23, [SP, #64]

0x42fe94 STP	X22, X21, [SP, #80]

0x42fe98 STP	X20, X19, [SP, #96]

0x42fe9c ADD	X29, SP, #16

0x42fea0 SUB	SP, SP, #1008

0x42fea4 LDP	X21, X23, [X0, #56]

0x42fea8 STUR	X1, [X29, #504]

0x42feac LDR	X10, [X0]

0x42feb0 MOVZ	W1, #8

0x42feb4 FMOV	D8, D0

0x42feb8 LDR	X24, [X0, #88]

0x42febc LDR	X26, [X2, #88]

0x42fec0 STR	X0, [SP, #312]

0x42fec4 MOVZ	W0, #1

0x42fec8 STR	X7, [SP, #304]

0x42fecc STR	X3, [SP, #320]

0x42fed0 STUR	XZR, [X29, #328]

0x42fed4 STR	XZR, [SP, #624]

0x42fed8 STR	XZR, [SP, #616]

0x42fedc STR	XZR, [SP, #608]

0x42fee0 LDR	X8, [X21, #48]

0x42fee4 LDR	X22, [X23, #24]

0x42fee8 STR	XZR, [SP, #600]

0x42feec STUR	X4, [X29, #480]

0x42fef0 STR	XZR, [SP, #480]

0x42fef4 STP	X8, X5, [X29, #976]

0x42fef8 LDP	X8, X9, [X21]

0x42fefc STP	XZR, X9, [X29, #952]

0x42ff00 STUR	X8, [X29, #456]

0x42ff04 LDR	X8, [X23]

0x42ff08 STP	XZR, X8, [X29, #936]

0x42ff0c LDP	X8, X25, [X2, #56]

0x42ff10 LDP	X9, X8, [X8]

0x42ff14 LDR	X28, [X25, #24]

0x42ff18 STP	X8, X9, [X29, #920]

0x42ff1c LDR	X9, [X2, #112]

0x42ff20 LDR	X8, [X25]

0x42ff24 STUR	XZR, [X29, #392]

0x42ff28 STUR	XZR, [X29, #352]

0x42ff2c STUR	XZR, [X29, #336]

0x42ff30 STP	XZR, XZR, [X29, #808]

0x42ff34 STP	XZR, XZR, [X29, #792]

0x42ff38 STUR	XZR, [X29, #272]

0x42ff3c STUR	XZR, [X29, #256]

0x42ff40 STR	XZR, [SP, #760]

0x42ff44 STR	XZR, [SP, #752]

0x42ff48 STR	XZR, [SP, #736]

0x42ff4c STR	XZR, [SP, #720]

0x42ff50 STR	XZR, [SP, #712]

0x42ff54 STR	XZR, [SP, #704]

0x42ff58 STR	XZR, [SP, #696]

0x42ff5c STR	XZR, [SP, #688]

0x42ff60 STR	XZR, [SP, #680]

0x42ff64 STR	XZR, [SP, #672]

0x42ff68 STR	XZR, [SP, #664]

0x42ff6c STR	XZR, [SP, #592]

0x42ff70 STR	XZR, [SP, #584]

0x42ff74 STR	XZR, [SP, #576]

0x42ff78 STR	XZR, [SP, #568]

0x42ff7c STP	X9, X10, [SP, #368]

0x42ff80 STUR	X8, [X29, #400]

0x42ff84 MOVN	X8, #0

0x42ff88 STP	X8, XZR, [SP, #488]

0x42ff8c BL	4a6c90

0x42ff90 ORR	X19, XZR, X0

0x42ff94 STR	X0, [SP, #456]

0x42ff98 BL	4a89d0

0x42ff9c MOVZ	W1, #8

0x42ffa0 STR	X0, [X19]

0x42ffa4 BL	4a6c90

0x42ffa8 ORR	X20, XZR, X0

0x42ffac STR	X0, [SP, #448]

0x42ffb0 LDR	X0, [X19]

0x42ffb4 MOVZ	W1, #8

0x42ffb8 BL	4a6c90

0x42ffbc STR	XZR, [SP, #560]

0x42ffc0 STR	X0, [SP, #440]

0x42ffc4 LDR	X8, [X19]

0x42ffc8 CMP	X8, #1

0x42ffcc B.LT	430004

0x42ffd0 ORR	X8, XZR, XZR

0x42ffd4 HINT	#0

0x42ffd8 HINT	#0

0x42ffdc HINT	#0

(666) 0x42ffe0 STR	XZR, [X0, X8,LSL #3]

(666) 0x42ffe4 LDR	X8, [SP, #560]

(666) 0x42ffe8 STR	XZR, [X20, X8,LSL #3]

(666) 0x42ffec LDR	X8, [SP, #560]

(666) 0x42fff0 ADD	X8, X8, #1

(666) 0x42fff4 STR	X8, [SP, #560]

(666) 0x42fff8 LDR	X9, [X19]

(666) 0x42fffc CMP	X8, X9

(666) 0x430000 B.LT	42ffe0

0x430004 LDR	X19, [SP, #376]

0x430008 ADD	X1, SP, #528

0x43000c ORR	X0, XZR, X19

0x430010 BL	4a7e70

0x430014 ADD	X1, SP, #536

0x430018 ORR	X0, XZR, X19

0x43001c BL	4a7ea0

0x430020 LDR	X9, [SP, #528]

0x430024 LDR	X8, [SP, #536]

0x430028 SUB	X3, X9, #1

0x43002c CMP	X8, X3

0x430030 B.NE	430040

0x430034 LDR	X8, [SP, #320]

0x430038 LDR	X8, [X8, #8]

0x43003c STR	X8, [SP, #520]

0x430040 LDR	X8, [SP, #320]

0x430044 ADRP	X2,

0x430048 ADD	X0, SP, #520

0x43004c MOVZ	W1, #1

0x430050 LDR	X27, [X8]

0x430054 LDR	X2, [X2, #4000]

0x430058 LDR	X4, [SP, #376]

0x43005c BL	4a8460

0x430060 LDR	X8, [SP, #368]

0x430064 CBZ	X8, 430070

0x430068 LDR	X8, [X29, #104]

0x43006c B	43009c

0x430070 LDR	X8, [SP, #312]

0x430074 LDR	X8, [X8, #112]

0x430078 STR	X8, [SP, #368]

0x43007c CBNZ	X8, 430094

0x430080 LDR	X19, [SP, #312]

0x430084 ORR	X0, XZR, X19

0x430088 BL	481820

0x43008c LDR	X8, [X19, #112]

0x430090 STR	X8, [SP, #368]

0x430094 ORR	X8, XZR, XZR

0x430098 STR	XZR, [X29, #104]

0x43009c CMP	X8, #0

0x4300a0 CSEL	X8, X22, X28, #0

0x4300a4 CSEL	X20, X24, X26, #0

0x4300a8 STUR	X8, [X29, #384]

0x4300ac CBZ	X22, 4300c0

0x4300b0 LDR	X9, [X23, #48]

0x4300b4 STUR	X9, [X29, #440]

0x4300b8 LDR	X9, [X23, #8]

0x4300bc STUR	X9, [X29, #424]

0x4300c0 CBZ	X8, 4300cc

0x4300c4 LDR	X8, [X25, #8]

0x4300c8 STUR	X8, [X29, #392]

0x4300cc LDR	X0, [X21, #16]

0x4300d0 STR	X0, [SP, #632]

0x4300d4 CBZ	X0, 4300e4

0x4300d8 MOVZ	W1, #8

0x4300dc BL	4a6c90

0x4300e0 STR	X0, [SP, #592]

0x4300e4 ADRP	X0,

0x4300e8 ADD	X0, X0, #208

0x4300ec ADRP	X2, 4320ec

0x4300f0 ADD	X2, X2, #2512

0x4300f4 ADD	X3, SP, #632

0x4300f8 SUB	X4, X29, #8

0x4300fc STR	XZR, [SP, #624]

0x430100 STR	XZR, [SP, #608]

0x430104 ADD	X5, SP, #624

0x430108 ADD	X6, SP, #608

0x43010c MOVZ	W1, #4

0x430110 BL	40f600

0x430114 LDR	X9, [SP, #624]

0x430118 LDR	X10, [SP, #608]

0x43011c LDR	X8, [SP, #632]

0x430120 ADD	X9, X10, X9

0x430124 SUBS	X28, X8, X9

0x430128 B.EQ	43013c

0x43012c MOVZ	W1, #8

0x430130 ORR	X0, XZR, X28

0x430134 BL	4a6c90

0x430138 STR	X0, [SP, #760]

0x43013c MOVZ	W0, #11

0x430140 MOVZ	W1, #8

0x430144 BL	4a6c90

0x430148 STR	X0, [SP, #752]

0x43014c LDR	X0, [SP, #632]

0x430150 CBZ	X0, 430168

0x430154 MOVZ	W1, #8

0x430158 BL	4a6c90

0x43015c LDR	X8, [SP, #632]

0x430160 STR	X0, [SP, #584]

0x430164 B	43016c

0x430168 ORR	X8, XZR, XZR

0x43016c ADD	X0, X8, #1

0x430170 MOVZ	W1, #8

0x430174 BL	4a6c90

0x430178 LDR	X8, [SP, #632]

0x43017c STUR	X0, [X29, #368]

0x430180 MOVZ	W1, #8

0x430184 ADD	X0, X8, #1

0x430188 BL	4a6c90

0x43018c STUR	X0, [X29, #344]

0x430190 LDR	X0, [SP, #624]

0x430194 CBZ	X0, 4301a4

0x430198 MOVZ	W1, #8

0x43019c BL	4a6c90

0x4301a0 STUR	X0, [X29, #264]

0x4301a4 LDUR	X0, [X29, #384]

0x4301a8 CBZ	X0, 4301d4

0x4301ac MOVZ	W1, #8

0x4301b0 BL	4a6c90

0x4301b4 LDUR	X8, [X29, #480]

0x4301b8 STUR	X0, [X29, #288]

0x4301bc CMP	X8, #2

0x4301c0 B.LT	4301d4

0x4301c4 LDUR	X0, [X29, #384]

0x4301c8 MOVZ	W1, #8

0x4301cc BL	4a6c90

0x4301d0 STUR	X0, [X29, #280]

0x4301d4 LDR	X8, [SP, #528]

0x4301d8 CMP	X8, #1

0x4301dc B.LE	430228

0x4301e0 LDR	X11, [SP, #368]

0x4301e4 LDP	X8, X9, [X11, #8]

0x4301e8 STR	X9, [SP, #336]

0x4301ec LDP	X9, X10, [X11, #24]

0x4301f0 STUR	X10, [X29, #312]

0x4301f4 LDR	X10, [X11, #40]

0x4301f8 STP	X9, X8, [X29, #832]

0x4301fc LDR	X0, [X9, X8,LSL #3]

0x430200 STR	X10, [SP, #408]

0x430204 LDR	X10, [X11, #48]

0x430208 STR	X10, [SP, #328]

0x43020c LDR	X10, [X11, #56]

0x430210 STR	X10, [SP, #416]

0x430214 CBZ	X0, 430234

0x430218 MOVZ	W1, #8

0x43021c BL	4a6c90

0x430220 ORR	X25, XZR, X0

0x430224 B	430238

0x430228 STR	XZR, [SP, #408]

0x43022c ORR	X25, XZR, XZR

0x430230 B	430238

0x430234 ORR	X25, XZR, XZR

0x430238 LDUR	X13, [X29, #328]

0x43023c STR	XZR, [SP, #560]

0x430240 CMP	X13, #1

0x430244 B.LT	4302b0

0x430248 LDP	X11, X8, [X29, #824]

0x43024c LDUR	X9, [X29, #504]

0x430250 ORR	X10, XZR, XZR

0x430254 ORR	X12, XZR, XZR

0x430258 B	43026c

0x43025c HINT	#0

(664) 0x430260 STR	X12, [SP, #560]

(664) 0x430264 CMP	X12, X13

(664) 0x430268 B.GE	4302b0

(664) 0x43026c LDR	X14, [X8, X12,LSL #3]

(664) 0x430270 ADD	X12, X12, #1

(664) 0x430274 LDR	X15, [X8, X12,LSL #3]

(664) 0x430278 CMP	X14, X15

(664) 0x43027c B.GE	430260

  (665) 0x430280 LDR	X12, [X11, X14,LSL #3]

  (665) 0x430284 ADD	X14, X14, #1

  (665) 0x430288 LDR	X12, [X9, X12,LSL #3]

  (665) 0x43028c STR	X12, [X25, X10,LSL #3]

  (665) 0x430290 ADD	X10, X10, #1

  (665) 0x430294 LDR	X12, [SP, #560]

  (665) 0x430298 ADD	X12, X12, #1

  (665) 0x43029c LDR	X13, [X8, X12,LSL #3]

  (665) 0x4302a0 CMP	X14, X13

  (665) 0x4302a4 B.LT	430280

(664) 0x4302a8 LDUR	X13, [X29, #328]

(664) 0x4302ac B	430260

0x4302b0 LDR	X8, [SP, #528]

0x4302b4 CMP	X8, #1

0x4302b8 B.LE	4302d4

0x4302bc LDUR	X3, [X29, #288]

0x4302c0 LDR	X1, [SP, #368]

0x4302c4 MOVZ	W0, #11

0x4302c8 ORR	X2, XZR, X25

0x4302cc BL	480c50

0x4302d0 BL	481040

0x4302d4 LDUR	X8, [X29, #480]

0x4302d8 CMP	X8, #2

0x4302dc B.LT	430378

0x4302e0 LDUR	X13, [X29, #328]

0x4302e4 STR	XZR, [SP, #560]

0x4302e8 CMP	X13, #1

0x4302ec B.LT	430354

0x4302f0 LDP	X11, X8, [X29, #824]

0x4302f4 LDUR	X9, [X29, #472]

0x4302f8 ORR	X10, XZR, XZR

0x4302fc ORR	X12, XZR, XZR

0x430300 B	430310

(662) 0x430304 STR	X12, [SP, #560]

(662) 0x430308 CMP	X12, X13

(662) 0x43030c B.GE	430354

(662) 0x430310 LDR	X14, [X8, X12,LSL #3]

(662) 0x430314 ADD	X12, X12, #1

(662) 0x430318 LDR	X15, [X8, X12,LSL #3]

(662) 0x43031c CMP	X14, X15

(662) 0x430320 B.GE	430304

  (663) 0x430324 LDR	X12, [X11, X14,LSL #3]

  (663) 0x430328 ADD	X14, X14, #1

  (663) 0x43032c LDR	X12, [X9, X12,LSL #3]

  (663) 0x430330 STR	X12, [X25, X10,LSL #3]

  (663) 0x430334 ADD	X10, X10, #1

  (663) 0x430338 LDR	X12, [SP, #560]

  (663) 0x43033c ADD	X12, X12, #1

  (663) 0x430340 LDR	X13, [X8, X12,LSL #3]

  (663) 0x430344 CMP	X14, X13

  (663) 0x430348 B.LT	430324

(662) 0x43034c LDUR	X13, [X29, #328]

(662) 0x430350 B	430304

0x430354 LDR	X8, [SP, #528]

0x430358 CMP	X8, #1

0x43035c B.LE	430378

0x430360 LDUR	X3, [X29, #280]

0x430364 LDR	X1, [SP, #368]

0x430368 MOVZ	W0, #11

0x43036c ORR	X2, XZR, X25

0x430370 BL	480c50

0x430374 BL	481040

0x430378 ADRP	X0,

0x43037c ADD	X0, X0, #304

0x430380 ADRP	X2, 432380

0x430384 ADD	X2, X2, #2960

0x430388 SUB	X3, X29, #128

0x43038c SUB	X4, X29, #224

0x430390 STR	XZR, [SP, #616]

0x430394 STR	XZR, [SP, #600]

0x430398 ADD	X5, SP, #616

0x43039c ADD	X6, SP, #600

0x4303a0 MOVZ	W1, #4

0x4303a4 BL	40f600

0x4303a8 LDUR	X0, [X29, #384]

0x4303ac CBZ	X0, 4303f0

0x4303b0 MOVZ	W1, #8

0x4303b4 BL	4a6c90

0x4303b8 STR	X0, [SP, #576]

0x4303bc LDUR	X0, [X29, #384]

0x4303c0 MOVZ	W1, #8

0x4303c4 BL	4a6c90

0x4303c8 STR	X0, [SP, #688]

0x4303cc LDUR	X0, [X29, #384]

0x4303d0 MOVZ	W1, #8

0x4303d4 BL	4a6c90

0x4303d8 ORR	X19, XZR, X0

0x4303dc LDR	X0, [SP, #616]

0x4303e0 MOVZ	W1, #8

0x4303e4 BL	4a6c90

0x4303e8 ORR	X26, XZR, X0

0x4303ec B	4303f8

0x4303f0 ORR	X19, XZR, XZR

0x4303f4 ORR	X26, XZR, XZR

0x4303f8 SUB	X8, X28, #1

0x4303fc LDUR	X9, [X29, #344]

0x430400 STR	X8, [SP, #432]

0x430404 LDUR	X8, [X29, #368]

0x430408 STR	XZR, [X8], #8

0x43040c STR	XZR, [X9], #8

0x430410 STR	XZR, [SP, #560]

0x430414 LDR	X10, [SP, #632]

0x430418 CMP	X10, #1

0x43041c B.LT	4304c8

0x430420 LDUR	X10, [X29, #504]

0x430424 LDR	X11, [SP, #760]

0x430428 LDR	X12, [SP, #584]

0x43042c MOVN	X15, #0

0x430430 MOVZ	W16, #1

0x430434 ORR	X13, XZR, XZR

0x430438 ORR	X0, XZR, XZR

0x43043c LDR	X14, [SP, #592]

0x430440 LDR	X18, [SP, #432]

0x430444 LDUR	X17, [X29, #264]

0x430448 B	43048c

(661) 0x43044c STR	X0, [X11, X18,LSL #3]

(661) 0x430450 SUB	X18, X18, #1

(661) 0x430454 LDR	X0, [SP, #560]

(661) 0x430458 STR	XZR, [X8, X0,LSL #3]

(661) 0x43045c LDR	X0, [SP, #560]

(661) 0x430460 STR	XZR, [X9, X0,LSL #3]

(661) 0x430464 LDR	X0, [SP, #560]

(661) 0x430468 STR	X15, [X12, X0,LSL #3]

(661) 0x43046c LDR	X0, [SP, #560]

(661) 0x430470 STR	X15, [X14, X0,LSL #3]

(661) 0x430474 LDR	X0, [SP, #560]

(661) 0x430478 LDR	X1, [SP, #632]

(661) 0x43047c ADD	X0, X0, #1

(661) 0x430480 STR	X0, [SP, #560]

(661) 0x430484 CMP	X0, X1

(661) 0x430488 B.GE	4304c8

(661) 0x43048c LDR	X1, [X10, X0,LSL #3]

(661) 0x430490 CMN	X1, #1

(661) 0x430494 B.EQ	43044c

(661) 0x430498 CMP	X1, #1

(661) 0x43049c B.NE	430458

(661) 0x4304a0 STR	X13, [X14, X0,LSL #3]

(661) 0x4304a4 LDR	X0, [SP, #560]

(661) 0x4304a8 STR	X0, [X17, X13,LSL #3]

(661) 0x4304ac STR	XZR, [X12, X0,LSL #3]

(661) 0x4304b0 ADD	X13, X13, #1

(661) 0x4304b4 LDR	X0, [SP, #560]

(661) 0x4304b8 STR	X16, [X8, X0,LSL #3]

(661) 0x4304bc LDR	X0, [SP, #560]

(661) 0x4304c0 STR	XZR, [X9, X0,LSL #3]

(661) 0x4304c4 B	430474

0x4304c8 LDUR	X13, [X29, #328]

0x4304cc STR	XZR, [SP, #560]

0x4304d0 CMP	X13, #1

0x4304d4 B.LT	430548

0x4304d8 LDP	X11, X9, [X29, #824]

0x4304dc LDR	X10, [SP, #592]

0x4304e0 ORR	X8, XZR, XZR

0x4304e4 ORR	X12, XZR, XZR

0x4304e8 B	4304f8

(659) 0x4304ec STR	X12, [SP, #560]

(659) 0x4304f0 CMP	X12, X13

(659) 0x4304f4 B.GE	430548

(659) 0x4304f8 LDR	X14, [X9, X12,LSL #3]

(659) 0x4304fc ADD	X12, X12, #1

(659) 0x430500 LDR	X15, [X9, X12,LSL #3]

(659) 0x430504 CMP	X14, X15

(659) 0x430508 B.GE	4304ec

  (660) 0x43050c LDR	X12, [X11, X14,LSL #3]

  (660) 0x430510 ADD	X14, X14, #1

  (660) 0x430514 LDR	X12, [X10, X12,LSL #3]

  (660) 0x430518 CMP	X12, #0

  (660) 0x43051c CSEL	X13, XZR, X27, #11

  (660) 0x430520 ADD	X12, X13, X12

  (660) 0x430524 STR	X12, [X25, X8,LSL #3]

  (660) 0x430528 ADD	X8, X8, #1

  (660) 0x43052c LDR	X12, [SP, #560]

  (660) 0x430530 ADD	X12, X12, #1

  (660) 0x430534 LDR	X13, [X9, X12,LSL #3]

  (660) 0x430538 CMP	X14, X13

  (660) 0x43053c B.LT	43050c

(659) 0x430540 LDUR	X13, [X29, #328]

(659) 0x430544 B	4304ec

0x430548 LDR	X8, [SP, #528]

0x43054c CMP	X8, #1

0x430550 B.LE	43056c

0x430554 LDR	X1, [SP, #368]

0x430558 MOVZ	W0, #11

0x43055c ORR	X2, XZR, X25

0x430560 ORR	X3, XZR, X19

0x430564 BL	480c50

0x430568 BL	481040

0x43056c LDR	X8, [SP, #408]

0x430570 MOVZ	W1, #8

0x430574 ADD	X0, X8, #1

0x430578 BL	4a6c90

0x43057c ORR	X21, XZR, X0

0x430580 LDR	X0, [SP, #616]

0x430584 CBZ	X0, 430594

0x430588 MOVZ	W1, #8

0x43058c BL	4a6c90

0x430590 STUR	X0, [X29, #256]

0x430594 LDR	X8, [SP, #408]

0x430598 STR	XZR, [X21]

0x43059c CMP	X8, #1

0x4305a0 B.LT	430658

0x4305a4 LDUR	X9, [X29, #288]

0x4305a8 MOVN	X11, #0

0x4305ac ORR	X8, XZR, XZR

0x4305b0 ORR	X10, XZR, XZR

0x4305b4 B	4305d0

0x4305b8 HINT	#0

0x4305bc HINT	#0

    (656) 0x4305c0 LDR	X12, [SP, #408]

    (656) 0x4305c4 STR	X10, [X21, X8,LSL #3]

    (656) 0x4305c8 CMP	X8, X12

    (656) 0x4305cc B.EQ	430658

    (656) 0x4305d0 LDR	X12, [SP, #416]

    (656) 0x4305d4 LDR	X15, [X12, X8,LSL #3]

    (656) 0x4305d8 ADD	X8, X8, #1

    (656) 0x4305dc STR	X15, [SP, #560]

    (656) 0x4305e0 LDR	X12, [X12, X8,LSL #3]

    (656) 0x4305e4 CMP	X15, X12

    (656) 0x4305e8 B.GE	4305c0

  (658) 0x4305ec LDR	X12, [SP, #576]

  (658) 0x4305f0 LDR	X13, [SP, #688]

  (658) 0x4305f4 LDUR	X14, [X29, #256]

  (658) 0x4305f8 B	430628

0x4305fc HINT	#0

(657) 0x430600 STR	X11, [X12, X15,LSL #3]

(657) 0x430604 LDR	X15, [SP, #560]

(657) 0x430608 STR	X11, [X13, X15,LSL #3]

  (658) 0x43060c LDR	X15, [SP, #560]

  (658) 0x430610 LDR	X16, [SP, #416]

  (658) 0x430614 ADD	X15, X15, #1

  (658) 0x430618 STR	X15, [SP, #560]

  (658) 0x43061c LDR	X16, [X16, X8,LSL #3]

  (658) 0x430620 CMP	X15, X16

  (658) 0x430624 B.GE	4305c0

  (658) 0x430628 LDR	X16, [X9, X15,LSL #3]

  (658) 0x43062c CMP	X16, #1

  (658) 0x430630 B.NE	430600

  (658) 0x430634 STR	X10, [X13, X15,LSL #3]

  (658) 0x430638 LDR	X15, [SP, #560]

  (658) 0x43063c STR	X15, [X14, X10,LSL #3]

  (658) 0x430640 LDR	X15, [X19, X15,LSL #3]

  (658) 0x430644 STR	X15, [X26, X10,LSL #3]

  (658) 0x430648 ADD	X10, X10, #1

  (658) 0x43064c LDR	X15, [SP, #560]

  (658) 0x430650 STR	XZR, [X12, X15,LSL #3]

  (658) 0x430654 B	43060c

0x430658 ORR	X0, XZR, X19

0x43065c BL	4a6d90

0x430660 LDR	X8, [X29, #104]

0x430664 CBZ	X8, 4306e0

0x430668 MOVZ	W1, #8

0x43066c ORR	X0, XZR, X22

0x430670 BL	4a6c90

0x430674 STR	X0, [SP, #680]

0x430678 STR	XZR, [SP, #560]

0x43067c CMP	X22, #1

0x430680 B.LT	4306e0

0x430684 ORR	X8, XZR, XZR

0x430688 ORR	X9, XZR, XZR

0x43068c B	4306cc

0x430690 HINT	#0

0x430694 HINT	#0

0x430698 HINT	#0

0x43069c HINT	#0

(654) 0x4306a0 LDR	X10, [X24, X9,LSL #3]

(654) 0x4306a4 LDR	X11, [X20, X8,LSL #3]

(654) 0x4306a8 CMP	X10, X11

(654) 0x4306ac CSINV	X10, X8, XZR, #0

(654) 0x4306b0 CSINC	X8, X8, X8, #1

  (655) 0x4306b4 STR	X10, [X0, X9,LSL #3]

  (655) 0x4306b8 LDR	X9, [SP, #560]

  (655) 0x4306bc ADD	X9, X9, #1

  (655) 0x4306c0 STR	X9, [SP, #560]

  (655) 0x4306c4 CMP	X9, X22

  (655) 0x4306c8 B.GE	4306e0

  (655) 0x4306cc LDUR	X10, [X29, #384]

  (655) 0x4306d0 CMP	X8, X10

  (655) 0x4306d4 B.LT	4306a0

  (655) 0x4306d8 MOVN	X10, #0

  (655) 0x4306dc B	4306b4

0x4306e0 LDR	X8, [SP, #752]

0x4306e4 LDR	X18, [SP, #432]

0x4306e8 STP	XZR, XZR, [X8]

0x4306ec STR	XZR, [SP, #512]

0x4306f0 STR	X18, [SP, #560]

0x4306f4 LDR	X9, [SP, #624]

0x4306f8 STR	X9, [SP, #656]

0x4306fc CMP	X28, #1

0x430700 B.LT	430850

0x430704 LDR	X9, [SP, #760]

0x430708 LDP	X11, X10, [X29, #920]

0x43070c LDUR	X12, [X29, #504]

0x430710 MOVZ	W16, #1

0x430714 ORR	X19, XZR, XZR

0x430718 ORR	X23, XZR, XZR

0x43071c ORR	X20, XZR, XZR

0x430720 LDP	X14, X13, [X29, #904]

0x430724 LDUR	X15, [X29, #288]

0x430728 LDR	X17, [SP, #584]

0x43072c B	430750

0x430730 HINT	#0

0x430734 HINT	#0

0x430738 HINT	#0

0x43073c HINT	#0

(651) 0x430740 SUB	X18, X0, #1

(651) 0x430744 STR	X18, [SP, #560]

(651) 0x430748 CMP	X0, X23

(651) 0x43074c B.LE	43085c

(651) 0x430750 LDR	X18, [X9, X18,LSL #3]

(651) 0x430754 ADD	X0, X18, #1

(651) 0x430758 LDR	X1, [X10, X18,LSL #3]

(651) 0x43075c LDR	X3, [X10, X0,LSL #3]

(651) 0x430760 CMP	X1, X3

(651) 0x430764 B.GE	4307c0

(651) 0x430768 LDUR	X2, [X29, #368]

(651) 0x43076c LDR	X4, [SP, #584]

(651) 0x430770 B	43078c

0x430774 HINT	#0

0x430778 HINT	#0

0x43077c HINT	#0

  (653) 0x430780 ADD	X1, X1, #1

  (653) 0x430784 CMP	X1, X3

  (653) 0x430788 B.GE	4307c0

  (653) 0x43078c LDR	X5, [X11, X1,LSL #3]

  (653) 0x430790 LDR	X5, [X12, X5,LSL #3]

  (653) 0x430794 CMP	X5, #1

  (653) 0x430798 B.NE	430780

  (653) 0x43079c LDR	X3, [X2, X0,LSL #3]

  (653) 0x4307a0 ADD	X20, X20, #1

  (653) 0x4307a4 ADD	X3, X3, #1

  (653) 0x4307a8 STR	X3, [X2, X0,LSL #3]

  (653) 0x4307ac STR	X16, [X4, X18,LSL #3]

  (653) 0x4307b0 LDR	X3, [X10, X0,LSL #3]

  (653) 0x4307b4 B	430780

0x4307b8 HINT	#0

0x4307bc HINT	#0

(651) 0x4307c0 LDR	X1, [X13, X18,LSL #3]

(651) 0x4307c4 LDR	X4, [X13, X0,LSL #3]

(651) 0x4307c8 CMP	X1, X4

(651) 0x4307cc B.GE	430820

(651) 0x4307d0 LDUR	X2, [X29, #344]

(651) 0x4307d4 LDR	X3, [SP, #584]

(651) 0x4307d8 B	4307ec

0x4307dc HINT	#0

  (652) 0x4307e0 ADD	X1, X1, #1

  (652) 0x4307e4 CMP	X1, X4

  (652) 0x4307e8 B.GE	430820

  (652) 0x4307ec LDR	X5, [X14, X1,LSL #3]

  (652) 0x4307f0 LDR	X5, [X15, X5,LSL #3]

  (652) 0x4307f4 CMP	X5, #1

  (652) 0x4307f8 B.NE	4307e0

  (652) 0x4307fc LDR	X4, [X2, X0,LSL #3]

  (652) 0x430800 ADD	X19, X19, #1

  (652) 0x430804 ADD	X4, X4, #1

  (652) 0x430808 STR	X4, [X2, X0,LSL #3]

  (652) 0x43080c STR	X16, [X3, X18,LSL #3]

  (652) 0x430810 LDR	X4, [X13, X0,LSL #3]

  (652) 0x430814 B	4307e0

0x430818 HINT	#0

0x43081c HINT	#0

(651) 0x430820 LDR	X1, [X17, X18,LSL #3]

(651) 0x430824 LDR	X0, [SP, #560]

(651) 0x430828 CMP	X1, #1

(651) 0x43082c B.NE	430740

(651) 0x430830 LDR	X1, [X9, X23,LSL #3]

(651) 0x430834 ADD	X2, X0, #1

(651) 0x430838 STR	X2, [SP, #560]

(651) 0x43083c STR	X1, [X9, X0,LSL #3]

(651) 0x430840 STR	X18, [X9, X23,LSL #3]

(651) 0x430844 ADD	X23, X23, #1

(651) 0x430848 LDR	X0, [SP, #560]

(651) 0x43084c B	430740

0x430850 ORR	X20, XZR, XZR

0x430854 ORR	X23, XZR, XZR

0x430858 ORR	X19, XZR, XZR

0x43085c LDUR	X13, [X29, #328]

0x430860 STR	X23, [X8, #16]

0x430864 STR	XZR, [SP, #560]

0x430868 CMP	X13, #1

0x43086c B.LT	4308d4

0x430870 LDP	X11, X8, [X29, #824]

0x430874 LDR	X9, [SP, #584]

0x430878 ORR	X10, XZR, XZR

0x43087c ORR	X12, XZR, XZR

0x430880 B	430890

(649) 0x430884 STR	X12, [SP, #560]

(649) 0x430888 CMP	X12, X13

(649) 0x43088c B.GE	4308d4

(649) 0x430890 LDR	X14, [X8, X12,LSL #3]

(649) 0x430894 ADD	X12, X12, #1

(649) 0x430898 LDR	X15, [X8, X12,LSL #3]

(649) 0x43089c CMP	X14, X15

(649) 0x4308a0 B.GE	430884

  (650) 0x4308a4 LDR	X12, [X11, X14,LSL #3]

  (650) 0x4308a8 ADD	X14, X14, #1

  (650) 0x4308ac LDR	X12, [X9, X12,LSL #3]

  (650) 0x4308b0 STR	X12, [X25, X10,LSL #3]

  (650) 0x4308b4 ADD	X10, X10, #1

  (650) 0x4308b8 LDR	X12, [SP, #560]

  (650) 0x4308bc ADD	X12, X12, #1

  (650) 0x4308c0 LDR	X13, [X8, X12,LSL #3]

  (650) 0x4308c4 CMP	X14, X13

  (650) 0x4308c8 B.LT	4308a4

(649) 0x4308cc LDUR	X13, [X29, #328]

(649) 0x4308d0 B	430884

0x4308d4 LDR	X8, [SP, #528]

0x4308d8 CMP	X8, #1

0x4308dc B.LE	4308f8

0x4308e0 LDR	X3, [SP, #576]

0x4308e4 LDR	X1, [SP, #368]

0x4308e8 MOVZ	W0, #11

0x4308ec ORR	X2, XZR, X25

0x4308f0 BL	480c50

0x4308f4 BL	481040

0x4308f8 MOVZ	W8, #2

0x4308fc ADRP	X3,

0x430900 ADRP	X4,

0x430904 ADD	X0, SP, #544

0x430908 ADD	X1, SP, #552

0x43090c MOVZ	W2, #1

0x430910 STR	X8, [SP, #648]

0x430914 SUB	X8, X28, X23

0x430918 STR	X8, [SP, #544]

0x43091c LDR	X3, [X3, #4000]

0x430920 LDR	X4, [X4, #4032]

0x430924 LDR	X5, [SP, #376]

0x430928 BL	4a86a0

0x43092c LDR	X8, [SP, #552]

0x430930 CBZ	X8, 430b38

0x430934 LDR	X8, [SP, #648]

0x430938 CMP	X8, #9

0x43093c B.GT	430b38

0x430940 ADRP	X24,

0x430944 ADRP	X22,

0x430948 LDR	X24, [X24, #4000]

0x43094c LDR	X22, [X22, #4032]

0x430950 HINT	#0

0x430954 HINT	#0

0x430958 HINT	#0

0x43095c HINT	#0

(643) 0x430960 LDR	X16, [SP, #432]

(643) 0x430964 STR	X16, [SP, #560]

(643) 0x430968 CMP	X28, X23

(643) 0x43096c B.LE	430a40

(643) 0x430970 LDR	X9, [SP, #760]

(643) 0x430974 LDP	X11, X10, [X29, #920]

(643) 0x430978 LDR	X12, [SP, #584]

(643) 0x43097c LDP	X14, X13, [X29, #904]

(643) 0x430980 LDR	X15, [SP, #576]

(643) 0x430984 B	4309bc

  (646) 0x430988 LDR	X8, [X9, X23,LSL #3]

  (646) 0x43098c ADD	X18, X16, #1

  (646) 0x430990 STR	X18, [SP, #560]

  (646) 0x430994 STR	X8, [X9, X16,LSL #3]

  (646) 0x430998 STR	X17, [X9, X23,LSL #3]

  (646) 0x43099c ADD	X23, X23, #1

  (646) 0x4309a0 LDR	X8, [SP, #648]

  (646) 0x4309a4 STR	X8, [X12, X17,LSL #3]

  (646) 0x4309a8 LDR	X17, [SP, #560]

  (646) 0x4309ac SUB	X16, X17, #1

  (646) 0x4309b0 STR	X16, [SP, #560]

  (646) 0x4309b4 CMP	X17, X23

  (646) 0x4309b8 B.LE	430a40

  (646) 0x4309bc LDR	X17, [X9, X16,LSL #3]

  (646) 0x4309c0 ADD	X18, X17, #1

  (646) 0x4309c4 LDR	X2, [X10, X17,LSL #3]

  (646) 0x4309c8 LDR	X0, [X10, X18,LSL #3]

  (646) 0x4309cc SUBS	X0, X0, X2

  (646) 0x4309d0 B.LE	4309f8

  (646) 0x4309d4 SUB	X1, X8, #1

  (646) 0x4309d8 ADD	X2, X11, X2,LSL #3

  (646) 0x4309dc HINT	#0

    (648) 0x4309e0 LDR	X3, [X2], #8

    (648) 0x4309e4 LDR	X3, [X12, X3,LSL #3]

    (648) 0x4309e8 CMP	X3, X1

    (648) 0x4309ec B.EQ	430988

    (648) 0x4309f0 SUBS	X0, X0, #1

    (648) 0x4309f4 B.NE	4309e0

  (646) 0x4309f8 LDR	X1, [X13, X17,LSL #3]

  (646) 0x4309fc LDR	X18, [X13, X18,LSL #3]

  (646) 0x430a00 SUBS	X18, X18, X1

  (646) 0x430a04 B.LE	4309a8

  (646) 0x430a08 SUB	X0, X8, #1

  (646) 0x430a0c ADD	X1, X14, X1,LSL #3

  (646) 0x430a10 HINT	#0

  (646) 0x430a14 HINT	#0

  (646) 0x430a18 HINT	#0

  (646) 0x430a1c HINT	#0

    (647) 0x430a20 LDR	X2, [X1], #8

    (647) 0x430a24 LDR	X2, [X15, X2,LSL #3]

    (647) 0x430a28 CMP	X2, X0

    (647) 0x430a2c B.EQ	430988

    (647) 0x430a30 SUBS	X18, X18, #1

    (647) 0x430a34 B.NE	430a20

  (646) 0x430a38 B	4309a8

0x430a3c HINT	#0

(643) 0x430a40 LDR	X9, [SP, #752]

(643) 0x430a44 LDR	X5, [SP, #376]

(643) 0x430a48 ADD	X8, X8, #1

(643) 0x430a4c ADD	X0, SP, #544

(643) 0x430a50 ADD	X1, SP, #552

(643) 0x430a54 MOVZ	W2, #1

(643) 0x430a58 ORR	X3, XZR, X24

(643) 0x430a5c ORR	X4, XZR, X22

(643) 0x430a60 STR	X8, [SP, #648]

(643) 0x430a64 STR	X23, [X9, X8,LSL #3]

(643) 0x430a68 SUB	X8, X28, X23

(643) 0x430a6c STR	X8, [SP, #544]

(643) 0x430a70 BL	4a86a0

(643) 0x430a74 LDUR	X13, [X29, #328]

(643) 0x430a78 STR	XZR, [SP, #560]

(643) 0x430a7c CMP	X13, #1

(643) 0x430a80 B.LT	430b00

(643) 0x430a84 LDP	X11, X8, [X29, #824]

(643) 0x430a88 LDR	X9, [SP, #584]

(643) 0x430a8c ORR	X10, XZR, XZR

(643) 0x430a90 ORR	X12, XZR, XZR

(643) 0x430a94 B	430aac

0x430a98 HINT	#0

0x430a9c HINT	#0

  (644) 0x430aa0 STR	X12, [SP, #560]

  (644) 0x430aa4 CMP	X12, X13

  (644) 0x430aa8 B.GE	430b00

  (644) 0x430aac LDR	X14, [X8, X12,LSL #3]

  (644) 0x430ab0 ADD	X12, X12, #1

  (644) 0x430ab4 LDR	X15, [X8, X12,LSL #3]

  (644) 0x430ab8 CMP	X14, X15

  (644) 0x430abc B.GE	430aa0

    (645) 0x430ac0 LDR	X12, [X11, X14,LSL #3]

    (645) 0x430ac4 ADD	X14, X14, #1

    (645) 0x430ac8 LDR	X12, [X9, X12,LSL #3]

    (645) 0x430acc STR	X12, [X25, X10,LSL #3]

    (645) 0x430ad0 ADD	X10, X10, #1

    (645) 0x430ad4 LDR	X12, [SP, #560]

    (645) 0x430ad8 ADD	X12, X12, #1

    (645) 0x430adc LDR	X13, [X8, X12,LSL #3]

    (645) 0x430ae0 CMP	X14, X13

    (645) 0x430ae4 B.LT	430ac0

  (644) 0x430ae8 LDUR	X13, [X29, #328]

  (644) 0x430aec B	430aa0

0x430af0 HINT	#0

0x430af4 HINT	#0

0x430af8 HINT	#0

0x430afc HINT	#0

(643) 0x430b00 LDR	X8, [SP, #528]

(643) 0x430b04 CMP	X8, #1

(643) 0x430b08 B.LE	430b24

(643) 0x430b0c LDR	X3, [SP, #576]

(643) 0x430b10 LDR	X1, [SP, #368]

(643) 0x430b14 MOVZ	W0, #11

(643) 0x430b18 ORR	X2, XZR, X25

(643) 0x430b1c BL	480c50

(643) 0x430b20 BL	481040

(643) 0x430b24 LDR	X8, [SP, #552]

(643) 0x430b28 CBZ	X8, 430b38

(643) 0x430b2c LDR	X8, [SP, #648]

(643) 0x430b30 CMP	X8, #10

(643) 0x430b34 B.LT	430960

0x430b38 ORR	X0, XZR, X25

0x430b3c BL	4a6d90

0x430b40 LDR	X22, [SP, #648]

0x430b44 MOVZ	W1, #8

0x430b48 STR	X22, [SP, #640]

0x430b4c ORR	X0, XZR, X22

0x430b50 BL	4a6c90

0x430b54 MOVZ	W1, #8

0x430b58 STR	X0, [SP, #728]

0x430b5c ORR	X0, XZR, X20

0x430b60 BL	4a6c90

0x430b64 LDR	X8, [SP, #728]

0x430b68 MOVZ	W1, #8

0x430b6c STR	X0, [X8, #8]

0x430b70 LDR	X0, [SP, #632]

0x430b74 BL	4a6c90

0x430b78 STR	X0, [SP, #744]

0x430b7c LDR	X0, [SP, #632]

0x430b80 MOVZ	W1, #8

0x430b84 BL	4a6c90

0x430b88 LDR	X8, [SP, #528]

0x430b8c STR	X0, [SP, #736]

0x430b90 CMP	X8, #2

0x430b94 B.LT	430bc4

0x430b98 MOVZ	W1, #8

0x430b9c ORR	X0, XZR, X22

0x430ba0 BL	4a6c90

0x430ba4 STR	X0, [SP, #720]

0x430ba8 CBZ	X19, 430bcc

0x430bac MOVZ	W1, #8

0x430bb0 ORR	X0, XZR, X19

0x430bb4 BL	4a6c90

0x430bb8 ORR	X8, XZR, X0

0x430bbc LDR	X0, [SP, #720]

0x430bc0 B	430bd0

0x430bc4 ORR	X20, XZR, XZR

0x430bc8 B	430c08

0x430bcc ORR	X8, XZR, XZR

0x430bd0 MOVZ	W1, #8

0x430bd4 STR	X8, [X0, #8]

0x430bd8 ORR	X0, XZR, X22

0x430bdc BL	4a6c90

0x430be0 ORR	X20, XZR, X0

0x430be4 ADD	X0, X22, #1

0x430be8 MOVZ	W1, #8

0x430bec BL	4a6c90

0x430bf0 STR	XZR, [X0]

0x430bf4 STR	X0, [SP, #704]

0x430bf8 LDR	X8, [SP, #616]

0x430bfc STR	X26, [X20]

0x430c00 STR	X8, [X0, #8]

0x430c04 STR	X8, [SP, #480]

0x430c08 LDR	X8, [SP, #752]

0x430c0c LDP	X1, X9, [X8, #8]

0x430c10 STR	X1, [SP, #560]

0x430c14 CMP	X1, X9

0x430c18 B.GE	430d14

0x430c1c LDR	X11, [SP, #760]

0x430c20 LDR	X12, [SP, #744]

0x430c24 LDR	X13, [SP, #736]

0x430c28 ORR	X9, XZR, XZR

0x430c2c ORR	X10, XZR, XZR

0x430c30 LDP	X15, X14, [X29, #920]

0x430c34 LDUR	X16, [X29, #504]

0x430c38 LDP	X18, X17, [X29, #904]

0x430c3c LDUR	X0, [X29, #288]

0x430c40 B	430c5c

  (640) 0x430c44 LDR	X1, [SP, #560]

  (640) 0x430c48 LDR	X2, [X8, #16]

  (640) 0x430c4c ADD	X1, X1, #1

  (640) 0x430c50 STR	X1, [SP, #560]

  (640) 0x430c54 CMP	X1, X2

  (640) 0x430c58 B.GE	430d1c

  (640) 0x430c5c LDR	X2, [X11, X1,LSL #3]

  (640) 0x430c60 STR	X10, [X12, X2,LSL #3]

  (640) 0x430c64 STR	X9, [X13, X2,LSL #3]

  (640) 0x430c68 ADD	X1, X2, #1

  (640) 0x430c6c LDR	X3, [X14, X2,LSL #3]

  (640) 0x430c70 LDR	X6, [X14, X1,LSL #3]

  (640) 0x430c74 CMP	X3, X6

  (640) 0x430c78 B.GE	430cc0

  (640) 0x430c7c LDR	X4, [SP, #592]

  (640) 0x430c80 LDR	X5, [SP, #728]

  (640) 0x430c84 B	430c94

    (642) 0x430c88 ADD	X3, X3, #1

    (642) 0x430c8c CMP	X3, X6

    (642) 0x430c90 B.GE	430cc0

    (642) 0x430c94 LDR	X7, [X15, X3,LSL #3]

    (642) 0x430c98 LDR	X19, [X16, X7,LSL #3]

    (642) 0x430c9c CMP	X19, #1

    (642) 0x430ca0 B.NE	430c88

    (642) 0x430ca4 LDR	X6, [X4, X7,LSL #3]

    (642) 0x430ca8 LDR	X7, [X5, #8]

    (642) 0x430cac STR	X6, [X7, X10,LSL #3]

    (642) 0x430cb0 ADD	X10, X10, #1

    (642) 0x430cb4 LDR	X6, [X14, X1,LSL #3]

    (642) 0x430cb8 B	430c88

0x430cbc HINT	#0

  (640) 0x430cc0 LDR	X2, [X17, X2,LSL #3]

  (640) 0x430cc4 LDR	X5, [X17, X1,LSL #3]

  (640) 0x430cc8 CMP	X2, X5

  (640) 0x430ccc B.GE	430c44

(641) 0x430cd0 LDR	X3, [SP, #688]

(641) 0x430cd4 LDR	X4, [SP, #720]

(641) 0x430cd8 B	430cec

0x430cdc HINT	#0

(641) 0x430ce0 ADD	X2, X2, #1

(641) 0x430ce4 CMP	X2, X5

(641) 0x430ce8 B.GE	430c44

(641) 0x430cec LDR	X6, [X18, X2,LSL #3]

(641) 0x430cf0 LDR	X7, [X0, X6,LSL #3]

(641) 0x430cf4 CMP	X7, #1

(641) 0x430cf8 B.NE	430ce0

(641) 0x430cfc LDR	X5, [X3, X6,LSL #3]

(641) 0x430d00 LDR	X6, [X4, #8]

(641) 0x430d04 STR	X5, [X6, X9,LSL #3]

(641) 0x430d08 ADD	X9, X9, #1

(641) 0x430d0c LDR	X5, [X17, X1,LSL #3]

(641) 0x430d10 B	430ce0

0x430d14 ORR	X10, XZR, XZR

0x430d18 ORR	X9, XZR, XZR

0x430d1c LDR	X8, [SP, #656]

0x430d20 STR	X21, [SP, #296]

0x430d24 ADD	X8, X8, X10

0x430d28 STR	X8, [SP, #656]

0x430d2c LDR	X8, [SP, #512]

0x430d30 ADD	X8, X8, X9

0x430d34 STR	X8, [SP, #512]

0x430d38 LDR	X8, [SP, #528]

0x430d3c CMP	X8, #2

0x430d40 B.LT	430e0c

0x430d44 MOVZ	W0, #1

0x430d48 MOVZ	W1, #112

0x430d4c BL	4a6c90

0x430d50 MOVZ	W1, #8

0x430d54 STR	X0, [SP, #384]

0x430d58 ORR	X0, XZR, X22

0x430d5c BL	4a6c90

0x430d60 MOVZ	W1, #8

0x430d64 ORR	X19, XZR, X0

0x430d68 ORR	X0, XZR, X22

0x430d6c BL	4a6c90

0x430d70 MOVZ	W1, #8

0x430d74 STR	X0, [SP, #400]

0x430d78 ORR	X0, XZR, X22

0x430d7c BL	4a6c90

0x430d80 LDUR	X8, [X29, #384]

0x430d84 STR	X0, [SP, #712]

0x430d88 MOVZ	W1, #8

0x430d8c ADD	X0, X8, #1

0x430d90 BL	4a6c90

0x430d94 STR	X0, [SP, #696]

0x430d98 LDUR	X0, [X29, #384]

0x430d9c CBZ	X0, 430dac

0x430da0 MOVZ	W1, #8

0x430da4 BL	4a6c90

0x430da8 STUR	X0, [X29, #304]

0x430dac LDP	X8, X9, [X29, #832]

0x430db0 LDR	X0, [X8, X9,LSL #3]

0x430db4 CBZ	X0, 430dc4

0x430db8 MOVZ	W1, #8

0x430dbc BL	4a6c90

0x430dc0 STUR	X0, [X29, #296]

0x430dc4 ADRP	X0,

0x430dc8 ADD	X0, X0, #376

0x430dcc ADRP	X2, 432dcc

0x430dd0 ADD	X2, X2, #3360

0x430dd4 SUB	X3, X29, #128

0x430dd8 ADD	X4, SP, #696

0x430ddc MOVZ	W1, #2

0x430de0 BL	40f600

0x430de4 ADRP	X0,

0x430de8 ADD	X0, X0, #448

0x430dec ADRP	X2, 432dec

0x430df0 ADD	X2, X2, #3552

0x430df4 SUB	X3, X29, #192

0x430df8 SUB	X4, X29, #184

0x430dfc SUB	X5, X29, #216

0x430e00 MOVZ	W1, #3

0x430e04 BL	40f600

0x430e08 B	430e14

0x430e0c STR	XZR, [SP, #400]

0x430e10 ORR	X19, XZR, XZR

0x430e14 MOVZ	W8, #2

0x430e18 STR	X20, [SP, #432]

0x430e1c STR	X19, [SP, #392]

0x430e20 STR	X8, [SP, #648]

0x430e24 CMP	X22, #2

0x430e28 B.LE	431694

0x430e2c LDR	X22, [SP, #416]

0x430e30 SUB	X23, X20, #8

0x430e34 SUB	X28, X29, #168

0x430e38 ADRP	X26,

0x430e3c ADD	X26, X26, #544

0x430e40 ADRP	X21, 432e40

0x430e44 ADD	X21, X21, #3792

0x430e48 STP	XZR, XZR, [SP, #352]

0x430e4c STR	XZR, [SP, #424]

0x430e50 ORR	X19, XZR, XZR

0x430e54 STR	X23, [SP, #344]

0x430e58 B	430f7c

0x430e5c HINT	#0

      (625) 0x430e60 LDR	X8, [SP, #752]

      (625) 0x430e64 LDR	X9, [SP, #648]

      (625) 0x430e68 ADD	X3, SP, #464

      (625) 0x430e6c ADD	X4, SP, #752

      (625) 0x430e70 ADD	X5, SP, #648

      (625) 0x430e74 ADD	X6, SP, #624

      (625) 0x430e78 ADD	X7, SP, #480

      (625) 0x430e7c ADRP	X0,

      (625) 0x430e80 ADD	X0, X0, #640

      (625) 0x430e84 MOVZ	W1, #29

      (625) 0x430e88 ADRP	X2, 433e88

      (625) 0x430e8c ADD	X2, X2, #176

      (625) 0x430e90 ADD	X8, X8, X9,LSL #3

      (625) 0x430e94 LDP	X8, X9, [X8]

      (625) 0x430e98 SUB	X8, X9, X8

      (625) 0x430e9c STR	X8, [SP, #464]

      (625) 0x430ea0 ADD	X8, SP, #528

      (625) 0x430ea4 STR	X8, [SP, #184]

      (625) 0x430ea8 ADD	X8, SP, #512

      (625) 0x430eac STR	X8, [SP, #176]

      (625) 0x430eb0 ADD	X8, SP, #656

      (625) 0x430eb4 STR	X8, [SP, #168]

      (625) 0x430eb8 ADD	X8, SP, #448

      (625) 0x430ebc STR	X8, [SP, #160]

      (625) 0x430ec0 ADD	X8, SP, #440

      (625) 0x430ec4 STR	X8, [SP, #152]

      (625) 0x430ec8 ADD	X8, SP, #456

      (625) 0x430ecc STR	X8, [SP, #144]

      (625) 0x430ed0 ADD	X8, SP, #712

      (625) 0x430ed4 STR	X8, [SP, #136]

      (625) 0x430ed8 ADD	X8, SP, #696

      (625) 0x430edc STR	X8, [SP, #128]

      (625) 0x430ee0 SUB	X8, X29, #208

      (625) 0x430ee4 STR	X8, [SP, #120]

      (625) 0x430ee8 ADD	X8, SP, #576

      (625) 0x430eec STR	X8, [SP, #112]

      (625) 0x430ef0 SUB	X8, X29, #120

      (625) 0x430ef4 STR	X8, [SP, #104]

      (625) 0x430ef8 SUB	X8, X29, #112

      (625) 0x430efc STR	X8, [SP, #96]

      (625) 0x430f00 ADD	X8, SP, #720

      (625) 0x430f04 STP	X28, X8, [SP, #80]

      (625) 0x430f08 ADD	X8, SP, #728

      (625) 0x430f0c STP	X10, X8, [SP, #64]

      (625) 0x430f10 ADD	X8, SP, #584

      (625) 0x430f14 STR	X8, [SP, #56]

      (625) 0x430f18 SUB	X8, X29, #104

      (625) 0x430f1c STR	X8, [SP, #48]

      (625) 0x430f20 SUB	X8, X29, #96

      (625) 0x430f24 STR	X8, [SP, #40]

      (625) 0x430f28 ADD	X8, SP, #736

      (625) 0x430f2c STR	X8, [SP, #32]

      (625) 0x430f30 ADD	X8, SP, #744

      (625) 0x430f34 STR	X8, [SP, #24]

      (625) 0x430f38 ADD	X8, SP, #760

      (625) 0x430f3c STR	X8, [SP, #16]

      (625) 0x430f40 ADD	X8, SP, #616

      (625) 0x430f44 STR	X8, [SP, #8]

      (625) 0x430f48 ADD	X8, SP, #488

      (625) 0x430f4c STR	X8, [SP]

      (625) 0x430f50 BL	40f600

      (625) 0x430f54 LDR	X8, [SP, #648]

      (625) 0x430f58 LDR	X9, [SP, #640]

      (625) 0x430f5c ADRP	X26,

      (625) 0x430f60 ADD	X26, X26, #544

      (625) 0x430f64 ADRP	X21, 432f64

      (625) 0x430f68 ADD	X21, X21, #3792

      (625) 0x430f6c ADD	X8, X8, #1

      (625) 0x430f70 STR	X8, [SP, #648]

      (625) 0x430f74 CMP	X8, X9

      (625) 0x430f78 B.GE	43169c

      (625) 0x430f7c LDR	X8, [SP, #528]

      (625) 0x430f80 CMP	X8, #1

      (625) 0x430f84 B.LE	431098

      (625) 0x430f88 LDUR	X8, [X29, #328]

      (625) 0x430f8c MOVZ	W1, #8

      (625) 0x430f90 ADD	X0, X8, #1

      (625) 0x430f94 BL	4a6c90

      (625) 0x430f98 LDR	X8, [SP, #648]

      (625) 0x430f9c LDR	X28, [SP, #392]

      (625) 0x430fa0 MOVZ	W1, #8

      (625) 0x430fa4 SUB	X25, X29, #216

      (625) 0x430fa8 SUB	X24, X29, #168

      (625) 0x430fac STR	X0, [X28, X8,LSL #3]

      (625) 0x430fb0 LDR	X8, [SP, #408]

      (625) 0x430fb4 ADD	X0, X8, #1

      (625) 0x430fb8 BL	4a6c90

      (625) 0x430fbc LDR	X8, [SP, #648]

      (625) 0x430fc0 LDR	X9, [SP, #400]

      (625) 0x430fc4 STR	XZR, [SP, #504]

      (625) 0x430fc8 STR	X0, [X9, X8,LSL #3]

      (625) 0x430fcc LDR	X8, [X28, X8,LSL #3]

      (625) 0x430fd0 STR	XZR, [X8]

      (625) 0x430fd4 STR	XZR, [SP, #560]

      (625) 0x430fd8 LDUR	X8, [X29, #328]

      (625) 0x430fdc CMP	X8, #1

      (625) 0x430fe0 B.LT	431048

        (639) 0x430fe4 ADD	X8, SP, #504

        (639) 0x430fe8 SUB	X3, X29, #192

        (639) 0x430fec ADD	X4, SP, #560

        (639) 0x430ff0 SUB	X5, X29, #200

        (639) 0x430ff4 ADD	X6, SP, #584

        (639) 0x430ff8 ADD	X7, SP, #648

        (639) 0x430ffc ORR	X0, XZR, X26

        (639) 0x431000 ORR	X2, XZR, X21

        (639) 0x431004 STP	X24, X8, [SP, #16]

        (639) 0x431008 SUB	X8, X29, #144

        (639) 0x43100c MOVZ	W1, #9

        (639) 0x431010 STP	X25, X8, [SP]

        (639) 0x431014 BL	40f600

        (639) 0x431018 LDR	X9, [SP, #648]

        (639) 0x43101c LDR	X10, [SP, #560]

        (639) 0x431020 LDR	X8, [SP, #504]

        (639) 0x431024 LDR	X9, [X28, X9,LSL #3]

        (639) 0x431028 ADD	X9, X9, X10,LSL #3

        (639) 0x43102c STR	X8, [X9, #8]

        (639) 0x431030 LDR	X8, [SP, #560]

        (639) 0x431034 LDUR	X9, [X29, #328]

        (639) 0x431038 ADD	X8, X8, #1

        (639) 0x43103c STR	X8, [SP, #560]

        (639) 0x431040 CMP	X8, X9

        (639) 0x431044 B.LT	430fe4

      (625) 0x431048 LDR	X8, [SP, #696]

      (625) 0x43104c LDUR	X2, [X29, #296]

      (625) 0x431050 LDR	X1, [SP, #368]

      (625) 0x431054 MOVZ	W0, #11

      (625) 0x431058 ADD	X3, X8, #8

      (625) 0x43105c BL	480c50

      (625) 0x431060 BL	481040

      (625) 0x431064 LDR	X8, [SP, #504]

      (625) 0x431068 LDR	X9, [SP, #352]

      (625) 0x43106c CMP	X8, X9

      (625) 0x431070 B.LE	431090

      (625) 0x431074 ORR	X0, XZR, X19

      (625) 0x431078 BL	4a6d90

      (625) 0x43107c LDR	X0, [SP, #504]

      (625) 0x431080 MOVZ	W1, #8

      (625) 0x431084 BL	4a6c90

      (625) 0x431088 LDR	X8, [SP, #504]

      (625) 0x43108c ORR	X19, XZR, X0

      (625) 0x431090 SUB	X28, X29, #168

      (625) 0x431094 STR	X8, [SP, #352]

      (625) 0x431098 LDUR	X13, [X29, #328]

      (625) 0x43109c STR	XZR, [SP, #560]

      (625) 0x4310a0 CMP	X13, #1

      (625) 0x4310a4 B.LT	431220

      (625) 0x4310a8 LDP	X9, X8, [X29, #824]

      (625) 0x4310ac LDR	X10, [SP, #584]

      (625) 0x4310b0 ORR	X11, XZR, XZR

      (625) 0x4310b4 ORR	X0, XZR, XZR

      (625) 0x4310b8 B	4310d0

0x4310bc HINT	#0

        (634) 0x4310c0 LDUR	X13, [X29, #328]

        (634) 0x4310c4 STR	X0, [SP, #560]

        (634) 0x4310c8 CMP	X0, X13

        (634) 0x4310cc B.GE	431220

        (634) 0x4310d0 LDR	X12, [X8, X0,LSL #3]

        (634) 0x4310d4 ADD	X0, X0, #1

        (634) 0x4310d8 LDR	X14, [X8, X0,LSL #3]

        (634) 0x4310dc CMP	X12, X14

        (634) 0x4310e0 B.GE	4310c4

        (634) 0x4310e4 LDR	X15, [SP, #728]

        (634) 0x4310e8 LDR	X18, [SP, #720]

        (634) 0x4310ec LDR	X13, [SP, #744]

        (634) 0x4310f0 SUB	X15, X15, #8

        (634) 0x4310f4 LDUR	X14, [X29, #368]

        (634) 0x4310f8 LDR	X16, [SP, #736]

        (634) 0x4310fc LDUR	X17, [X29, #344]

        (634) 0x431100 SUB	X18, X18, #8

        (634) 0x431104 B	431124

          (635) 0x431108 ORR	X11, XZR, X2

          (635) 0x43110c LDR	X0, [SP, #560]

          (635) 0x431110 ADD	X12, X12, #1

          (635) 0x431114 ADD	X0, X0, #1

          (635) 0x431118 LDR	X1, [X8, X0,LSL #3]

          (635) 0x43111c CMP	X12, X1

          (635) 0x431120 B.GE	4310c0

          (635) 0x431124 LDR	X0, [X9, X12,LSL #3]

          (635) 0x431128 LDR	X2, [SP, #648]

          (635) 0x43112c LDR	X1, [X10, X0,LSL #3]

          (635) 0x431130 SUB	X2, X2, #1

          (635) 0x431134 CMP	X1, X2

          (635) 0x431138 B.NE	43110c

          (635) 0x43113c ADD	X1, X0, #1

          (635) 0x431140 LDR	X2, [X14, X1,LSL #3]

          (635) 0x431144 CMP	X2, #1

          (635) 0x431148 B.LT	43118c

          (635) 0x43114c LDR	X3, [X13, X0,LSL #3]

          (635) 0x431150 ADD	X4, X2, X3

          (635) 0x431154 HINT	#0

          (635) 0x431158 HINT	#0

          (635) 0x43115c HINT	#0

            (638) 0x431160 LDR	X2, [SP, #648]

            (638) 0x431164 LDR	X2, [X15, X2,LSL #3]

            (638) 0x431168 LDR	X2, [X2, X3,LSL #3]

            (638) 0x43116c ADD	X3, X3, #1

            (638) 0x431170 ADD	X5, X2, X27

            (638) 0x431174 ADD	X2, X11, #1

            (638) 0x431178 STR	X5, [X19, X11,LSL #3]

            (638) 0x43117c ORR	X11, XZR, X2

            (638) 0x431180 CMP	X3, X4

            (638) 0x431184 B.LT	431160

          (635) 0x431188 B	431190

          (635) 0x43118c ORR	X2, XZR, X11

          (635) 0x431190 LDR	X11, [X17, X1,LSL #3]

          (635) 0x431194 CMP	X11, #1

          (635) 0x431198 B.LT	431108

          (635) 0x43119c LDR	X0, [X16, X0,LSL #3]

          (635) 0x4311a0 ADD	X1, X11, X0

          (635) 0x4311a4 ORR	X11, XZR, X2

          (635) 0x4311a8 B	4311d0

            (636) 0x4311ac LDUR	X3, [X4, #496]

            (636) 0x4311b0 SUB	X2, X2, X3

            (636) 0x4311b4 LDR	X3, [X5]

            (636) 0x4311b8 LDR	X2, [X3, X2,LSL #3]

            (636) 0x4311bc STR	X2, [X19, X11,LSL #3]

            (636) 0x4311c0 ADD	X11, X11, #1

            (636) 0x4311c4 ADD	X0, X0, #1

            (636) 0x4311c8 CMP	X0, X1

            (636) 0x4311cc B.GE	43110c

            (636) 0x4311d0 LDR	X3, [SP, #648]

            (636) 0x4311d4 LDR	X4, [SP, #704]

            (636) 0x4311d8 ORR	X5, XZR, X23

            (636) 0x4311dc LDR	X2, [X18, X3,LSL #3]

            (636) 0x4311e0 CMP	X3, #1

            (636) 0x4311e4 ADD	X4, X4, #8

            (636) 0x4311e8 CSINC	X3, X3, XZR, #12

            (636) 0x4311ec SUB	X3, X3, #1

            (636) 0x4311f0 LDR	X2, [X2, X0,LSL #3]

            (636) 0x4311f4 HINT	#0

            (636) 0x4311f8 HINT	#0

            (636) 0x4311fc HINT	#0

              (637) 0x431200 CBZ	X3, 4311c4

              (637) 0x431204 LDR	X6, [X4], #8

              (637) 0x431208 ADD	X5, X5, #8

              (637) 0x43120c SUB	X3, X3, #1

              (637) 0x431210 CMP	X2, X6

              (637) 0x431214 B.GE	431200

            (636) 0x431218 B	4311ac

0x43121c HINT	#0

      (625) 0x431220 LDR	X8, [SP, #528]

      (625) 0x431224 CMP	X8, #1

      (625) 0x431228 B.LE	4313b0

      (625) 0x43122c LDR	X8, [SP, #648]

      (625) 0x431230 LDR	X9, [SP, #400]

      (625) 0x431234 LDR	X8, [X9, X8,LSL #3]

      (625) 0x431238 STR	XZR, [X8]

      (625) 0x43123c LDR	X8, [SP, #408]

      (625) 0x431240 STR	XZR, [SP, #560]

      (625) 0x431244 CMP	X8, #1

      (625) 0x431248 B.LT	4312e4

      (625) 0x43124c LDR	X8, [SP, #576]

      (625) 0x431250 ORR	X24, XZR, XZR

      (625) 0x431254 ORR	X9, XZR, XZR

      (625) 0x431258 B	431284

0x43125c HINT	#0

        (632) 0x431260 LDR	X9, [SP, #648]

        (632) 0x431264 LDP	X11, X10, [SP, #400]

        (632) 0x431268 LDR	X9, [X11, X9,LSL #3]

        (632) 0x43126c STR	X24, [X9, X13,LSL #3]

        (632) 0x431270 LDR	X9, [SP, #560]

        (632) 0x431274 ADD	X9, X9, #1

        (632) 0x431278 STR	X9, [SP, #560]

        (632) 0x43127c CMP	X9, X10

        (632) 0x431280 B.GE	4312e8

        (632) 0x431284 ADD	X13, X9, #1

        (632) 0x431288 LDR	X10, [X22, X9,LSL #3]

        (632) 0x43128c LDR	X11, [X22, X13,LSL #3]

        (632) 0x431290 CMP	X10, X11

        (632) 0x431294 B.GE	431260

        (632) 0x431298 LDR	X12, [SP, #696]

        (632) 0x43129c LDUR	X11, [X29, #304]

        (632) 0x4312a0 ADD	X12, X12, #8

        (632) 0x4312a4 B	4312bc

          (633) 0x4312a8 ADD	X13, X9, #1

          (633) 0x4312ac ADD	X10, X10, #1

          (633) 0x4312b0 LDR	X14, [X22, X13,LSL #3]

          (633) 0x4312b4 CMP	X10, X14

          (633) 0x4312b8 B.GE	431260

          (633) 0x4312bc LDR	X14, [SP, #648]

          (633) 0x4312c0 LDR	X13, [X8, X10,LSL #3]

          (633) 0x4312c4 SUB	X14, X14, #1

          (633) 0x4312c8 CMP	X13, X14

          (633) 0x4312cc B.NE	4312a8

          (633) 0x4312d0 STR	X24, [X11, X10,LSL #3]

          (633) 0x4312d4 LDR	X9, [X12, X10,LSL #3]

          (633) 0x4312d8 ADD	X24, X9, X24

          (633) 0x4312dc LDR	X9, [SP, #560]

          (633) 0x4312e0 B	4312a8

      (625) 0x4312e4 ORR	X24, XZR, XZR

      (625) 0x4312e8 LDUR	X8, [X29, #328]

      (625) 0x4312ec LDP	X9, X10, [SP, #376]

      (625) 0x4312f0 LDR	X11, [SP, #408]

      (625) 0x4312f4 STP	X9, X8, [X10]

      (625) 0x4312f8 LDR	X8, [SP, #336]

      (625) 0x4312fc LDR	X9, [SP, #392]

      (625) 0x431300 STR	X8, [X10, #16]

      (625) 0x431304 LDR	X8, [SP, #648]

      (625) 0x431308 LDR	X9, [X9, X8,LSL #3]

      (625) 0x43130c STR	X9, [X10, #24]

      (625) 0x431310 LDR	X9, [SP, #328]

      (625) 0x431314 STP	X11, X9, [X10, #40]

      (625) 0x431318 LDR	X9, [SP, #400]

      (625) 0x43131c LDR	X9, [X9, X8,LSL #3]

      (625) 0x431320 STR	X9, [X10, #56]

      (625) 0x431324 CBZ	X24, 431354

      (625) 0x431328 MOVZ	W1, #8

      (625) 0x43132c ORR	X0, XZR, X24

      (625) 0x431330 BL	4a6c90

      (625) 0x431334 LDR	X8, [SP, #712]

      (625) 0x431338 LDR	X9, [SP, #648]

      (625) 0x43133c MOVZ	W1, #8

      (625) 0x431340 STR	X0, [X8, X9,LSL #3]

      (625) 0x431344 ORR	X0, XZR, X24

      (625) 0x431348 BL	4a6c90

      (625) 0x43134c LDR	X8, [SP, #648]

      (625) 0x431350 B	431360

      (625) 0x431354 LDR	X9, [SP, #712]

      (625) 0x431358 ORR	X0, XZR, XZR

      (625) 0x43135c STR	XZR, [X9, X8,LSL #3]

      (625) 0x431360 ADD	X8, X20, X8,LSL #3

      (625) 0x431364 LDR	X9, [SP, #648]

      (625) 0x431368 LDR	X1, [SP, #384]

      (625) 0x43136c ORR	X2, XZR, X19

      (625) 0x431370 STUR	X0, [X8, #504]

      (625) 0x431374 MOVZ	W0, #11

      (625) 0x431378 LDR	X8, [SP, #712]

      (625) 0x43137c LDR	X3, [X8, X9,LSL #3]

      (625) 0x431380 BL	480c50

      (625) 0x431384 BL	481040

      (625) 0x431388 LDR	X8, [SP, #360]

      (625) 0x43138c CMP	X24, X8

      (625) 0x431390 B.LE	4313ac

      (625) 0x431394 LDR	X0, [SP, #424]

      (625) 0x431398 BL	4a6d90

      (625) 0x43139c MOVZ	W1, #8

      (625) 0x4313a0 ORR	X0, XZR, X24

      (625) 0x4313a4 BL	4a6c90

      (625) 0x4313a8 STR	X0, [SP, #424]

      (625) 0x4313ac STR	X24, [SP, #360]

      (625) 0x4313b0 LDR	X8, [SP, #408]

      (625) 0x4313b4 STR	XZR, [SP, #560]

      (625) 0x4313b8 CMP	X8, #1

      (625) 0x4313bc B.LT	431644

      (625) 0x4313c0 LDR	X28, [X22, XZR,LSL #3]

      (625) 0x4313c4 ORR	X25, XZR, XZR

      (625) 0x4313c8 ORR	X21, XZR, XZR

      (625) 0x4313cc ORR	X8, XZR, XZR

      (625) 0x4313d0 B	4313f0

0x4313d4 HINT	#0

0x4313d8 HINT	#0

0x4313dc HINT	#0

        (629) 0x4313e0 LDR	X8, [SP, #560]

        (629) 0x4313e4 LDR	X22, [SP, #416]

        (629) 0x4313e8 ORR	X21, XZR, X9

        (629) 0x4313ec ADD	X28, X28, #1

        (629) 0x4313f0 ADD	X9, X8, #1

        (629) 0x4313f4 LDR	X10, [X22, X9,LSL #3]

        (629) 0x4313f8 CMP	X28, X10

        (629) 0x4313fc B.GE	431538

        (629) 0x431400 LDR	X9, [SP, #576]

        (629) 0x431404 LDR	X10, [SP, #648]

        (629) 0x431408 LDR	X9, [X9, X28,LSL #3]

        (629) 0x43140c SUB	X10, X10, #1

        (629) 0x431410 CMP	X9, X10

        (629) 0x431414 B.NE	4313ec

        (629) 0x431418 LDR	X9, [SP, #696]

        (629) 0x43141c ADD	X9, X9, X28,LSL #3

        (629) 0x431420 LDR	X9, [X9, #8]

        (629) 0x431424 CMP	X9, #1

        (629) 0x431428 B.LT	431530

        (629) 0x43142c ORR	X22, XZR, X21

        (629) 0x431430 B	431464

0x431434 HINT	#0

0x431438 HINT	#0

0x43143c HINT	#0

          (630) 0x431440 ORN	X8, XZR, X10

          (630) 0x431444 STR	X8, [X9, X22,LSL #3]

          (630) 0x431448 LDR	X8, [SP, #696]

          (630) 0x43144c ADD	X22, X22, #1

          (630) 0x431450 ADD	X8, X8, X28,LSL #3

          (630) 0x431454 LDR	X8, [X8, #8]

          (630) 0x431458 ADD	X9, X8, X21

          (630) 0x43145c CMP	X22, X9

          (630) 0x431460 B.GE	4313e0

          (630) 0x431464 LDR	X9, [SP, #712]

          (630) 0x431468 LDR	X8, [SP, #648]

          (630) 0x43146c LDR	X9, [X9, X8,LSL #3]

          (630) 0x431470 LDR	X24, [X9, X22,LSL #3]

          (630) 0x431474 SUBS	X10, X24, X27

          (630) 0x431478 B.MI	431488

          (630) 0x43147c LDR	X11, [SP, #624]

          (630) 0x431480 CMP	X10, X11

          (630) 0x431484 B.LT	431440

          (630) 0x431488 ORR	X26, XZR, X27

          (630) 0x43148c CMP	X8, #2

          (630) 0x431490 B.LT	4314e0

          (630) 0x431494 LDR	X23, [SP, #704]

          (630) 0x431498 MOVZ	W27, #1

          (630) 0x43149c HINT	#0

            (631) 0x4314a0 LDP	X9, X8, [X23]

            (631) 0x4314a4 LDR	X0, [X20]

            (631) 0x4314a8 ORR	X1, XZR, X24

            (631) 0x4314ac SUB	X2, X8, X9

            (631) 0x4314b0 BL	4a5f40

            (631) 0x4314b4 TBZ	X0, #63, 43150c

            (631) 0x4314b8 LDR	X8, [SP, #648]

            (631) 0x4314bc SUB	X9, X8, #1

            (631) 0x4314c0 TBZ	X0, #63, 4314e4

            (631) 0x4314c4 ADD	X23, X23, #8

            (631) 0x4314c8 ADD	X10, X27, #1

            (631) 0x4314cc ADD	X20, X20, #8

            (631) 0x4314d0 CMP	X27, X9

            (631) 0x4314d4 ORR	X27, XZR, X10

            (631) 0x4314d8 B.LT	4314a0

          (630) 0x4314dc B	4314e4

          (630) 0x4314e0 SUB	X9, X8, #1

          (630) 0x4314e4 LDR	X10, [SP, #712]

          (630) 0x4314e8 LDR	X20, [SP, #432]

          (630) 0x4314ec LDR	X8, [X10, X8,LSL #3]

          (630) 0x4314f0 LDR	X9, [X20, X9,LSL #3]

          (630) 0x4314f4 LDR	X8, [X8, X22,LSL #3]

          (630) 0x4314f8 STR	X8, [X9, X25,LSL #3]

          (630) 0x4314fc LDR	X8, [SP, #424]

          (630) 0x431500 STR	X22, [X8, X25,LSL #3]

          (630) 0x431504 ADD	X25, X25, #1

          (630) 0x431508 B	431528

          (630) 0x43150c LDR	X9, [SP, #712]

          (630) 0x431510 LDR	X10, [SP, #648]

          (630) 0x431514 LDR	X8, [X23]

          (630) 0x431518 ADD	X8, X8, X0

          (630) 0x43151c LDR	X9, [X9, X10,LSL #3]

          (630) 0x431520 LDR	X20, [SP, #432]

          (630) 0x431524 STR	X8, [X9, X22,LSL #3]

          (630) 0x431528 ORR	X27, XZR, X26

          (630) 0x43152c B	431448

        (629) 0x431530 ADD	X21, X9, X21

        (629) 0x431534 B	4313ec

        (629) 0x431538 LDR	X10, [SP, #408]

        (629) 0x43153c STR	X9, [SP, #560]

        (629) 0x431540 ORR	X8, XZR, X9

        (629) 0x431544 CMP	X9, X10

        (629) 0x431548 B.GE	431560

        (629) 0x43154c LDR	X28, [X22, X8,LSL #3]

        (629) 0x431550 B	4313f0

0x431554 HINT	#0

0x431558 HINT	#0

0x43155c HINT	#0

      (625) 0x431560 LDR	X23, [SP, #344]

      (625) 0x431564 SUB	X28, X29, #168

      (625) 0x431568 CBZ	X25, 431644

    (626) 0x43156c LDR	X8, [SP, #648]

    (626) 0x431570 LDR	X24, [SP, #424]

    (626) 0x431574 SUB	X3, X25, #1

    (626) 0x431578 ORR	X2, XZR, XZR

    (626) 0x43157c ADD	X8, X20, X8,LSL #3

    (626) 0x431580 ORR	X1, XZR, X24

    (626) 0x431584 LDUR	X0, [X8, #504]

    (626) 0x431588 BL	4a7660

    (626) 0x43158c LDR	X8, [SP, #704]

    (626) 0x431590 LDR	X9, [SP, #648]

    (626) 0x431594 ADD	X10, X8, X9,LSL #3

    (626) 0x431598 UBFM	X11, X9, #61, #60

    (626) 0x43159c LDR	X9, [SP, #712]

    (626) 0x4315a0 LDUR	X10, [X10, #504]

    (626) 0x4315a4 LDR	X11, [X9, X11]

    (626) 0x4315a8 STR	X10, [SP, #488]

    (626) 0x4315ac LDR	X12, [X24]

    (626) 0x4315b0 STR	X10, [X11, X12,LSL #3]

    (626) 0x4315b4 MOVZ	W10, #1

    (626) 0x4315b8 STR	X10, [SP, #560]

    (626) 0x4315bc CMP	X25, #2

    (626) 0x4315c0 B.LT	431668

  (628) 0x4315c4 MOVZ	W11, #1

  (628) 0x4315c8 ORR	X10, XZR, XZR

  (628) 0x4315cc B	431620

0x4315d0 HINT	#0

0x4315d4 HINT	#0

0x4315d8 HINT	#0

0x4315dc HINT	#0

(627) 0x4315e0 ADD	X10, X10, #1

(627) 0x4315e4 STR	X14, [X13, X10,LSL #3]

(627) 0x4315e8 LDR	X11, [SP, #488]

(627) 0x4315ec LDR	X12, [SP, #648]

(627) 0x4315f0 ADD	X13, X11, #1

(627) 0x4315f4 LDR	X11, [SP, #560]

(627) 0x4315f8 STR	X13, [SP, #488]

  (628) 0x4315fc LDR	X14, [SP, #424]

  (628) 0x431600 LDR	X12, [X9, X12,LSL #3]

  (628) 0x431604 LDR	X11, [X14, X11,LSL #3]

  (628) 0x431608 STR	X13, [X12, X11,LSL #3]

  (628) 0x43160c LDR	X11, [SP, #560]

  (628) 0x431610 ADD	X11, X11, #1

  (628) 0x431614 STR	X11, [SP, #560]

  (628) 0x431618 CMP	X11, X25

  (628) 0x43161c B.GE	431668

  (628) 0x431620 LDR	X12, [SP, #648]

  (628) 0x431624 ADD	X13, X20, X12,LSL #3

  (628) 0x431628 LDUR	X13, [X13, #504]

  (628) 0x43162c LDR	X14, [X13, X11,LSL #3]

  (628) 0x431630 LDR	X15, [X13, X10,LSL #3]

  (628) 0x431634 CMP	X14, X15

  (628) 0x431638 B.GT	4315e0

  (628) 0x43163c LDR	X13, [SP, #488]

  (628) 0x431640 B	4315fc

      (625) 0x431644 LDR	X8, [SP, #528]

      (625) 0x431648 CMP	X8, #1

      (625) 0x43164c B.LE	431678

      (625) 0x431650 LDR	X8, [SP, #704]

      (625) 0x431654 LDR	X9, [SP, #648]

      (625) 0x431658 ADD	X8, X8, X9,LSL #3

      (625) 0x43165c LDUR	X9, [X8, #504]

      (625) 0x431660 STR	X9, [X8]

      (625) 0x431664 B	431678

    (626) 0x431668 LDR	X9, [SP, #488]

    (626) 0x43166c LDR	X10, [SP, #648]

    (626) 0x431670 ADD	X9, X9, #1

    (626) 0x431674 STR	X9, [X8, X10,LSL #3]

      (625) 0x431678 LDP	X9, X8, [SP, #480]

      (625) 0x43167c SUB	X10, X29, #144

      (625) 0x431680 CMP	X9, X8

      (625) 0x431684 B.GT	430e60

      (625) 0x431688 ADD	X8, X8, #1

      (625) 0x43168c STR	X8, [SP, #480]

      (625) 0x431690 B	430e60

0x431694 ORR	X19, XZR, XZR

0x431698 STR	XZR, [SP, #424]

0x43169c LDR	X0, [SP, #424]

0x4316a0 BL	4a6d90

0x4316a4 LDUR	X0, [X29, #296]

0x4316a8 BL	4a6d90

0x4316ac STUR	XZR, [X29, #296]

0x4316b0 ORR	X0, XZR, X19

0x4316b4 BL	4a6d90

0x4316b8 LDR	X0, [SP, #296]

0x4316bc BL	4a6d90

0x4316c0 LDR	X0, [SP, #448]

0x4316c4 BL	4a6d90

0x4316c8 LDR	X0, [SP, #440]

0x4316cc STR	XZR, [SP, #448]

0x4316d0 BL	4a6d90

0x4316d4 LDR	X0, [SP, #456]

0x4316d8 STR	XZR, [SP, #440]

0x4316dc BL	4a6d90

0x4316e0 LDR	X0, [SP, #656]

0x4316e4 MOVZ	W1, #8

0x4316e8 STR	XZR, [SP, #456]

0x4316ec BL	4a6c90

0x4316f0 STUR	X0, [X29, #360]

0x4316f4 LDR	X0, [SP, #656]

0x4316f8 MOVZ	W1, #8

0x4316fc BL	4a6c90

0x431700 STUR	X0, [X29, #376]

0x431704 LDR	X0, [SP, #512]

0x431708 CBZ	X0, 431728

0x43170c MOVZ	W1, #8

0x431710 BL	4a6c90

0x431714 STUR	X0, [X29, #336]

0x431718 LDR	X0, [SP, #512]

0x43171c MOVZ	W1, #8

0x431720 BL	4a6c90

0x431724 STUR	X0, [X29, #352]

0x431728 LDR	X25, [X29, #96]

0x43172c LDR	X8, [SP, #632]

0x431730 STR	XZR, [SP, #560]

0x431734 CMP	X8, #1

0x431738 B.LT	431784

0x43173c LDUR	X8, [X29, #368]

0x431740 LDUR	X9, [X29, #344]

0x431744 ORR	X10, XZR, XZR

(624) 0x431748 ADD	X10, X8, X10,LSL #3

(624) 0x43174c LDP	X11, X12, [X10]

(624) 0x431750 ADD	X11, X12, X11

(624) 0x431754 STR	X11, [X10, #8]

(624) 0x431758 LDR	X10, [SP, #560]

(624) 0x43175c ADD	X10, X9, X10,LSL #3

(624) 0x431760 LDP	X11, X12, [X10]

(624) 0x431764 ADD	X11, X12, X11

(624) 0x431768 STR	X11, [X10, #8]

(624) 0x43176c LDR	X10, [SP, #560]

(624) 0x431770 LDR	X11, [SP, #632]

(624) 0x431774 ADD	X10, X10, #1

(624) 0x431778 STR	X10, [SP, #560]

(624) 0x43177c CMP	X10, X11

(624) 0x431780 B.LT	431748

0x431784 SUB	X21, X29, #136

0x431788 ADRP	X0,

0x43178c ADD	X0, X0, #712

0x431790 ADRP	X2, 433790

0x431794 ADD	X2, X2, #2640

0x431798 ADD	X3, SP, #624

0x43179c STR	X21, [SP]

0x4317a0 SUB	X4, X29, #248

0x4317a4 SUB	X5, X29, #152

0x4317a8 SUB	X6, X29, #144

0x4317ac ADD	X7, SP, #592

0x4317b0 MOVZ	W1, #6

0x4317b4 SUB	X20, X29, #248

0x4317b8 SUB	X22, X29, #152

0x4317bc SUB	X19, X29, #144

0x4317c0 ADD	X24, SP, #592

0x4317c4 BL	40f600

0x4317c8 LDR	X8, [SP, #752]

0x4317cc SUB	X10, X29, #160

0x4317d0 LDP	X8, X9, [X8, #8]

0x4317d4 SUB	X8, X9, X8

0x4317d8 SUB	X9, X29, #176

0x4317dc STR	X8, [SP, #464]

0x4317e0 ADD	X8, SP, #688

0x4317e4 CBZ	X25, 431e74

0x4317e8 STP	X9, X8, [SP, #200]

0x4317ec SUB	X8, X29, #72

0x4317f0 SUB	X11, X29, #232

0x4317f4 SUB	X9, X29, #88

0x4317f8 ADRP	X0,

0x4317fc ADD	X0, X0, #736

0x431800 ADRP	X2, 433800

0x431804 ADD	X2, X2, #3024

0x431808 STP	X21, X22, [SP, #80]

0x43180c STP	X8, X10, [SP, #184]

0x431810 SUB	X8, X29, #224

0x431814 STR	X9, [SP, #160]

0x431818 ADD	X9, X29, #104

0x43181c ADD	X10, SP, #728

0x431820 ADD	X3, SP, #632

0x431824 SUB	X4, X29, #128

0x431828 ADD	X5, SP, #752

0x43182c STP	X8, X11, [SP, #168]

0x431830 ADD	X8, SP, #680

0x431834 ADD	X6, SP, #464

0x431838 ADD	X7, SP, #760

0x43183c MOVZ	W1, #32

0x431840 STP	X10, X20, [SP, #16]

0x431844 STP	X9, X8, [SP, #144]

0x431848 SUB	X8, X29, #80

0x43184c SUB	X9, X29, #256

0x431850 STP	X9, X8, [SP, #128]

0x431854 ADD	X8, SP, #720

0x431858 SUB	X9, X29, #168

0x43185c STP	X9, X8, [SP, #112]

0x431860 ADD	X8, SP, #736

0x431864 SUB	X9, X29, #40

0x431868 STP	X24, X8, [SP, #96]

0x43186c SUB	X8, X29, #48

0x431870 STP	X9, X8, [SP, #64]

0x431874 SUB	X8, X29, #32

0x431878 SUB	X9, X29, #8

0x43187c STP	X9, X8, [SP, #48]

0x431880 SUB	X8, X29, #64

0x431884 SUB	X9, X29, #56

0x431888 STP	X9, X8, [SP, #32]

0x43188c ADD	X8, SP, #744

0x431890 STP	X8, X19, [SP]

0x431894 BL	40f600

0x431898 LDR	X8, [SP, #624]

0x43189c CBZ	X8, 4318ac

0x4318a0 LDUR	X0, [X29, #264]

0x4318a4 BL	4a6d90

0x4318a8 STUR	XZR, [X29, #264]

0x4318ac LDUR	X0, [X29, #256]

0x4318b0 BL	4a6d90

0x4318b4 LDR	X8, [SP, #728]

0x4318b8 STUR	XZR, [X29, #256]

0x4318bc LDR	X0, [X8, #8]

0x4318c0 BL	4a6d90

0x4318c4 LDR	X8, [SP, #728]

0x4318c8 LDR	X19, [SP, #392]

0x4318cc STR	XZR, [X8, #8]

0x4318d0 LDR	X8, [SP, #528]

0x4318d4 CMP	X8, #2

0x4318d8 B.LT	4318f0

0x4318dc LDR	X8, [SP, #720]

0x4318e0 LDR	X0, [X8, #8]

0x4318e4 BL	4a6d90

0x4318e8 LDR	X8, [SP, #720]

0x4318ec STR	XZR, [X8, #8]

0x4318f0 MOVZ	W8, #2

0x4318f4 STR	X8, [SP, #648]

0x4318f8 LDR	X8, [SP, #640]

0x4318fc CMP	X8, #2

0x431900 B.LE	4324f4

0x431904 MOVZ	W8, #2

0x431908 SUB	X21, X29, #232

0x43190c ADRP	X20, 43490c

0x431910 ADD	X20, X20, #896

0x431914 ORR	X26, XZR, XZR

0x431918 ORR	X27, XZR, XZR

0x43191c ORR	X24, XZR, XZR

0x431920 B	431938

      (614) 0x431924 LDR	X9, [SP, #640]

      (614) 0x431928 ADD	X8, X8, #1

      (614) 0x43192c STR	X8, [SP, #648]

      (614) 0x431930 CMP	X8, X9

      (614) 0x431934 B.GE	4324f8

      (614) 0x431938 LDR	X9, [SP, #528]

      (614) 0x43193c CMP	X9, #2

      (614) 0x431940 B.LT	431cbc

    (615) 0x431944 LDR	X10, [X19, X8,LSL #3]

    (615) 0x431948 LDUR	X9, [X29, #328]

    (615) 0x43194c LDR	X10, [X10, X9,LSL #3]

    (615) 0x431950 STR	X10, [SP, #504]

    (615) 0x431954 CMP	X10, X27

    (615) 0x431958 B.LE	431984

    (615) 0x43195c ORR	X0, XZR, X24

    (615) 0x431960 BL	4a6d90

    (615) 0x431964 LDR	X0, [SP, #504]

    (615) 0x431968 MOVZ	W1, #8

    (615) 0x43196c BL	4a6c90

    (615) 0x431970 LDR	X27, [SP, #504]

    (615) 0x431974 LDUR	X9, [X29, #328]

    (615) 0x431978 LDR	X8, [SP, #648]

    (615) 0x43197c ORR	X24, XZR, X0

    (615) 0x431980 B	431988

    (615) 0x431984 ORR	X27, XZR, X10

    (615) 0x431988 STR	XZR, [SP, #560]

    (615) 0x43198c CMP	X9, #1

    (615) 0x431990 B.LT	431c20

  (616) 0x431994 LDP	X12, X11, [X29, #824]

  (616) 0x431998 LDR	X13, [SP, #584]

  (616) 0x43199c ORR	X5, XZR, XZR

  (616) 0x4319a0 ORR	X10, XZR, XZR

  (616) 0x4319a4 SUB	X14, X8, #1

  (616) 0x4319a8 ADD	X15, X24, #16

  (616) 0x4319ac B	4319cc

0x4319b0 HINT	#0

0x4319b4 HINT	#0

0x4319b8 HINT	#0

0x4319bc HINT	#0

  (616) 0x4319c0 STR	X10, [SP, #560]

  (616) 0x4319c4 CMP	X10, X9

  (616) 0x4319c8 B.EQ	431c20

  (616) 0x4319cc LDR	X16, [X11, X10,LSL #3]

  (616) 0x4319d0 ADD	X10, X10, #1

  (616) 0x4319d4 LDR	X17, [X11, X10,LSL #3]

  (616) 0x4319d8 CMP	X16, X17

  (616) 0x4319dc B.GE	4319c0

(617) 0x4319e0 LDP	X18, X0, [X29, #880]

(617) 0x4319e4 LDP	X1, X2, [X29, #856]

(617) 0x4319e8 ADD	X3, X0, #16

(617) 0x4319ec ADD	X4, X2, #16

(617) 0x4319f0 B	431a0c

0x4319f4 HINT	#0

0x4319f8 HINT	#0

0x4319fc HINT	#0

(617) 0x431a00 ADD	X16, X16, #1

(617) 0x431a04 CMP	X16, X17

(617) 0x431a08 B.EQ	4319c0

(617) 0x431a0c LDR	X6, [X12, X16,LSL #3]

(617) 0x431a10 LDR	X7, [X13, X6,LSL #3]

(617) 0x431a14 CMP	X7, X14

(617) 0x431a18 B.NE	431a00

(617) 0x431a1c ADD	X7, X6, #1

(617) 0x431a20 LDR	X28, [X18, X6,LSL #3]

(617) 0x431a24 LDR	X21, [X18, X7,LSL #3]

(617) 0x431a28 SUBS	X30, X21, X28

(617) 0x431a2c B.LE	431b1c

(617) 0x431a30 CMP	X30, #4

(617) 0x431a34 B.CC	431a8c

(617) 0x431a38 ADD	X19, X24, X5,LSL #3

(617) 0x431a3c ADD	X22, X0, X28,LSL #3

(617) 0x431a40 SUB	X19, X19, X22

(617) 0x431a44 CMP	X19, #32

(617) 0x431a48 B.CC	431a8c

(617) 0x431a4c UBFM	X23, X5, #61, #60

(617) 0x431a50 UBFM	X22, X28, #61, #60

(617) 0x431a54 AND	X19, X30, #8062

(617) 0x431a58 ADD	X5, X5, X19

(617) 0x431a5c ADD	X28, X28, X19

(617) 0x431a60 ADD	X22, X3, X22

(617) 0x431a64 ADD	X25, X15, X23

(617) 0x431a68 ORR	X23, XZR, X19

  (623) 0x431a6c LDP	Q0, Q1, [X22, #2032]

  (623) 0x431a70 ADD	X22, X22, #32

  (623) 0x431a74 SUBS	X23, X23, #4

  (623) 0x431a78 STP	Q0, Q1, [X25, #2032]

  (623) 0x431a7c ADD	X25, X25, #32

  (623) 0x431a80 B.NE	431a6c

(617) 0x431a84 CMP	X30, X19

(617) 0x431a88 B.EQ	431b1c

(617) 0x431a8c SUB	W19, W21, W28

(617) 0x431a90 ANDS	X22, X19, #4160

(617) 0x431a94 B.EQ	431ac0

(617) 0x431a98 ORR	X30, XZR, X28

(617) 0x431a9c HINT	#0

  (622) 0x431aa0 LDR	D0, [X0, X30,LSL #3]

  (622) 0x431aa4 ADD	X23, X5, #1

  (622) 0x431aa8 ADD	X30, X30, #1

  (622) 0x431aac SUBS	X22, X22, #1

  (622) 0x431ab0 STR	D0, [X24, X5,LSL #3]

  (622) 0x431ab4 ORR	X5, XZR, X23

  (622) 0x431ab8 B.NE	431aa0

(617) 0x431abc B	431ac8

(617) 0x431ac0 ORR	X23, XZR, X5

(617) 0x431ac4 ORR	X30, XZR, X28

(617) 0x431ac8 SUB	X19, X28, X21

(617) 0x431acc ORR	X5, XZR, X23

(617) 0x431ad0 CMN	X19, #4

(617) 0x431ad4 B.HI	431b1c

(617) 0x431ad8 SUB	X21, X21, X30

(617) 0x431adc ADD	X28, X3, X30,LSL #3

(617) 0x431ae0 ADD	X30, X15, X23,LSL #3

(617) 0x431ae4 ORR	X5, XZR, X23

  (621) 0x431ae8 LDUR	D0, [X28, #496]

  (621) 0x431aec ADD	X5, X5, #4

  (621) 0x431af0 SUBS	X21, X21, #4

  (621) 0x431af4 STUR	D0, [X30, #496]

  (621) 0x431af8 LDUR	D0, [X28, #504]

  (621) 0x431afc STUR	D0, [X30, #504]

  (621) 0x431b00 LDR	D0, [X28]

  (621) 0x431b04 STR	D0, [X30]

  (621) 0x431b08 LDR	D0, [X28, #8]

  (621) 0x431b0c ADD	X28, X28, #32

  (621) 0x431b10 STR	D0, [X30, #8]

  (621) 0x431b14 ADD	X30, X30, #32

  (621) 0x431b18 B.NE	431ae8

(617) 0x431b1c LDR	X21, [X1, X6,LSL #3]

(617) 0x431b20 LDR	X6, [X1, X7,LSL #3]

(617) 0x431b24 SUBS	X7, X6, X21

(617) 0x431b28 B.LE	431a00

(617) 0x431b2c CMP	X7, #4

(617) 0x431b30 B.CC	431b88

(617) 0x431b34 ADD	X19, X24, X5,LSL #3

(617) 0x431b38 ADD	X22, X2, X21,LSL #3

(617) 0x431b3c SUB	X19, X19, X22

(617) 0x431b40 CMP	X19, #32

(617) 0x431b44 B.CC	431b88

(617) 0x431b48 UBFM	X19, X5, #61, #60

(617) 0x431b4c UBFM	X22, X21, #61, #60

(617) 0x431b50 AND	X23, X7, #8062

(617) 0x431b54 ADD	X5, X5, X23

(617) 0x431b58 ADD	X21, X21, X23

(617) 0x431b5c ADD	X22, X4, X22

(617) 0x431b60 ADD	X25, X15, X19

(617) 0x431b64 ORR	X19, XZR, X23

  (620) 0x431b68 LDP	Q0, Q1, [X22, #2032]

  (620) 0x431b6c ADD	X22, X22, #32

  (620) 0x431b70 SUBS	X19, X19, #4

  (620) 0x431b74 STP	Q0, Q1, [X25, #2032]

  (620) 0x431b78 ADD	X25, X25, #32

  (620) 0x431b7c B.NE	431b68

(617) 0x431b80 CMP	X7, X23

(617) 0x431b84 B.EQ	431a00

(617) 0x431b88 SUB	W7, W6, W21

(617) 0x431b8c ANDS	X22, X7, #4160

(617) 0x431b90 B.EQ	431bc0

(617) 0x431b94 ORR	X23, XZR, X21

(617) 0x431b98 HINT	#0

(617) 0x431b9c HINT	#0

  (619) 0x431ba0 LDR	D0, [X2, X23,LSL #3]

  (619) 0x431ba4 ADD	X7, X5, #1

  (619) 0x431ba8 ADD	X23, X23, #1

  (619) 0x431bac SUBS	X22, X22, #1

  (619) 0x431bb0 STR	D0, [X24, X5,LSL #3]

  (619) 0x431bb4 ORR	X5, XZR, X7

  (619) 0x431bb8 B.NE	431ba0

(617) 0x431bbc B	431bc8

(617) 0x431bc0 ORR	X7, XZR, X5

(617) 0x431bc4 ORR	X23, XZR, X21

(617) 0x431bc8 SUB	X19, X21, X6

(617) 0x431bcc ORR	X5, XZR, X7

(617) 0x431bd0 CMN	X19, #4

(617) 0x431bd4 B.HI	431a00

(617) 0x431bd8 SUB	X6, X6, X23

(617) 0x431bdc ADD	X21, X4, X23,LSL #3

(617) 0x431be0 ADD	X23, X15, X7,LSL #3

(617) 0x431be4 ORR	X5, XZR, X7

  (618) 0x431be8 LDUR	D0, [X21, #496]

  (618) 0x431bec ADD	X5, X5, #4

  (618) 0x431bf0 SUBS	X6, X6, #4

  (618) 0x431bf4 STUR	D0, [X23, #496]

  (618) 0x431bf8 LDUR	D0, [X21, #504]

  (618) 0x431bfc STUR	D0, [X23, #504]

  (618) 0x431c00 LDR	D0, [X21]

  (618) 0x431c04 STR	D0, [X23]

  (618) 0x431c08 LDR	D0, [X21, #8]

  (618) 0x431c0c ADD	X21, X21, #32

  (618) 0x431c10 STR	D0, [X23, #8]

  (618) 0x431c14 ADD	X23, X23, #32

  (618) 0x431c18 B.NE	431be8

(617) 0x431c1c B	431a00

    (615) 0x431c20 LDR	X10, [SP, #384]

    (615) 0x431c24 LDR	X3, [SP, #568]

    (615) 0x431c28 STR	X9, [X10, #8]

    (615) 0x431c2c LDP	X9, X11, [SP, #392]

    (615) 0x431c30 LDR	X9, [X9, X8,LSL #3]

    (615) 0x431c34 STR	X9, [X10, #24]

    (615) 0x431c38 LDR	X9, [SP, #408]

    (615) 0x431c3c LDR	X8, [X11, X8,LSL #3]

    (615) 0x431c40 STR	X9, [X10, #40]

    (615) 0x431c44 LDR	X21, [X8, X9,LSL #3]

    (615) 0x431c48 STR	X8, [X10, #56]

    (615) 0x431c4c CMP	X21, X26

    (615) 0x431c50 B.LE	431c74

    (615) 0x431c54 ORR	X0, XZR, X3

    (615) 0x431c58 BL	4a6d90

    (615) 0x431c5c MOVZ	W1, #8

    (615) 0x431c60 STR	XZR, [SP, #568]

    (615) 0x431c64 ORR	X0, XZR, X21

    (615) 0x431c68 BL	4a6c90

    (615) 0x431c6c ORR	X3, XZR, X0

    (615) 0x431c70 STR	X0, [SP, #568]

    (615) 0x431c74 LDR	X1, [SP, #384]

    (615) 0x431c78 MOVZ	W0, #1

    (615) 0x431c7c ORR	X2, XZR, X24

    (615) 0x431c80 BL	480c50

    (615) 0x431c84 BL	481040

    (615) 0x431c88 LDR	X8, [SP, #648]

    (615) 0x431c8c LDR	X19, [SP, #392]

    (615) 0x431c90 LDR	X0, [X19, X8,LSL #3]

    (615) 0x431c94 BL	4a6d90

    (615) 0x431c98 LDR	X8, [SP, #648]

    (615) 0x431c9c LDR	X22, [SP, #400]

    (615) 0x431ca0 STR	XZR, [X19, X8,LSL #3]

    (615) 0x431ca4 LDR	X0, [X22, X8,LSL #3]

    (615) 0x431ca8 BL	4a6d90

    (615) 0x431cac LDR	X8, [SP, #648]

    (615) 0x431cb0 ORR	X26, XZR, X21

    (615) 0x431cb4 SUB	X21, X29, #232

    (615) 0x431cb8 STR	XZR, [X22, X8,LSL #3]

      (614) 0x431cbc LDR	X9, [SP, #752]

      (614) 0x431cc0 ADD	X3, SP, #632

      (614) 0x431cc4 SUB	X4, X29, #128

      (614) 0x431cc8 ADD	X5, SP, #624

      (614) 0x431ccc ADD	X6, SP, #480

      (614) 0x431cd0 ADD	X7, SP, #616

      (614) 0x431cd4 ADRP	X0,

      (614) 0x431cd8 ADD	X0, X0, #760

      (614) 0x431cdc ORR	X2, XZR, X20

      (614) 0x431ce0 MOVZ	W1, #42

      (614) 0x431ce4 ADD	X8, X9, X8,LSL #3

      (614) 0x431ce8 LDP	X8, X9, [X8]

      (614) 0x431cec SUB	X8, X9, X8

      (614) 0x431cf0 STR	X8, [SP, #464]

      (614) 0x431cf4 SUB	X8, X29, #224

      (614) 0x431cf8 STP	X8, X21, [SP, #280]

      (614) 0x431cfc ADD	X8, SP, #568

      (614) 0x431d00 STR	X8, [SP, #272]

      (614) 0x431d04 SUB	X8, X29, #72

      (614) 0x431d08 STR	X8, [SP, #264]

      (614) 0x431d0c ADD	X8, SP, #712

      (614) 0x431d10 STR	X8, [SP, #256]

      (614) 0x431d14 ADD	X8, SP, #696

      (614) 0x431d18 STR	X8, [SP, #248]

      (614) 0x431d1c SUB	X8, X29, #208

      (614) 0x431d20 STR	X8, [SP, #240]

      (614) 0x431d24 SUB	X8, X29, #88

      (614) 0x431d28 STR	X8, [SP, #232]

      (614) 0x431d2c ADD	X8, SP, #680

      (614) 0x431d30 STR	X8, [SP, #224]

      (614) 0x431d34 ADD	X8, X29, #104

      (614) 0x431d38 STR	X8, [SP, #216]

      (614) 0x431d3c SUB	X8, X29, #80

      (614) 0x431d40 STR	X8, [SP, #208]

      (614) 0x431d44 SUB	X8, X29, #40

      (614) 0x431d48 STR	X8, [SP, #200]

      (614) 0x431d4c SUB	X8, X29, #32

      (614) 0x431d50 STR	X8, [SP, #192]

      (614) 0x431d54 SUB	X8, X29, #8

      (614) 0x431d58 STR	X8, [SP, #184]

      (614) 0x431d5c SUB	X8, X29, #48

      (614) 0x431d60 STR	X8, [SP, #176]

      (614) 0x431d64 SUB	X8, X29, #64

      (614) 0x431d68 STR	X8, [SP, #168]

      (614) 0x431d6c SUB	X8, X29, #56

      (614) 0x431d70 STR	X8, [SP, #160]

      (614) 0x431d74 ADD	X8, SP, #576

      (614) 0x431d78 STR	X8, [SP, #152]

      (614) 0x431d7c SUB	X8, X29, #120

      (614) 0x431d80 STR	X8, [SP, #144]

      (614) 0x431d84 SUB	X8, X29, #112

      (614) 0x431d88 STR	X8, [SP, #136]

      (614) 0x431d8c ADD	X8, SP, #584

      (614) 0x431d90 STR	X8, [SP, #128]

      (614) 0x431d94 SUB	X8, X29, #104

      (614) 0x431d98 STR	X8, [SP, #120]

      (614) 0x431d9c SUB	X8, X29, #96

      (614) 0x431da0 STR	X8, [SP, #112]

      (614) 0x431da4 SUB	X8, X29, #176

      (614) 0x431da8 STR	X8, [SP, #104]

      (614) 0x431dac SUB	X8, X29, #160

      (614) 0x431db0 STR	X8, [SP, #96]

      (614) 0x431db4 ADD	X8, SP, #720

      (614) 0x431db8 STR	X8, [SP, #88]

      (614) 0x431dbc SUB	X8, X29, #168

      (614) 0x431dc0 STR	X8, [SP, #80]

      (614) 0x431dc4 ADD	X8, SP, #736

      (614) 0x431dc8 STR	X8, [SP, #72]

      (614) 0x431dcc SUB	X8, X29, #152

      (614) 0x431dd0 STR	X8, [SP, #64]

      (614) 0x431dd4 SUB	X8, X29, #136

      (614) 0x431dd8 STR	X8, [SP, #56]

      (614) 0x431ddc ADD	X8, SP, #728

      (614) 0x431de0 STR	X8, [SP, #48]

      (614) 0x431de4 SUB	X8, X29, #144

      (614) 0x431de8 STR	X8, [SP, #40]

      (614) 0x431dec ADD	X8, SP, #744

      (614) 0x431df0 STR	X8, [SP, #32]

      (614) 0x431df4 ADD	X8, SP, #760

      (614) 0x431df8 STR	X8, [SP, #24]

      (614) 0x431dfc ADD	X8, SP, #464

      (614) 0x431e00 STR	X8, [SP, #16]

      (614) 0x431e04 ADD	X8, SP, #648

      (614) 0x431e08 STR	X8, [SP, #8]

      (614) 0x431e0c ADD	X8, SP, #752

      (614) 0x431e10 STR	X8, [SP]

      (614) 0x431e14 BL	40f600

      (614) 0x431e18 LDR	X8, [SP, #728]

      (614) 0x431e1c LDR	X9, [SP, #648]

      (614) 0x431e20 LDR	X0, [X8, X9,LSL #3]

      (614) 0x431e24 BL	4a6d90

      (614) 0x431e28 LDR	X9, [SP, #728]

      (614) 0x431e2c LDR	X8, [SP, #648]

      (614) 0x431e30 STR	XZR, [X9, X8,LSL #3]

      (614) 0x431e34 LDR	X9, [SP, #528]

      (614) 0x431e38 CMP	X9, #2

      (614) 0x431e3c B.LT	431924

      (614) 0x431e40 LDR	X9, [SP, #720]

      (614) 0x431e44 LDR	X0, [X9, X8,LSL #3]

      (614) 0x431e48 BL	4a6d90

      (614) 0x431e4c LDR	X8, [SP, #720]

      (614) 0x431e50 LDR	X9, [SP, #648]

      (614) 0x431e54 STR	XZR, [X8, X9,LSL #3]

      (614) 0x431e58 LDR	X8, [SP, #712]

      (614) 0x431e5c LDR	X0, [X8, X9,LSL #3]

      (614) 0x431e60 BL	4a6d90

      (614) 0x431e64 LDR	X9, [SP, #712]

      (614) 0x431e68 LDR	X8, [SP, #648]

      (614) 0x431e6c STR	XZR, [X9, X8,LSL #3]

      (614) 0x431e70 B	431924

0x431e74 STP	X9, X8, [SP, #200]

0x431e78 SUB	X8, X29, #72

0x431e7c SUB	X11, X29, #232

0x431e80 SUB	X9, X29, #88

0x431e84 ADRP	X0,

0x431e88 ADD	X0, X0, #784

0x431e8c ADRP	X2, 434e8c

0x431e90 ADD	X2, X2, #3568

0x431e94 STP	X21, X22, [SP, #80]

0x431e98 STP	X8, X10, [SP, #184]

0x431e9c SUB	X8, X29, #224

0x431ea0 STR	X9, [SP, #160]

0x431ea4 ADD	X9, X29, #104

0x431ea8 ADD	X10, SP, #728

0x431eac ADD	X3, SP, #632

0x431eb0 SUB	X4, X29, #128

0x431eb4 ADD	X5, SP, #752

0x431eb8 STP	X8, X11, [SP, #168]

0x431ebc ADD	X8, SP, #680

0x431ec0 ADD	X6, SP, #464

0x431ec4 ADD	X7, SP, #760

0x431ec8 MOVZ	W1, #32

0x431ecc STP	X10, X20, [SP, #16]

0x431ed0 STP	X9, X8, [SP, #144]

0x431ed4 SUB	X8, X29, #80

0x431ed8 SUB	X9, X29, #256

0x431edc STP	X9, X8, [SP, #128]

0x431ee0 ADD	X8, SP, #720

0x431ee4 SUB	X9, X29, #168

0x431ee8 STP	X9, X8, [SP, #112]

0x431eec ADD	X8, SP, #736

0x431ef0 SUB	X9, X29, #40

0x431ef4 STP	X24, X8, [SP, #96]

0x431ef8 SUB	X8, X29, #48

0x431efc STP	X9, X8, [SP, #64]

0x431f00 SUB	X8, X29, #32

0x431f04 SUB	X9, X29, #8

0x431f08 STP	X9, X8, [SP, #48]

0x431f0c SUB	X8, X29, #64

0x431f10 SUB	X9, X29, #56

0x431f14 STP	X9, X8, [SP, #32]

0x431f18 ADD	X8, SP, #744

0x431f1c STP	X8, X19, [SP]

0x431f20 BL	40f600

0x431f24 LDR	X8, [SP, #624]

0x431f28 CBZ	X8, 431f38

0x431f2c LDUR	X0, [X29, #264]

0x431f30 BL	4a6d90

0x431f34 STUR	XZR, [X29, #264]

0x431f38 LDUR	X0, [X29, #256]

0x431f3c BL	4a6d90

0x431f40 LDR	X8, [SP, #728]

0x431f44 STUR	XZR, [X29, #256]

0x431f48 LDR	X0, [X8, #8]

0x431f4c BL	4a6d90

0x431f50 LDR	X8, [SP, #728]

0x431f54 LDR	X19, [SP, #392]

0x431f58 STR	XZR, [X8, #8]

0x431f5c LDR	X8, [SP, #528]

0x431f60 CMP	X8, #2

0x431f64 B.LT	431f7c

0x431f68 LDR	X8, [SP, #720]

0x431f6c LDR	X0, [X8, #8]

0x431f70 BL	4a6d90

0x431f74 LDR	X8, [SP, #720]

0x431f78 STR	XZR, [X8, #8]

0x431f7c MOVZ	W8, #2

0x431f80 STR	X8, [SP, #648]

0x431f84 LDR	X8, [SP, #640]

0x431f88 CMP	X8, #2

0x431f8c B.LE	4324f4

0x431f90 MOVZ	W8, #2

0x431f94 SUB	X21, X29, #232

0x431f98 ADRP	X20, 435f98

0x431f9c ADD	X20, X20, #1264

0x431fa0 ORR	X26, XZR, XZR

0x431fa4 ORR	X27, XZR, XZR

0x431fa8 ORR	X24, XZR, XZR

0x431fac B	431fd4

0x431fb0 HINT	#0

0x431fb4 HINT	#0

0x431fb8 HINT	#0

0x431fbc HINT	#0

(605) 0x431fc0 LDR	X9, [SP, #640]

(605) 0x431fc4 ADD	X8, X8, #1

(605) 0x431fc8 STR	X8, [SP, #648]

(605) 0x431fcc CMP	X8, X9

(605) 0x431fd0 B.GE	4324f8

(605) 0x431fd4 LDR	X9, [SP, #528]

(605) 0x431fd8 CMP	X9, #2

(605) 0x431fdc B.LT	43233c

(605) 0x431fe0 LDR	X10, [X19, X8,LSL #3]

(605) 0x431fe4 LDUR	X9, [X29, #328]

(605) 0x431fe8 LDR	X10, [X10, X9,LSL #3]

(605) 0x431fec STR	X10, [SP, #504]

(605) 0x431ff0 CMP	X10, X27

(605) 0x431ff4 B.LE	432020

(605) 0x431ff8 ORR	X0, XZR, X24

(605) 0x431ffc BL	4a6d90

(605) 0x432000 LDR	X0, [SP, #504]

(605) 0x432004 MOVZ	W1, #8

(605) 0x432008 BL	4a6c90

(605) 0x43200c LDR	X27, [SP, #504]

(605) 0x432010 LDUR	X9, [X29, #328]

(605) 0x432014 LDR	X8, [SP, #648]

(605) 0x432018 ORR	X24, XZR, X0

(605) 0x43201c B	432024

(605) 0x432020 ORR	X27, XZR, X10

(605) 0x432024 STR	XZR, [SP, #560]

(605) 0x432028 CMP	X9, #1

(605) 0x43202c B.LT	4322a0

(605) 0x432030 LDP	X12, X11, [X29, #824]

(605) 0x432034 LDR	X13, [SP, #584]

(605) 0x432038 ORR	X5, XZR, XZR

(605) 0x43203c ORR	X10, XZR, XZR

(605) 0x432040 SUB	X14, X8, #1

(605) 0x432044 ADD	X15, X24, #16

(605) 0x432048 B	432058

  (606) 0x43204c STR	X10, [SP, #560]

  (606) 0x432050 CMP	X10, X9

  (606) 0x432054 B.EQ	4322a0

  (606) 0x432058 LDR	X16, [X11, X10,LSL #3]

  (606) 0x43205c ADD	X10, X10, #1

  (606) 0x432060 LDR	X17, [X11, X10,LSL #3]

  (606) 0x432064 CMP	X16, X17

  (606) 0x432068 B.GE	43204c

  (606) 0x43206c LDP	X18, X0, [X29, #880]

  (606) 0x432070 LDP	X1, X2, [X29, #856]

  (606) 0x432074 ADD	X3, X0, #16

  (606) 0x432078 ADD	X4, X2, #16

  (606) 0x43207c B	43208c

    (607) 0x432080 ADD	X16, X16, #1

    (607) 0x432084 CMP	X16, X17

    (607) 0x432088 B.EQ	43204c

    (607) 0x43208c LDR	X6, [X12, X16,LSL #3]

    (607) 0x432090 LDR	X7, [X13, X6,LSL #3]

    (607) 0x432094 CMP	X7, X14

    (607) 0x432098 B.NE	432080

    (607) 0x43209c ADD	X7, X6, #1

    (607) 0x4320a0 LDR	X28, [X18, X6,LSL #3]

    (607) 0x4320a4 LDR	X21, [X18, X7,LSL #3]

    (607) 0x4320a8 SUBS	X30, X21, X28

    (607) 0x4320ac B.LE	43219c

    (607) 0x4320b0 CMP	X30, #4

    (607) 0x4320b4 B.CC	43210c

    (607) 0x4320b8 ADD	X19, X24, X5,LSL #3

    (607) 0x4320bc ADD	X22, X0, X28,LSL #3

    (607) 0x4320c0 SUB	X19, X19, X22

    (607) 0x4320c4 CMP	X19, #32

    (607) 0x4320c8 B.CC	43210c

    (607) 0x4320cc UBFM	X23, X5, #61, #60

    (607) 0x4320d0 UBFM	X22, X28, #61, #60

    (607) 0x4320d4 AND	X19, X30, #8062

    (607) 0x4320d8 ADD	X5, X5, X19

    (607) 0x4320dc ADD	X28, X28, X19

    (607) 0x4320e0 ADD	X22, X3, X22

    (607) 0x4320e4 ADD	X25, X15, X23

    (607) 0x4320e8 ORR	X23, XZR, X19

      (613) 0x4320ec LDP	Q0, Q1, [X22, #2032]

      (613) 0x4320f0 ADD	X22, X22, #32

      (613) 0x4320f4 SUBS	X23, X23, #4

      (613) 0x4320f8 STP	Q0, Q1, [X25, #2032]

      (613) 0x4320fc ADD	X25, X25, #32

      (613) 0x432100 B.NE	4320ec

    (607) 0x432104 CMP	X30, X19

    (607) 0x432108 B.EQ	43219c

    (607) 0x43210c SUB	W19, W21, W28

    (607) 0x432110 ANDS	X22, X19, #4160

    (607) 0x432114 B.EQ	432140

    (607) 0x432118 ORR	X30, XZR, X28

    (607) 0x43211c HINT	#0

      (612) 0x432120 LDR	D0, [X0, X30,LSL #3]

      (612) 0x432124 ADD	X23, X5, #1

      (612) 0x432128 ADD	X30, X30, #1

      (612) 0x43212c SUBS	X22, X22, #1

      (612) 0x432130 STR	D0, [X24, X5,LSL #3]

      (612) 0x432134 ORR	X5, XZR, X23

      (612) 0x432138 B.NE	432120

    (607) 0x43213c B	432148

    (607) 0x432140 ORR	X23, XZR, X5

    (607) 0x432144 ORR	X30, XZR, X28

    (607) 0x432148 SUB	X19, X28, X21

    (607) 0x43214c ORR	X5, XZR, X23

    (607) 0x432150 CMN	X19, #4

    (607) 0x432154 B.HI	43219c

    (607) 0x432158 SUB	X21, X21, X30

    (607) 0x43215c ADD	X28, X3, X30,LSL #3

    (607) 0x432160 ADD	X30, X15, X23,LSL #3

    (607) 0x432164 ORR	X5, XZR, X23

      (611) 0x432168 LDUR	D0, [X28, #496]

      (611) 0x43216c ADD	X5, X5, #4

      (611) 0x432170 SUBS	X21, X21, #4

      (611) 0x432174 STUR	D0, [X30, #496]

      (611) 0x432178 LDUR	D0, [X28, #504]

      (611) 0x43217c STUR	D0, [X30, #504]

      (611) 0x432180 LDR	D0, [X28]

      (611) 0x432184 STR	D0, [X30]

      (611) 0x432188 LDR	D0, [X28, #8]

      (611) 0x43218c ADD	X28, X28, #32

      (611) 0x432190 STR	D0, [X30, #8]

      (611) 0x432194 ADD	X30, X30, #32

      (611) 0x432198 B.NE	432168

    (607) 0x43219c LDR	X21, [X1, X6,LSL #3]

    (607) 0x4321a0 LDR	X6, [X1, X7,LSL #3]

    (607) 0x4321a4 SUBS	X7, X6, X21

    (607) 0x4321a8 B.LE	432080

    (607) 0x4321ac CMP	X7, #4

    (607) 0x4321b0 B.CC	432208

    (607) 0x4321b4 ADD	X19, X24, X5,LSL #3

    (607) 0x4321b8 ADD	X22, X2, X21,LSL #3

    (607) 0x4321bc SUB	X19, X19, X22

    (607) 0x4321c0 CMP	X19, #32

    (607) 0x4321c4 B.CC	432208

    (607) 0x4321c8 UBFM	X19, X5, #61, #60

    (607) 0x4321cc UBFM	X22, X21, #61, #60

    (607) 0x4321d0 AND	X23, X7, #8062

    (607) 0x4321d4 ADD	X5, X5, X23

    (607) 0x4321d8 ADD	X21, X21, X23

    (607) 0x4321dc ADD	X22, X4, X22

    (607) 0x4321e0 ADD	X25, X15, X19

    (607) 0x4321e4 ORR	X19, XZR, X23

      (610) 0x4321e8 LDP	Q0, Q1, [X22, #2032]

      (610) 0x4321ec ADD	X22, X22, #32

      (610) 0x4321f0 SUBS	X19, X19, #4

      (610) 0x4321f4 STP	Q0, Q1, [X25, #2032]

      (610) 0x4321f8 ADD	X25, X25, #32

      (610) 0x4321fc B.NE	4321e8

    (607) 0x432200 CMP	X7, X23

    (607) 0x432204 B.EQ	432080

    (607) 0x432208 SUB	W7, W6, W21

    (607) 0x43220c ANDS	X22, X7, #4160

    (607) 0x432210 B.EQ	432240

    (607) 0x432214 ORR	X23, XZR, X21

    (607) 0x432218 HINT	#0

    (607) 0x43221c HINT	#0

      (609) 0x432220 LDR	D0, [X2, X23,LSL #3]

      (609) 0x432224 ADD	X7, X5, #1

      (609) 0x432228 ADD	X23, X23, #1

      (609) 0x43222c SUBS	X22, X22, #1

      (609) 0x432230 STR	D0, [X24, X5,LSL #3]

      (609) 0x432234 ORR	X5, XZR, X7

      (609) 0x432238 B.NE	432220

    (607) 0x43223c B	432248

    (607) 0x432240 ORR	X7, XZR, X5

    (607) 0x432244 ORR	X23, XZR, X21

    (607) 0x432248 SUB	X19, X21, X6

    (607) 0x43224c ORR	X5, XZR, X7

    (607) 0x432250 CMN	X19, #4

    (607) 0x432254 B.HI	432080

    (607) 0x432258 SUB	X6, X6, X23

    (607) 0x43225c ADD	X21, X4, X23,LSL #3

    (607) 0x432260 ADD	X23, X15, X7,LSL #3

    (607) 0x432264 ORR	X5, XZR, X7

      (608) 0x432268 LDUR	D0, [X21, #496]

      (608) 0x43226c ADD	X5, X5, #4

      (608) 0x432270 SUBS	X6, X6, #4

      (608) 0x432274 STUR	D0, [X23, #496]

      (608) 0x432278 LDUR	D0, [X21, #504]

      (608) 0x43227c STUR	D0, [X23, #504]

      (608) 0x432280 LDR	D0, [X21]

      (608) 0x432284 STR	D0, [X23]

      (608) 0x432288 LDR	D0, [X21, #8]

      (608) 0x43228c ADD	X21, X21, #32

      (608) 0x432290 STR	D0, [X23, #8]

      (608) 0x432294 ADD	X23, X23, #32

      (608) 0x432298 B.NE	432268

    (607) 0x43229c B	432080

(605) 0x4322a0 LDR	X10, [SP, #384]

(605) 0x4322a4 LDR	X3, [SP, #568]

(605) 0x4322a8 STR	X9, [X10, #8]

(605) 0x4322ac LDP	X9, X11, [SP, #392]

(605) 0x4322b0 LDR	X9, [X9, X8,LSL #3]

(605) 0x4322b4 STR	X9, [X10, #24]

(605) 0x4322b8 LDR	X9, [SP, #408]

(605) 0x4322bc LDR	X8, [X11, X8,LSL #3]

(605) 0x4322c0 STR	X9, [X10, #40]

(605) 0x4322c4 LDR	X21, [X8, X9,LSL #3]

(605) 0x4322c8 STR	X8, [X10, #56]

(605) 0x4322cc CMP	X21, X26

(605) 0x4322d0 B.LE	4322f4

(605) 0x4322d4 ORR	X0, XZR, X3

(605) 0x4322d8 BL	4a6d90

(605) 0x4322dc MOVZ	W1, #8

(605) 0x4322e0 STR	XZR, [SP, #568]

(605) 0x4322e4 ORR	X0, XZR, X21

(605) 0x4322e8 BL	4a6c90

(605) 0x4322ec ORR	X3, XZR, X0

(605) 0x4322f0 STR	X0, [SP, #568]

(605) 0x4322f4 LDR	X1, [SP, #384]

(605) 0x4322f8 MOVZ	W0, #1

(605) 0x4322fc ORR	X2, XZR, X24

(605) 0x432300 BL	480c50

(605) 0x432304 BL	481040

(605) 0x432308 LDR	X8, [SP, #648]

(605) 0x43230c LDR	X19, [SP, #392]

(605) 0x432310 LDR	X0, [X19, X8,LSL #3]

(605) 0x432314 BL	4a6d90

(605) 0x432318 LDR	X8, [SP, #648]

(605) 0x43231c LDR	X22, [SP, #400]

(605) 0x432320 STR	XZR, [X19, X8,LSL #3]

(605) 0x432324 LDR	X0, [X22, X8,LSL #3]

(605) 0x432328 BL	4a6d90

(605) 0x43232c LDR	X8, [SP, #648]

(605) 0x432330 ORR	X26, XZR, X21

(605) 0x432334 SUB	X21, X29, #232

(605) 0x432338 STR	XZR, [X22, X8,LSL #3]

(605) 0x43233c LDR	X9, [SP, #752]

(605) 0x432340 ADD	X3, SP, #632

(605) 0x432344 SUB	X4, X29, #128

(605) 0x432348 ADD	X5, SP, #624

(605) 0x43234c ADD	X6, SP, #480

(605) 0x432350 ADD	X7, SP, #616

(605) 0x432354 ADRP	X0,

(605) 0x432358 ADD	X0, X0, #808

(605) 0x43235c ORR	X2, XZR, X20

(605) 0x432360 MOVZ	W1, #42

(605) 0x432364 ADD	X8, X9, X8,LSL #3

(605) 0x432368 LDP	X8, X9, [X8]

(605) 0x43236c SUB	X8, X9, X8

(605) 0x432370 STR	X8, [SP, #464]

(605) 0x432374 SUB	X8, X29, #224

(605) 0x432378 STP	X8, X21, [SP, #280]

(605) 0x43237c ADD	X8, SP, #568

(605) 0x432380 STR	X8, [SP, #272]

(605) 0x432384 SUB	X8, X29, #72

(605) 0x432388 STR	X8, [SP, #264]

(605) 0x43238c ADD	X8, SP, #712

(605) 0x432390 STR	X8, [SP, #256]

(605) 0x432394 ADD	X8, SP, #696

(605) 0x432398 STR	X8, [SP, #248]

(605) 0x43239c SUB	X8, X29, #208

(605) 0x4323a0 STR	X8, [SP, #240]

(605) 0x4323a4 SUB	X8, X29, #88

(605) 0x4323a8 STR	X8, [SP, #232]

(605) 0x4323ac ADD	X8, SP, #680

(605) 0x4323b0 STR	X8, [SP, #224]

(605) 0x4323b4 ADD	X8, X29, #104

(605) 0x4323b8 STR	X8, [SP, #216]

(605) 0x4323bc SUB	X8, X29, #80

(605) 0x4323c0 STR	X8, [SP, #208]

(605) 0x4323c4 SUB	X8, X29, #40

(605) 0x4323c8 STR	X8, [SP, #200]

(605) 0x4323cc SUB	X8, X29, #32

(605) 0x4323d0 STR	X8, [SP, #192]

(605) 0x4323d4 SUB	X8, X29, #8

(605) 0x4323d8 STR	X8, [SP, #184]

(605) 0x4323dc SUB	X8, X29, #48

(605) 0x4323e0 STR	X8, [SP, #176]

(605) 0x4323e4 SUB	X8, X29, #64

(605) 0x4323e8 STR	X8, [SP, #168]

(605) 0x4323ec SUB	X8, X29, #56

(605) 0x4323f0 STR	X8, [SP, #160]

(605) 0x4323f4 ADD	X8, SP, #576

(605) 0x4323f8 STR	X8, [SP, #152]

(605) 0x4323fc SUB	X8, X29, #120

(605) 0x432400 STR	X8, [SP, #144]

(605) 0x432404 SUB	X8, X29, #112

(605) 0x432408 STR	X8, [SP, #136]

(605) 0x43240c ADD	X8, SP, #584

(605) 0x432410 STR	X8, [SP, #128]

(605) 0x432414 SUB	X8, X29, #104

(605) 0x432418 STR	X8, [SP, #120]

(605) 0x43241c SUB	X8, X29, #96

(605) 0x432420 STR	X8, [SP, #112]

(605) 0x432424 SUB	X8, X29, #176

(605) 0x432428 STR	X8, [SP, #104]

(605) 0x43242c SUB	X8, X29, #160

(605) 0x432430 STR	X8, [SP, #96]

(605) 0x432434 ADD	X8, SP, #720

(605) 0x432438 STR	X8, [SP, #88]

(605) 0x43243c SUB	X8, X29, #168

(605) 0x432440 STR	X8, [SP, #80]

(605) 0x432444 ADD	X8, SP, #736

(605) 0x432448 STR	X8, [SP, #72]

(605) 0x43244c SUB	X8, X29, #152

(605) 0x432450 STR	X8, [SP, #64]

(605) 0x432454 SUB	X8, X29, #136

(605) 0x432458 STR	X8, [SP, #56]

(605) 0x43245c ADD	X8, SP, #728

(605) 0x432460 STR	X8, [SP, #48]

(605) 0x432464 SUB	X8, X29, #144

(605) 0x432468 STR	X8, [SP, #40]

(605) 0x43246c ADD	X8, SP, #744

(605) 0x432470 STR	X8, [SP, #32]

(605) 0x432474 ADD	X8, SP, #760

(605) 0x432478 STR	X8, [SP, #24]

(605) 0x43247c ADD	X8, SP, #464

(605) 0x432480 STR	X8, [SP, #16]

(605) 0x432484 ADD	X8, SP, #648

(605) 0x432488 STR	X8, [SP, #8]

(605) 0x43248c ADD	X8, SP, #752

(605) 0x432490 STR	X8, [SP]

(605) 0x432494 BL	40f600

(605) 0x432498 LDR	X8, [SP, #728]

(605) 0x43249c LDR	X9, [SP, #648]

(605) 0x4324a0 LDR	X0, [X8, X9,LSL #3]

(605) 0x4324a4 BL	4a6d90

(605) 0x4324a8 LDR	X9, [SP, #728]

(605) 0x4324ac LDR	X8, [SP, #648]

(605) 0x4324b0 STR	XZR, [X9, X8,LSL #3]

(605) 0x4324b4 LDR	X9, [SP, #528]

(605) 0x4324b8 CMP	X9, #2

(605) 0x4324bc B.LT	431fc0

(605) 0x4324c0 LDR	X9, [SP, #720]

(605) 0x4324c4 LDR	X0, [X9, X8,LSL #3]

(605) 0x4324c8 BL	4a6d90

(605) 0x4324cc LDR	X8, [SP, #720]

(605) 0x4324d0 LDR	X9, [SP, #648]

(605) 0x4324d4 STR	XZR, [X8, X9,LSL #3]

(605) 0x4324d8 LDR	X8, [SP, #712]

(605) 0x4324dc LDR	X0, [X8, X9,LSL #3]

(605) 0x4324e0 BL	4a6d90

(605) 0x4324e4 LDR	X9, [SP, #712]

(605) 0x4324e8 LDR	X8, [SP, #648]

(605) 0x4324ec STR	XZR, [X9, X8,LSL #3]

(605) 0x4324f0 B	431fc0

0x4324f4 ORR	X24, XZR, XZR

0x4324f8 LDUR	X0, [X29, #288]

0x4324fc BL	4a6d90

0x432500 STUR	XZR, [X29, #288]

0x432504 ORR	X0, XZR, X19

0x432508 BL	4a6d90

0x43250c LDR	X0, [SP, #400]

0x432510 BL	4a6d90

0x432514 LDUR	X0, [X29, #280]

0x432518 BL	4a6d90

0x43251c STUR	XZR, [X29, #280]

0x432520 ORR	X0, XZR, X24

0x432524 BL	4a6d90

0x432528 LDR	X0, [SP, #568]

0x43252c BL	4a6d90

0x432530 LDR	X0, [SP, #728]

0x432534 STR	XZR, [SP, #568]

0x432538 BL	4a6d90

0x43253c LDR	X0, [SP, #720]

0x432540 STR	XZR, [SP, #728]

0x432544 BL	4a6d90

0x432548 LDR	X0, [SP, #712]

0x43254c STR	XZR, [SP, #720]

0x432550 BL	4a6d90

0x432554 LDR	X0, [SP, #744]

0x432558 STR	XZR, [SP, #712]

0x43255c BL	4a6d90

0x432560 LDR	X0, [SP, #736]

0x432564 STR	XZR, [SP, #744]

0x432568 BL	4a6d90

0x43256c LDUR	X0, [X29, #304]

0x432570 STR	XZR, [SP, #736]

0x432574 BL	4a6d90

0x432578 LDR	X0, [SP, #696]

0x43257c STUR	XZR, [X29, #304]

0x432580 BL	4a6d90

0x432584 LDR	X0, [SP, #592]

0x432588 STR	XZR, [SP, #696]

0x43258c BL	4a6d90

0x432590 LDR	X0, [SP, #584]

0x432594 STR	XZR, [SP, #592]

0x432598 BL	4a6d90

0x43259c LDR	X0, [SP, #576]

0x4325a0 STR	XZR, [SP, #584]

0x4325a4 BL	4a6d90

0x4325a8 LDR	X0, [SP, #752]

0x4325ac STR	XZR, [SP, #576]

0x4325b0 BL	4a6d90

0x4325b4 LDR	X0, [SP, #760]

0x4325b8 STR	XZR, [SP, #752]

0x4325bc BL	4a6d90

0x4325c0 LDR	X0, [SP, #688]

0x4325c4 STR	XZR, [SP, #760]

0x4325c8 BL	4a6d90

0x4325cc LDR	X0, [SP, #680]

0x4325d0 STR	XZR, [SP, #688]

0x4325d4 BL	4a6d90

0x4325d8 LDR	X8, [SP, #528]

0x4325dc STR	XZR, [SP, #680]

0x4325e0 CMP	X8, #2

0x4325e4 B.LT	4325f0

0x4325e8 LDR	X0, [SP, #384]

0x4325ec BL	4a6d90

0x4325f0 LDP	X8, X4, [SP, #312]

0x4325f4 LDR	X9, [SP, #632]

0x4325f8 LDR	X2, [SP, #520]

0x4325fc ORR	X5, XZR, XZR

0x432600 LDR	X0, [SP, #376]

0x432604 LDR	X1, [X8, #8]

0x432608 LDR	X3, [X8, #104]

0x43260c LDUR	X8, [X29, #368]

0x432610 LDR	X6, [X8, X9,LSL #3]

0x432614 LDUR	X8, [X29, #344]

0x432618 LDR	X7, [X8, X9,LSL #3]

0x43261c BL	489e20

0x432620 LDP	X8, X9, [X29, #880]

0x432624 LDP	X20, X22, [X0, #56]

0x432628 LDR	X1, [SP, #304]

0x43262c FCMP	D8, #0

0x432630 ORR	X19, XZR, X0

0x432634 LDR	X23, [SP, #432]

0x432638 STR	XZR, [X0, #136]

0x43263c STR	X8, [X20]

0x432640 STR	X9, [X20, #48]

0x432644 LDP	X8, X9, [X29, #864]

0x432648 STR	X8, [X22, #48]

0x43264c LDUR	X8, [X29, #344]

0x432650 STR	X9, [X20, #8]

0x432654 STR	X8, [X22]

0x432658 LDUR	X9, [X29, #336]

0x43265c STR	X9, [X22, #8]

0x432660 B.NE	432668

0x432664 CBZ	X1, 432694

0x432668 FMOV	D0, D8

0x43266c ORR	X0, XZR, X19

0x432670 BL	428050

0x432674 LDR	X8, [X20, #48]

0x432678 STUR	X8, [X29, #376]

0x43267c LDP	X8, X9, [X20]

0x432680 STP	X9, X8, [X29, #872]

0x432684 LDR	X8, [X22, #48]

0x432688 STUR	X8, [X29, #352]

0x43268c LDP	X8, X9, [X22]

0x432690 STP	X9, X8, [X29, #848]

0x432694 LDR	X9, [SP, #632]

0x432698 LDR	X21, [X8, X9,LSL #3]

0x43269c STR	XZR, [SP, #472]

0x4326a0 STR	X21, [SP, #496]

0x4326a4 CBZ	X21, 4328ac

0x4326a8 LDR	X8, [SP, #480]

0x4326ac LDUR	X9, [X29, #384]

0x4326b0 MOVZ	W1, #8

0x4326b4 CMP	X8, X9

0x4326b8 CSEL	X0, X8, X9, #12

0x4326bc BL	4a6c90

0x4326c0 STUR	X0, [X29, #272]

0x4326c4 ADRP	X0,

0x4326c8 ADD	X0, X0, #880

0x4326cc ADRP	X2, 4356cc

0x4326d0 ADD	X2, X2, #3968

0x4326d4 ADD	X3, SP, #480

0x4326d8 SUB	X4, X29, #240

0x4326dc MOVZ	W1, #2

0x4326e0 BL	40f600

0x4326e4 STR	XZR, [SP, #472]

0x4326e8 STR	XZR, [SP, #560]

0x4326ec CMP	X21, #1

0x4326f0 B.LT	43273c

0x4326f4 LDUR	X8, [X29, #336]

0x4326f8 LDUR	X9, [X29, #272]

0x4326fc MOVZ	W11, #1

0x432700 ORR	X20, XZR, XZR

0x432704 ORR	X10, XZR, XZR

0x432708 B	43271c

(604) 0x43270c ADD	X10, X10, #1

(604) 0x432710 STR	X10, [SP, #560]

(604) 0x432714 CMP	X10, X21

(604) 0x432718 B.GE	432740

(604) 0x43271c LDR	X12, [X8, X10,LSL #3]

(604) 0x432720 LDR	X13, [X9, X12,LSL #3]

(604) 0x432724 CBNZ	X13, 43270c

(604) 0x432728 ADD	X20, X20, #1

(604) 0x43272c STR	X20, [SP, #472]

(604) 0x432730 STR	X11, [X9, X12,LSL #3]

(604) 0x432734 LDR	X10, [SP, #560]

(604) 0x432738 B	43270c

0x43273c ORR	X20, XZR, XZR

0x432740 MOVZ	W1, #8

0x432744 ORR	X0, XZR, X20

0x432748 BL	4a6c90

0x43274c LDR	X8, [SP, #704]

0x432750 LDR	X9, [SP, #640]

0x432754 ORR	X21, XZR, X0

0x432758 STR	X0, [SP, #672]

0x43275c MOVZ	W1, #8

0x432760 ADD	X8, X8, X9,LSL #3

0x432764 LDUR	X0, [X8, #504]

0x432768 BL	4a6c90

0x43276c STR	X0, [SP, #664]

0x432770 ADRP	X0,

0x432774 ADD	X0, X0, #952

0x432778 ADRP	X2, 436778

0x43277c ADD	X2, X2, #64

0x432780 ADD	X3, SP, #704

0x432784 ADD	X4, SP, #640

0x432788 ADD	X5, SP, #664

0x43278c MOVZ	W1, #3

0x432790 BL	40f600

0x432794 LDR	X12, [SP, #640]

0x432798 STR	XZR, [SP, #560]

0x43279c CMP	X12, #1

0x4327a0 B.LE	432840

0x4327a4 LDR	X9, [SP, #704]

0x4327a8 LDUR	X10, [X29, #272]

0x4327ac ORR	X8, XZR, XZR

0x4327b0 ORR	X11, XZR, XZR

0x4327b4 B	4327d8

0x4327b8 HINT	#0

0x4327bc HINT	#0

(603) 0x4327c0 LDR	X12, [SP, #640]

  (602) 0x4327c4 SUB	X13, X12, #1

  (602) 0x4327c8 STR	X14, [SP, #560]

  (602) 0x4327cc ORR	X11, XZR, X14

  (602) 0x4327d0 CMP	X14, X13

  (602) 0x4327d4 B.GE	432840

  (602) 0x4327d8 ADD	X14, X11, #1

  (602) 0x4327dc LDR	X13, [X9, X11,LSL #3]

  (602) 0x4327e0 LDR	X15, [X9, X14,LSL #3]

  (602) 0x4327e4 CMP	X13, X15

  (602) 0x4327e8 B.GE	4327c4

(603) 0x4327ec LDR	X12, [SP, #664]

(603) 0x4327f0 B	432814

0x4327f4 HINT	#0

0x4327f8 HINT	#0

0x4327fc HINT	#0

(603) 0x432800 ADD	X14, X11, #1

(603) 0x432804 ADD	X13, X13, #1

(603) 0x432808 LDR	X15, [X9, X14,LSL #3]

(603) 0x43280c CMP	X13, X15

(603) 0x432810 B.GE	4327c0

(603) 0x432814 LDR	X14, [X10, X13,LSL #3]

(603) 0x432818 CBZ	X14, 432800

(603) 0x43281c LDR	X14, [X23, X11,LSL #3]

(603) 0x432820 LDR	X11, [X9, X11,LSL #3]

(603) 0x432824 SUB	X11, X14, X11,LSL #3

(603) 0x432828 LDR	X11, [X11, X13,LSL #3]

(603) 0x43282c STR	X11, [X21, X8,LSL #3]

(603) 0x432830 STR	X11, [X12, X13,LSL #3]

(603) 0x432834 ADD	X8, X8, #1

(603) 0x432838 LDR	X11, [SP, #560]

(603) 0x43283c B	432800

0x432840 SUB	X2, X20, #1

0x432844 ORR	X0, XZR, X21

0x432848 ORR	X1, XZR, XZR

0x43284c BL	4a7470

0x432850 ADRP	X0,

0x432854 ADD	X0, X0, #1024

0x432858 ADRP	X2, 436858

0x43285c ADD	X2, X2, #272

0x432860 ADD	X3, SP, #704

0x432864 ADD	X4, SP, #640

0x432868 ADD	X5, SP, #664

0x43286c ADD	X6, SP, #672

0x432870 ADD	X7, SP, #472

0x432874 MOVZ	W1, #5

0x432878 BL	40f600

0x43287c ADRP	X0,

0x432880 ADD	X0, X0, #1096

0x432884 ADRP	X2, 436884

0x432888 ADD	X2, X2, #528

0x43288c ADD	X3, SP, #496

0x432890 SUB	X4, X29, #176

0x432894 ADD	X5, SP, #664

0x432898 MOVZ	W1, #3

0x43289c BL	40f600

0x4328a0 LDUR	X0, [X29, #272]

0x4328a4 BL	4a6d90

0x4328a8 STUR	XZR, [X29, #272]

0x4328ac LDR	X8, [SP, #528]

0x4328b0 CMP	X8, #2

0x4328b4 B.LT	4328f4

0x4328b8 LDR	X8, [SP, #640]

0x4328bc STR	XZR, [SP, #560]

0x4328c0 CMP	X8, #2

0x4328c4 B.LT	4328f4

0x4328c8 ORR	X8, XZR, XZR

(601) 0x4328cc LDR	X0, [X23, X8,LSL #3]

(601) 0x4328d0 BL	4a6d90

(601) 0x4328d4 LDR	X8, [SP, #560]

(601) 0x4328d8 LDR	X9, [SP, #640]

(601) 0x4328dc STR	XZR, [X23, X8,LSL #3]

(601) 0x4328e0 ADD	X8, X8, #1

(601) 0x4328e4 SUB	X9, X9, #1

(601) 0x4328e8 STR	X8, [SP, #560]

(601) 0x4328ec CMP	X8, X9

(601) 0x4328f0 B.LT	4328cc

0x4328f4 LDR	X0, [SP, #664]

0x4328f8 BL	4a6d90

0x4328fc STR	XZR, [SP, #664]

0x432900 ORR	X0, XZR, X23

0x432904 BL	4a6d90

0x432908 LDR	X0, [SP, #704]

0x43290c BL	4a6d90

0x432910 LDR	X8, [SP, #472]

0x432914 STR	XZR, [SP, #704]

0x432918 CBZ	X8, 432928

0x43291c LDR	X9, [SP, #672]

0x432920 STR	X8, [X22, #24]

0x432924 STR	X9, [X19, #88]

0x432928 LDR	X20, [X29, #112]

0x43292c LDR	X8, [SP, #608]

0x432930 CBZ	X8, 432954

0x432934 ADRP	X0,

0x432938 ADD	X0, X0, #1168

0x43293c ADRP	X2, 43693c

0x432940 ADD	X2, X2, #800

0x432944 ADD	X3, SP, #632

0x432948 SUB	X4, X29, #8

0x43294c MOVZ	W1, #2

0x432950 BL	40f600

0x432954 LDR	X8, [SP, #528]

0x432958 CMP	X8, #2

0x43295c B.LT	432968

0x432960 ORR	X0, XZR, X19

0x432964 BL	481820

0x432968 STR	X19, [X20]

0x43296c ORR	X0, XZR, XZR

0x432970 ADD	SP, SP, #1008

0x432974 LDP	X20, X19, [SP, #96]

0x432978 LDP	X22, X21, [SP, #80]

0x43297c LDP	X24, X23, [SP, #64]

0x432980 LDP	X26, X25, [SP, #48]

0x432984 LDP	X28, X27, [SP, #32]

0x432988 LDP	X29, X30, [SP, #16]

0x43298c LDR	D8, [SP], #112

0x432990 RET

0x432994 HINT	#0

0x432998 HINT	#0

0x43299c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:742	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start		exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	par_multi_interp.c:41-2060
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:41-71,83-88,99-131,141-153,184-186,194,202-208,216-223,229-241,252-261,267-272,278-340,346-351,382-400,415-468,479-482,488-518,526-536,544-557,568-571,583-636,646-685,693-706,717-758,768-815,823-845,855-856,865-891,1140-1161,1167,1177,1184,1304-1369,1562-1566,1575,1669-1705,1711-1737,1884-1976,1982-1997,2007-2032,2038-2043,2060.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 156.50 to 12.00 cycles (13.04x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 156.50 to 120.00 cycles (1.30x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 156.50 to 57.00 cycles (2.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 2184 bytes. The binary function is storing 2160 bytes.

General properties

nb instructions	1122
loop length	4488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

131.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	98.00	98.00	83.33	83.33	83.33	83.33	83.33	83.33	1.00	1.00	1.00	1.00	156.50	156.17	156.33	112.00	112.00
cycles	98.00	98.00	83.33	83.33	83.33	83.33	83.33	83.33	1.00	1.00	1.00	1.00	156.50	156.17	156.33	112.00	112.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	131.25
Overall L1	156.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 156.50 cycles. At this rate:

14% of peak load performance is reached (13.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42fe80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR D8, [SP, #400]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #1008	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X21, X23, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X1, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV D8, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X24, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X7, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X5, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP XZR, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, X8, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X25, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X28, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X9, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP XZR, XZR, [X29, #808]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP XZR, XZR, [X29, #792]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR XZR, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X10, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVN X8, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, XZR, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a89d0 <hypre_NumThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430004 <hypre_BoomerAMGBuildMultipass+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X19, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #528	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a7e70 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, SP, #536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a7ea0 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 430040 <hypre_BoomerAMGBuildMultipass+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X2, <4df044>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #520	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X2, #4000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a8460 <hypre_MPI_Bcast>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 430070 <hypre_BoomerAMGBuildMultipass+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 43009c <hypre_BoomerAMGBuildMultipass+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X8, 430094 <hypre_BoomerAMGBuildMultipass+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 481820 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X8, X22, X28, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X20, X24, X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X22, 4300c0 <hypre_BoomerAMGBuildMultipass+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X23, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X8, 4300cc <hypre_BoomerAMGBuildMultipass+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 4300e4 <hypre_BoomerAMGBuildMultipass+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dc0e4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 4320ec <hypre_BoomerAMGBuildMultipass+0x226c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #2512	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, SP, #624	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, SP, #608	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X28, X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 43013c <hypre_BoomerAMGBuildMultipass+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 430168 <hypre_BoomerAMGBuildMultipass+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 43016c <hypre_BoomerAMGBuildMultipass+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 4301a4 <hypre_BoomerAMGBuildMultipass+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 4301d4 <hypre_BoomerAMGBuildMultipass+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4301d4 <hypre_BoomerAMGBuildMultipass+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 430228 <hypre_BoomerAMGBuildMultipass+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X9, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X9, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X10, [X11, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X10, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X11, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X9, X8, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X0, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X11, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X10, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X11, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X10, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 430234 <hypre_BoomerAMGBuildMultipass+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 430238 <hypre_BoomerAMGBuildMultipass+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 430238 <hypre_BoomerAMGBuildMultipass+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4302b0 <hypre_BoomerAMGBuildMultipass+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X8, [X29, #824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 43026c <hypre_BoomerAMGBuildMultipass+0x3ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4302d4 <hypre_BoomerAMGBuildMultipass+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X3, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430378 <hypre_BoomerAMGBuildMultipass+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430354 <hypre_BoomerAMGBuildMultipass+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X8, [X29, #824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 430310 <hypre_BoomerAMGBuildMultipass+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 430378 <hypre_BoomerAMGBuildMultipass+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X3, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dc378>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 432380 <hypre_BoomerAMGBuildMultipass+0x2500>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #2960	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, SP, #616	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, SP, #600	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 4303f0 <hypre_BoomerAMGBuildMultipass+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4303f8 <hypre_BoomerAMGBuildMultipass+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X8, X28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X9], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4304c8 <hypre_BoomerAMGBuildMultipass+0x648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVN X15, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X17, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 43048c <hypre_BoomerAMGBuildMultipass+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430548 <hypre_BoomerAMGBuildMultipass+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X9, [X29, #824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4304f8 <hypre_BoomerAMGBuildMultipass+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 43056c <hypre_BoomerAMGBuildMultipass+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X3, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 430594 <hypre_BoomerAMGBuildMultipass+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430658 <hypre_BoomerAMGBuildMultipass+0x7d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4305d0 <hypre_BoomerAMGBuildMultipass+0x750>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 4306e0 <hypre_BoomerAMGBuildMultipass+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X22, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4306e0 <hypre_BoomerAMGBuildMultipass+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4306cc <hypre_BoomerAMGBuildMultipass+0x84c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP XZR, XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR XZR, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X28, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430850 <hypre_BoomerAMGBuildMultipass+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X10, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X12, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X14, X13, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDUR X15, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 430750 <hypre_BoomerAMGBuildMultipass+0x8d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X23, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4308d4 <hypre_BoomerAMGBuildMultipass+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X8, [X29, #824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 430890 <hypre_BoomerAMGBuildMultipass+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4308f8 <hypre_BoomerAMGBuildMultipass+0xa78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X3, <4df8fc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X4, <4df900>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #544	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, SP, #552	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X8, X28, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #544]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X3, #4000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X4, #4032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a86a0 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 430b38 <hypre_BoomerAMGBuildMultipass+0xcb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 430b38 <hypre_BoomerAMGBuildMultipass+0xcb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X24, <4df940>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X22, <4df944>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [X24, #4000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X22, #4032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X22, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430bc4 <hypre_BoomerAMGBuildMultipass+0xd44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X19, 430bcc <hypre_BoomerAMGBuildMultipass+0xd4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 430bd0 <hypre_BoomerAMGBuildMultipass+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 430c08 <hypre_BoomerAMGBuildMultipass+0xd88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X8, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X1, X9, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X1, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 430d14 <hypre_BoomerAMGBuildMultipass+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X15, X14, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDUR X16, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X18, X17, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDUR X0, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 430c5c <hypre_BoomerAMGBuildMultipass+0xddc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430e0c <hypre_BoomerAMGBuildMultipass+0xf8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 430dac <hypre_BoomerAMGBuildMultipass+0xf2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 430dc4 <hypre_BoomerAMGBuildMultipass+0xf44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dcdc4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #376	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 432dcc <hypre_BoomerAMGBuildMultipass.omp_outlined.4+0xac>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3360	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #696	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dcde4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 432dec <hypre_BoomerAMGBuildMultipass.omp_outlined.6+0xc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3552	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #184	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 430e14 <hypre_BoomerAMGBuildMultipass+0xf94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X20, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X22, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 431694 <hypre_BoomerAMGBuildMultipass+0x1814>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X23, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X28, X29, #168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X26, <4dce38>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X26, X26, #544	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X21, 432e40 <hypre_BoomerAMGBuildMultipass.omp_outlined.6+0x60>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #3792	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP XZR, XZR, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR XZR, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X23, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 430f7c <hypre_BoomerAMGBuildMultipass+0x10fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR XZR, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 431728 <hypre_BoomerAMGBuildMultipass+0x18a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X25, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 431784 <hypre_BoomerAMGBuildMultipass+0x1904>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X21, X29, #136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4dc788>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #712	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 433790 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x6e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #2640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #624	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #152	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, SP, #592	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X20, X29, #248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X22, X29, #152	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X19, X29, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, SP, #592	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X10, X29, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X8, X9, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X8, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, SP, #688	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBZ X25, 431e74 <hypre_BoomerAMGBuildMultipass+0x1ff4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X9, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X29, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4dc7f8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #736	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 433800 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x750>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3024	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X29, #104	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, SP, #728	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, SP, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X8, X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #464	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, SP, #760	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X10, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #720	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #736	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X24, X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #744	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 4318ac <hypre_BoomerAMGBuildMultipass+0x1a2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4318f0 <hypre_BoomerAMGBuildMultipass+0x1a70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4324f4 <hypre_BoomerAMGBuildMultipass+0x2674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X21, X29, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X20, 43490c <hypre_BoomerAMGBuildMultipass.omp_outlined.16+0x58c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X20, #896	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X27, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 431938 <hypre_BoomerAMGBuildMultipass+0x1ab8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
STP X9, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X29, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4dce84>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 434e8c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x9c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3568	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X29, #104	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, SP, #728	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, SP, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X8, X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #464	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, SP, #760	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X10, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #720	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #736	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X24, X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #744	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 431f38 <hypre_BoomerAMGBuildMultipass+0x20b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 431f7c <hypre_BoomerAMGBuildMultipass+0x20fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4324f4 <hypre_BoomerAMGBuildMultipass+0x2674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X21, X29, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X20, 435f98 <hypre_BoomerAMGBuildMultipass.omp_outlined.22+0x18>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X20, #1264	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X27, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 431fd4 <hypre_BoomerAMGBuildMultipass+0x2154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X0, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4325f0 <hypre_BoomerAMGBuildMultipass+0x2770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X4, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X5, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X8, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 489e20 <hypre_ParCSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X20, X22, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FCMP D8, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.NE 432668 <hypre_BoomerAMGBuildMultipass+0x27e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X1, 432694 <hypre_BoomerAMGBuildMultipass+0x2814>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 428050 <hypre_BoomerAMGInterpTruncation>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X8, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X8, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X9, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X21, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X21, 4328ac <hypre_BoomerAMGBuildMultipass+0x2a2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X0, X8, X9, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dc6c4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #880	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 4356cc <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1dc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3968	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43273c <hypre_BoomerAMGBuildMultipass+0x28bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 43271c <hypre_BoomerAMGBuildMultipass+0x289c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X0, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dc770>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #952	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 436778 <hypre_BoomerAMGBuildStdInterp+0x2f8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #704	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #664	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 432840 <hypre_BoomerAMGBuildMultipass+0x29c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4327d8 <hypre_BoomerAMGBuildMultipass+0x2958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
SUB X2, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a7470 <hypre_qsort0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dc850>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1024	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 436858 <hypre_BoomerAMGBuildStdInterp+0x3d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #704	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #664	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, SP, #672	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, SP, #472	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dc87c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1096	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 436884 <hypre_BoomerAMGBuildStdInterp+0x404>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #528	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #496	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #664	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4328f4 <hypre_BoomerAMGBuildMultipass+0x2a74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4328f4 <hypre_BoomerAMGBuildMultipass+0x2a74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X8, 432928 <hypre_BoomerAMGBuildMultipass+0x2aa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X20, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 432954 <hypre_BoomerAMGBuildMultipass+0x2ad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dc934>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 43693c <hypre_BoomerAMGBuildStdInterp+0x4bc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #800	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 432968 <hypre_BoomerAMGBuildMultipass+0x2ae8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 481820 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X19, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD SP, SP, #1008	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR D8, [SP], #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_5

Source file and lines	par_multi_interp.c:41-2060
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 156.50 to 57.00 cycles (2.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 2184 bytes. The binary function is storing 2160 bytes.

General properties

nb instructions	1122
loop length	4488
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

131.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	98.00	98.00	83.33	83.33	83.33	83.33	83.33	83.33	1.00	1.00	1.00	1.00	156.50	156.17	156.33	112.00	112.00
cycles	98.00	98.00	83.33	83.33	83.33	83.33	83.33	83.33	1.00	1.00	1.00	1.00	156.50	156.17	156.33	112.00	112.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	131.25
Overall L1	156.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 156.50 cycles. At this rate:

14% of peak load performance is reached (13.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42fe80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR D8, [SP, #400]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #1008	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X21, X23, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X1, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV D8, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X24, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X7, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X5, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP XZR, X9, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, X8, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X25, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X28, [X25, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X9, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP XZR, XZR, [X29, #808]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP XZR, XZR, [X29, #792]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR XZR, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X10, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVN X8, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, XZR, [SP, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a89d0 <hypre_NumThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430004 <hypre_BoomerAMGBuildMultipass+0x184>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X19, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #528	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a7e70 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, SP, #536	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a7ea0 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #536]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 430040 <hypre_BoomerAMGBuildMultipass+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X2, <4df044>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #520	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X2, #4000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a8460 <hypre_MPI_Bcast>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 430070 <hypre_BoomerAMGBuildMultipass+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 43009c <hypre_BoomerAMGBuildMultipass+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X8, 430094 <hypre_BoomerAMGBuildMultipass+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X19, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 481820 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X8, X22, X28, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X20, X24, X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X22, 4300c0 <hypre_BoomerAMGBuildMultipass+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X23, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X23, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X8, 4300cc <hypre_BoomerAMGBuildMultipass+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 4300e4 <hypre_BoomerAMGBuildMultipass+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dc0e4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 4320ec <hypre_BoomerAMGBuildMultipass+0x226c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #2512	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, SP, #624	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, SP, #608	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X10, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X28, X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 43013c <hypre_BoomerAMGBuildMultipass+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 430168 <hypre_BoomerAMGBuildMultipass+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 43016c <hypre_BoomerAMGBuildMultipass+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 4301a4 <hypre_BoomerAMGBuildMultipass+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 4301d4 <hypre_BoomerAMGBuildMultipass+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X0, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4301d4 <hypre_BoomerAMGBuildMultipass+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 430228 <hypre_BoomerAMGBuildMultipass+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X8, X9, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X9, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X10, [X11, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X10, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X11, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X9, X8, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X0, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X11, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X10, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X11, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X10, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 430234 <hypre_BoomerAMGBuildMultipass+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 430238 <hypre_BoomerAMGBuildMultipass+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X25, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 430238 <hypre_BoomerAMGBuildMultipass+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4302b0 <hypre_BoomerAMGBuildMultipass+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X8, [X29, #824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X9, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 43026c <hypre_BoomerAMGBuildMultipass+0x3ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4302d4 <hypre_BoomerAMGBuildMultipass+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X3, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430378 <hypre_BoomerAMGBuildMultipass+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430354 <hypre_BoomerAMGBuildMultipass+0x4d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X8, [X29, #824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 430310 <hypre_BoomerAMGBuildMultipass+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 430378 <hypre_BoomerAMGBuildMultipass+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X3, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dc378>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 432380 <hypre_BoomerAMGBuildMultipass+0x2500>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #2960	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #600]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X5, SP, #616	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, SP, #600	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 4303f0 <hypre_BoomerAMGBuildMultipass+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4303f8 <hypre_BoomerAMGBuildMultipass+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X8, X28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X9], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4304c8 <hypre_BoomerAMGBuildMultipass+0x648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVN X15, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X17, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 43048c <hypre_BoomerAMGBuildMultipass+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430548 <hypre_BoomerAMGBuildMultipass+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X9, [X29, #824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4304f8 <hypre_BoomerAMGBuildMultipass+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 43056c <hypre_BoomerAMGBuildMultipass+0x6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X3, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 430594 <hypre_BoomerAMGBuildMultipass+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430658 <hypre_BoomerAMGBuildMultipass+0x7d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 4305d0 <hypre_BoomerAMGBuildMultipass+0x750>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 4306e0 <hypre_BoomerAMGBuildMultipass+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X22, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4306e0 <hypre_BoomerAMGBuildMultipass+0x860>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4306cc <hypre_BoomerAMGBuildMultipass+0x84c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP XZR, XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR XZR, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X28, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430850 <hypre_BoomerAMGBuildMultipass+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X10, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X12, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X14, X13, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDUR X15, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 430750 <hypre_BoomerAMGBuildMultipass+0x8d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X23, [X8, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4308d4 <hypre_BoomerAMGBuildMultipass+0xa54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X8, [X29, #824]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 430890 <hypre_BoomerAMGBuildMultipass+0xa10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4308f8 <hypre_BoomerAMGBuildMultipass+0xa78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W0, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 480c50 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 481040 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X3, <4df8fc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X4, <4df900>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, SP, #544	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, SP, #552	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X8, X28, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #544]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X3, #4000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X4, #4032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a86a0 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #552]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 430b38 <hypre_BoomerAMGBuildMultipass+0xcb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 430b38 <hypre_BoomerAMGBuildMultipass+0xcb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X24, <4df940>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X22, <4df944>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X24, [X24, #4000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X22, #4032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X22, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430bc4 <hypre_BoomerAMGBuildMultipass+0xd44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X19, 430bcc <hypre_BoomerAMGBuildMultipass+0xd4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 430bd0 <hypre_BoomerAMGBuildMultipass+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 430c08 <hypre_BoomerAMGBuildMultipass+0xd88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X8, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X22, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X1, X9, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X1, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 430d14 <hypre_BoomerAMGBuildMultipass+0xe94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X15, X14, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDUR X16, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X18, X17, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDUR X0, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 430c5c <hypre_BoomerAMGBuildMultipass+0xddc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 430e0c <hypre_BoomerAMGBuildMultipass+0xf8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X0, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 430dac <hypre_BoomerAMGBuildMultipass+0xf2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 430dc4 <hypre_BoomerAMGBuildMultipass+0xf44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dcdc4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #376	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 432dcc <hypre_BoomerAMGBuildMultipass.omp_outlined.4+0xac>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3360	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #696	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dcde4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 432dec <hypre_BoomerAMGBuildMultipass.omp_outlined.6+0xc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3552	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #192	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #184	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 430e14 <hypre_BoomerAMGBuildMultipass+0xf94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X20, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X19, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X22, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 431694 <hypre_BoomerAMGBuildMultipass+0x1814>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X22, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X23, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X28, X29, #168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X26, <4dce38>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X26, X26, #544	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADRP X21, 432e40 <hypre_BoomerAMGBuildMultipass.omp_outlined.6+0x60>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #3792	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP XZR, XZR, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR XZR, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X23, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 430f7c <hypre_BoomerAMGBuildMultipass+0x10fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR XZR, [SP, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X0, 431728 <hypre_BoomerAMGBuildMultipass+0x18a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X25, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 431784 <hypre_BoomerAMGBuildMultipass+0x1904>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X21, X29, #136	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4dc788>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #712	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 433790 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x6e0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #2640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #624	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X5, X29, #152	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X6, X29, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, SP, #592	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB X20, X29, #248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X22, X29, #152	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X19, X29, #144	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, SP, #592	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X10, X29, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X8, X9, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X8, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, SP, #688	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBZ X25, 431e74 <hypre_BoomerAMGBuildMultipass+0x1ff4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X9, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X29, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4dc7f8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #736	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 433800 <hypre_BoomerAMGBuildMultipass.omp_outlined.10+0x750>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3024	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X29, #104	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, SP, #728	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, SP, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X8, X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #464	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, SP, #760	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X10, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #720	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #736	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X24, X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #744	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 4318ac <hypre_BoomerAMGBuildMultipass+0x1a2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4318f0 <hypre_BoomerAMGBuildMultipass+0x1a70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4324f4 <hypre_BoomerAMGBuildMultipass+0x2674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X21, X29, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X20, 43490c <hypre_BoomerAMGBuildMultipass.omp_outlined.16+0x58c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X20, #896	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X27, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 431938 <hypre_BoomerAMGBuildMultipass+0x1ab8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
STP X9, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X29, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4dce84>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 434e8c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x9c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3568	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X29, #104	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, SP, #728	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, SP, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #752	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X8, X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #680	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, SP, #464	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, SP, #760	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X10, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #720	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #736	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X24, X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB X8, X29, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X9, X29, #56	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X9, X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, SP, #744	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X19, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 431f38 <hypre_BoomerAMGBuildMultipass+0x20b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X0, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 431f7c <hypre_BoomerAMGBuildMultipass+0x20fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #648]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4324f4 <hypre_BoomerAMGBuildMultipass+0x2674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W8, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X21, X29, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X20, 435f98 <hypre_BoomerAMGBuildMultipass.omp_outlined.22+0x18>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X20, X20, #1264	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X27, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 431fd4 <hypre_BoomerAMGBuildMultipass+0x2154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X0, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #728]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #712]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #744]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #736]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR XZR, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #752]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #680]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4325f0 <hypre_BoomerAMGBuildMultipass+0x2770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X4, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [SP, #520]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X5, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [X8, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 489e20 <hypre_ParCSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X20, X22, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FCMP D8, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #864]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.NE 432668 <hypre_BoomerAMGBuildMultipass+0x27e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X1, 432694 <hypre_BoomerAMGBuildMultipass+0x2814>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D0, D8	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 428050 <hypre_BoomerAMGInterpTruncation>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X8, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X8, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X9, [SP, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X21, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X21, 4328ac <hypre_BoomerAMGBuildMultipass+0x2a2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X0, X8, X9, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dc6c4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #880	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 4356cc <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1dc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #3968	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43273c <hypre_BoomerAMGBuildMultipass+0x28bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 43271c <hypre_BoomerAMGBuildMultipass+0x289c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X8, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X0, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6c90 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4dc770>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #952	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 436778 <hypre_BoomerAMGBuildStdInterp+0x2f8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #704	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #664	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 432840 <hypre_BoomerAMGBuildMultipass+0x29c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4327d8 <hypre_BoomerAMGBuildMultipass+0x2958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
SUB X2, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a7470 <hypre_qsort0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dc850>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1024	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 436858 <hypre_BoomerAMGBuildStdInterp+0x3d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #704	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X4, SP, #640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #664	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, SP, #672	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, SP, #472	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dc87c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1096	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 436884 <hypre_BoomerAMGBuildStdInterp+0x404>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #528	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #496	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #664	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR XZR, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4328f4 <hypre_BoomerAMGBuildMultipass+0x2a74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #560]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4328f4 <hypre_BoomerAMGBuildMultipass+0x2a74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #664]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4a6d90 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [SP, #704]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X8, 432928 <hypre_BoomerAMGBuildMultipass+0x2aa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X20, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 432954 <hypre_BoomerAMGBuildMultipass+0x2ad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4dc934>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X2, 43693c <hypre_BoomerAMGBuildStdInterp+0x4bc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X2, #800	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, SP, #632	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X29, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f600 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 432968 <hypre_BoomerAMGBuildMultipass+0x2ae8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 481820 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X19, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD SP, SP, #1008	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR D8, [SP], #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass–	0.26	0.05
○Loop 661 - par_multi_interp.c:385-400 - exec	0.02	0.28
○Loop 624 - par_multi_interp.c:1158-1161 - exec	0.01	0.15
▼Loop 651 - par_multi_interp.c:488-514 - exec–	0.01	0.14
○Loop 653 - par_multi_interp.c:491-498 - exec	0.08	1.16
○Loop 652 - par_multi_interp.c:501-508 - exec	0.00	0.00
○Loop 601 - par_multi_interp.c:2016-2017 - exec	0.00	0.00
▼Loop 617 - par_multi_interp.c:1310-1566 - exec–	0.00	0.00
○Loop 620 - par_multi_interp.c:1338-1338 - exec	0.00	0.00
○Loop 619 - par_multi_interp.c:1337-1338 - exec	0.00	0.00
○Loop 621 - par_multi_interp.c:1333-1334 - exec	0.00	0.00
○Loop 618 - par_multi_interp.c:1337-1338 - exec	0.00	0.00
○Loop 622 - par_multi_interp.c:1333-1334 - exec	0.00	0.00
▼Loop 616 - par_multi_interp.c:1310-1566 - exec–	0.00	0.00
▼Loop 615 - par_multi_interp.c:1310-1566 - exec–	0.00	0.00
○Loop 614 - par_multi_interp.c:1310-1566 - exec	0.00	0.00
○Loop 623 - par_multi_interp.c:1334-1334 - exec	0.00	0.00
▼Loop 603 - par_multi_interp.c:1982-1989 - exec–	0.00	0.00
○Loop 602 - par_multi_interp.c:1982-1984 - exec	0.00	0.00
▼Loop 649 - par_multi_interp.c:526-530 - exec–	0.00	0.00
○Loop 650 - par_multi_interp.c:529-530 - exec	0.00	0.00
▼Loop 627 - par_multi_interp.c:433-891 - exec–	0.00	0.00
▼Loop 628 - par_multi_interp.c:433-891 - exec–	0.00	0.00
▼Loop 626 - par_multi_interp.c:433-891 - exec–	0.00	0.00
▼Loop 625 - par_multi_interp.c:433-891 - exec–	0.00	0.00
▼Loop 632 - par_multi_interp.c:773-784 - exec–	0.00	0.00
○Loop 633 - par_multi_interp.c:775-780 - exec	0.00	0.00
○Loop 639 - par_multi_interp.c:703-717 - exec	0.00	0.00
▼Loop 634 - par_multi_interp.c:733-758 - exec–	0.00	0.00
▼Loop 635 - par_multi_interp.c:735-758 - exec–	0.00	0.00
▼Loop 636 - par_multi_interp.c:749-758 - exec–	0.00	0.00
○Loop 637 - par_multi_interp.c:753-755 - exec	0.00	0.00
○Loop 638 - par_multi_interp.c:742-745 - exec	0.00	0.00
▼Loop 629 - par_multi_interp.c:823-856 - exec–	0.00	0.00
▼Loop 630 - par_multi_interp.c:829-856 - exec–	0.00	0.00
○Loop 631 - par_multi_interp.c:839-843 - exec	0.00	0.00
▼Loop 605 - par_multi_interp.c:1674-1888 - exec–	0.00	0.00
▼Loop 606 - par_multi_interp.c:1688-1705 - exec–	0.00	0.00
▼Loop 607 - par_multi_interp.c:1690-1705 - exec–	0.00	0.00
○Loop 609 - par_multi_interp.c:1703-1705 - exec	0.00	0.00
○Loop 613 - par_multi_interp.c:1699-1699 - exec	0.00	0.00
○Loop 608 - par_multi_interp.c:1703-1705 - exec	0.00	0.00
○Loop 612 - par_multi_interp.c:1697-1699 - exec	0.00	0.00
○Loop 610 - par_multi_interp.c:1705-1705 - exec	0.00	0.00
○Loop 611 - par_multi_interp.c:1697-1699 - exec	0.00	0.00
○Loop 666 - par_multi_interp.c:205-208 - exec	0.00	0.00
▼Loop 641 - par_multi_interp.c:646-661 - exec–	0.00	0.00
▼Loop 640 - par_multi_interp.c:646-657 - exec–	0.00	0.04
○Loop 642 - par_multi_interp.c:651-655 - exec	0.07	1.09
▼Loop 657 - par_multi_interp.c:440-457 - exec–	0.00	0.00
▼Loop 658 - par_multi_interp.c:440-457 - exec–	0.00	0.00
○Loop 656 - par_multi_interp.c:440-457 - exec	0.00	0.00
▼Loop 654 - par_multi_interp.c:466-468 - exec–	0.00	0.00
○Loop 655 - par_multi_interp.c:466-468 - exec	0.00	0.00
○Loop 604 - par_multi_interp.c:1962-1968 - exec	0.00	0.00
▼Loop 643 - par_multi_interp.c:548-600 - exec–	0.00	0.00
▼Loop 646 - par_multi_interp.c:550-571 - exec–	0.01	0.19
○Loop 648 - par_multi_interp.c:554-557 - exec	0.05	0.76
○Loop 647 - par_multi_interp.c:568-571 - exec	0.00	0.00
▼Loop 644 - par_multi_interp.c:590-594 - exec–	0.00	0.00
○Loop 645 - par_multi_interp.c:593-594 - exec	0.00	0.00
▼Loop 659 - par_multi_interp.c:415-423 - exec–	0.00	0.00
○Loop 660 - par_multi_interp.c:418-423 - exec	0.00	0.00
▼Loop 664 - par_multi_interp.c:307-311 - exec–	0.00	0.00
○Loop 665 - par_multi_interp.c:310-311 - exec	0.00	0.00
▼Loop 662 - par_multi_interp.c:323-327 - exec–	0.00	0.00
○Loop 663 - par_multi_interp.c:326-327 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code