OV - exec - Loop 958

	Loop Id: 958	Module: exec	Source: par_multi_interp.c:385-410	Coverage: 0.01%

0x45de14 CMN	X30, #1

0x45de18 B.EQ	461f84

0x45de1c STR	XZR, [X2, X0,LSL #3]    [7]

0x45de20 STR	XZR, [X14, X0,LSL #3]    [3]

0x45de24 STR	X13, [X22, X0,LSL #3]    [2]

0x45de28 STR	X13, [X15, X0,LSL #3]    [4]

0x45de2c ADD	X0, X0, #1

0x45de30 LDR	X8, [X16, X0,LSL #3]    [5]

0x45de34 CMP	X8, #1

0x45de38 B.EQ	45dee8

0x45de3c CMN	X8, #1

0x45de40 B.EQ	461f68

0x45de44 STR	XZR, [X2, X0,LSL #3]    [7]

0x45de48 STR	XZR, [X14, X0,LSL #3]    [3]

0x45de4c STR	X13, [X22, X0,LSL #3]    [2]

0x45de50 STR	X13, [X15, X0,LSL #3]    [4]

0x45de54 ADD	X7, X0, #1

0x45de58 LDR	X9, [X16, X7,LSL #3]    [5]

0x45de5c CMP	X9, #1

0x45de60 B.EQ	45df10

0x45de64 CMN	X9, #1

0x45de68 B.EQ	461f4c

0x45de6c STR	XZR, [X2, X7,LSL #3]    [7]

0x45de70 STR	XZR, [X14, X7,LSL #3]    [3]

0x45de74 STR	X13, [X22, X7,LSL #3]    [2]

0x45de78 STR	X13, [X15, X7,LSL #3]    [4]

0x45de7c ADD	X10, X0, #2

0x45de80 LDR	X11, [X16, X10,LSL #3]    [5]

0x45de84 CMP	X11, #1

0x45de88 B.EQ	45df38

0x45de8c CMN	X11, #1

0x45de90 B.EQ	461f30

0x45de94 STR	XZR, [X2, X10,LSL #3]    [7]

0x45de98 STR	XZR, [X14, X10,LSL #3]    [3]

0x45de9c STR	X13, [X22, X10,LSL #3]    [2]

0x45dea0 STR	X13, [X15, X10,LSL #3]    [4]

0x45dea4 LDR	X12, [SP, #312]    [1]

0x45dea8 ADD	X0, X0, #3

0x45deac CMP	X12, X0

0x45deb0 B.EQ	45df60

0x45deb4 LDR	X30, [X16, X0,LSL #3]    [5]

0x45deb8 CMP	X30, #1

0x45debc B.NE	45de14

0x45dec0 STR	X1, [X15, X0,LSL #3]    [4]

0x45dec4 STR	X0, [X17, X1,LSL #3]    [6]

0x45dec8 ADD	X1, X1, #1

0x45decc STR	XZR, [X22, X0,LSL #3]    [2]

0x45ded0 STR	X30, [X2, X0,LSL #3]    [7]

0x45ded4 STR	XZR, [X14, X0,LSL #3]    [3]

0x45ded8 ADD	X0, X0, #1

0x45dedc LDR	X8, [X16, X0,LSL #3]    [5]

0x45dee0 CMP	X8, #1

0x45dee4 B.NE	45de3c

0x45dee8 STR	X1, [X15, X0,LSL #3]    [4]

0x45deec ADD	X7, X0, #1

0x45def0 STR	X0, [X17, X1,LSL #3]    [6]

0x45def4 ADD	X1, X1, #1

0x45def8 STR	XZR, [X22, X0,LSL #3]    [2]

0x45defc STR	X8, [X2, X0,LSL #3]    [7]

0x45df00 STR	XZR, [X14, X0,LSL #3]    [3]

0x45df04 LDR	X9, [X16, X7,LSL #3]    [5]

0x45df08 CMP	X9, #1

0x45df0c B.NE	45de64

0x45df10 STR	X1, [X15, X7,LSL #3]    [4]

0x45df14 ADD	X10, X0, #2

0x45df18 STR	X7, [X17, X1,LSL #3]    [6]

0x45df1c ADD	X1, X1, #1

0x45df20 STR	XZR, [X22, X7,LSL #3]    [2]

0x45df24 STR	X9, [X2, X7,LSL #3]    [7]

0x45df28 STR	XZR, [X14, X7,LSL #3]    [3]

0x45df2c LDR	X11, [X16, X10,LSL #3]    [5]

0x45df30 CMP	X11, #1

0x45df34 B.NE	45de8c

0x45df38 LDR	X12, [SP, #312]    [1]

0x45df3c ADD	X0, X0, #3

0x45df40 STR	X1, [X15, X10,LSL #3]    [4]

0x45df44 STR	X10, [X17, X1,LSL #3]    [6]

0x45df48 ADD	X1, X1, #1

0x45df4c STR	XZR, [X22, X10,LSL #3]    [2]

0x45df50 STR	X11, [X2, X10,LSL #3]    [7]

0x45df54 STR	XZR, [X14, X10,LSL #3]    [3]

0x45df58 CMP	X12, X0

0x45df5c B.NE	45deb4

0x461f30 STR	X10, [X4, X3,LSL #3]    [8]

0x461f34 SUB	X3, X3, #1

0x461f38 STR	XZR, [X2, X10,LSL #3]    [7]

0x461f3c STR	XZR, [X14, X10,LSL #3]    [3]

0x461f40 STR	X11, [X22, X10,LSL #3]    [2]

0x461f44 STR	X11, [X15, X10,LSL #3]    [4]

0x461f48 B	45dea4

0x461f4c STR	X7, [X4, X3,LSL #3]    [8]

0x461f50 SUB	X3, X3, #1

0x461f54 STR	XZR, [X2, X7,LSL #3]    [7]

0x461f58 STR	XZR, [X14, X7,LSL #3]    [3]

0x461f5c STR	X9, [X22, X7,LSL #3]    [2]

0x461f60 STR	X9, [X15, X7,LSL #3]    [4]

0x461f64 B	45de7c

0x461f68 STR	X0, [X4, X3,LSL #3]    [8]

0x461f6c SUB	X3, X3, #1

0x461f70 STR	XZR, [X2, X0,LSL #3]    [7]

0x461f74 STR	XZR, [X14, X0,LSL #3]    [3]

0x461f78 STR	X8, [X22, X0,LSL #3]    [2]

0x461f7c STR	X8, [X15, X0,LSL #3]    [4]

0x461f80 B	45de54

0x461f84 STR	X0, [X4, X3,LSL #3]    [8]

0x461f88 SUB	X3, X3, #1

0x461f8c STR	XZR, [X2, X0,LSL #3]    [7]

0x461f90 STR	XZR, [X14, X0,LSL #3]    [3]

0x461f94 STR	X30, [X22, X0,LSL #3]    [2]

0x461f98 STR	X30, [X15, X0,LSL #3]    [4]

0x461f9c B	45de2c

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 385 - 410

--------------------------------------------------------------------------------

385:    for (i = 0; i < n_fine; i++)

386:    {

387:       if (CF_marker[i] == 1)

388:       {

389:          fine_to_coarse[i] = cnt; /* this C point is assigned index

390:                                      coarse_counter on coarse grid,

391:                                      and in column of P */

392:          C_array[cnt++] = i;

393:          assigned[i] = 0;

394:          P_diag_i[i+1] = 1; /* one element in row i1 of P */

395:          P_offd_i[i+1] = 0;

396:       }

397:       else if (CF_marker[i] == -1)

398:       {

399:          pass_array[p_cnt--] = i;

400:          P_diag_i[i+1] = 0;

401:          P_offd_i[i+1] = 0;

402:          assigned[i] = -1;

403:          fine_to_coarse[i] = -1;

404:       }

405:       else

406:       {

407:          P_diag_i[i+1] = 0;

408:          P_offd_i[i+1] = 0;

409:          assigned[i] = -1;

410:          fine_to_coarse[i] = -1;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	P12, P13, P15, P16,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:385-410
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	14.00
Front-end cycles	13.88
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	4.92
P3 cycles	4.92
P4 cycles	4.83
P5 cycles	4.83
P6 cycles	4.75
P7 cycles	4.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	28.00
P13 cycles	28.00
P14 cycles	9.00
P15 cycles	28.00
P16 cycles	28.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	56.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.57
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	448.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	P12, P13, P15, P16,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:385-410
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	14.00
Front-end cycles	13.88
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	4.92
P3 cycles	4.92
P4 cycles	4.83
P5 cycles	4.83
P6 cycles	4.75
P7 cycles	4.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	28.00
P13 cycles	28.00
P14 cycles	9.00
P15 cycles	28.00
P16 cycles	28.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	56.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.57
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	448.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:385-410
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:385-410.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 81 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 28.00 to 14.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.50	8.50	4.92	4.92	4.83	4.83	4.75	4.75	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00
cycles	8.50	8.50	4.92	4.92	4.83	4.83	4.75	4.75	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Overall L1	28.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

2% of peak load performance is reached (2.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45deb4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
CMN X30, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461f84 <hypre_BoomerAMGBuildMultipass+0x4724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X8, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45dee8 <hypre_BoomerAMGBuildMultipass+0x688>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461f68 <hypre_BoomerAMGBuildMultipass+0x4708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X9, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45df10 <hypre_BoomerAMGBuildMultipass+0x6b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461f4c <hypre_BoomerAMGBuildMultipass+0x46ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X11, [X16, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45df38 <hypre_BoomerAMGBuildMultipass+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461f30 <hypre_BoomerAMGBuildMultipass+0x46d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [SP, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X12, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45df60 <hypre_BoomerAMGBuildMultipass+0x700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X30, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45de14 <hypre_BoomerAMGBuildMultipass+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X30, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X8, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45de3c <hypre_BoomerAMGBuildMultipass+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45de64 <hypre_BoomerAMGBuildMultipass+0x604>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X7, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X16, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45de8c <hypre_BoomerAMGBuildMultipass+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X1, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [X2, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X12, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45deb4 <hypre_BoomerAMGBuildMultipass+0x654>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X10, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X2, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45dea4 <hypre_BoomerAMGBuildMultipass+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X7, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45de7c <hypre_BoomerAMGBuildMultipass+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45de54 <hypre_BoomerAMGBuildMultipass+0x5f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X30, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X30, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45de2c <hypre_BoomerAMGBuildMultipass+0x5cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:385-410
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.50	8.50	4.92	4.92	4.83	4.83	4.75	4.75	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00
cycles	8.50	8.50	4.92	4.92	4.83	4.83	4.75	4.75	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Overall L1	28.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

2% of peak load performance is reached (2.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45deb4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
CMN X30, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461f84 <hypre_BoomerAMGBuildMultipass+0x4724>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X8, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45dee8 <hypre_BoomerAMGBuildMultipass+0x688>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461f68 <hypre_BoomerAMGBuildMultipass+0x4708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X9, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45df10 <hypre_BoomerAMGBuildMultipass+0x6b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461f4c <hypre_BoomerAMGBuildMultipass+0x46ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X11, [X16, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45df38 <hypre_BoomerAMGBuildMultipass+0x6d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461f30 <hypre_BoomerAMGBuildMultipass+0x46d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [X2, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X12, [SP, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X12, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45df60 <hypre_BoomerAMGBuildMultipass+0x700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X30, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45de14 <hypre_BoomerAMGBuildMultipass+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X30, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X8, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45de3c <hypre_BoomerAMGBuildMultipass+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X0, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X9, [X16, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45de64 <hypre_BoomerAMGBuildMultipass+0x604>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X0, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X7, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X16, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45de8c <hypre_BoomerAMGBuildMultipass+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X1, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [X17, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [X2, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X12, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45deb4 <hypre_BoomerAMGBuildMultipass+0x654>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X10, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X2, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [X22, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [X15, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45dea4 <hypre_BoomerAMGBuildMultipass+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X7, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X2, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X22, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45de7c <hypre_BoomerAMGBuildMultipass+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45de54 <hypre_BoomerAMGBuildMultipass+0x5f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR XZR, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X30, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X30, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45de2c <hypre_BoomerAMGBuildMultipass+0x5cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code