OV - exec - Loop 862

	Loop Id: 862	Module: exec	Source: par_multi_interp.c:1811-1837	Coverage: 0.74%

0x45b59c LDR	X11, [X27, X2]

0x45b5a0 LDR	X5, [X27, X4]

0x45b5a4 CMP	X5, X11

0x45b5a8 B.EQ	45b5e0

0x45b5ac ADD	X0, X0, #1

0x45b5b0 CMP	X0, X14

0x45b5b4 B.EQ	45b5f4

0x45b5b8 LDR	X11, [X12, X0,LSL #3]

0x45b5bc UBFM	X2, X11, #61, #60

0x45b5c0 LDR	X28, [X26, X2]

0x45b5c4 CMP	X3, X28

0x45b5c8 B.EQ	45bb34

0x45b5cc LDR	X15, [X7, X2]

0x45b5d0 CMN	X15, #3

0x45b5d4 B.EQ	45b5ac

0x45b5d8 CMP	X18, #1

0x45b5dc B.NE	45b59c

0x45b5e0 LDR	D28, [X21, X0,LSL #3]

0x45b5e4 ADD	X0, X0, #1

0x45b5e8 FADD	D20, D20, D28

0x45b5ec CMP	X0, X14

0x45b5f0 B.NE	45b5b8

0x45bb34 LDR	X28, [SP, #120]

0x45bb38 ADD	X11, X2, #8

0x45bb3c LDR	X5, [X28, X2]

0x45bb40 LDR	X15, [X28, X11]

0x45bb44 CMP	X5, X15

0x45bb48 B.GE	45bcd8

0x45bb4c SUB	X28, X15, X5

0x45bb50 ANDS	X28, X28, #4160

0x45bb54 B.EQ	45bc00

0x45bb58 CMP	X28, #1

0x45bb5c B.EQ	45bbc8

0x45bb60 CMP	X28, #2

0x45bb64 B.EQ	45bb98

0x45bb68 LDR	X28, [X25, X5,LSL #3]

0x45bb6c LDR	D17, [X20, X5,LSL #3]

0x45bb70 ADD	X5, X5, #1

0x45bb74 LDR	D18, [X21, X0,LSL #3]

0x45bb78 LDR	X28, [X23, X28,LSL #3]

0x45bb7c FMUL	D0, D18, D17

0x45bb80 UBFM	X28, X28, #61, #60

0x45bb84 LDR	D26, [X20, X28]

0x45bb88 FADD	D29, D29, D0

0x45bb8c FADD	D20, D20, D0

0x45bb90 FADD	D1, D26, D0

0x45bb94 STR	D1, [X20, X28]

0x45bb98 LDR	X28, [X25, X5,LSL #3]

0x45bb9c LDR	D24, [X20, X5,LSL #3]

0x45bba0 ADD	X5, X5, #1

0x45bba4 LDR	D25, [X21, X0,LSL #3]

0x45bba8 LDR	X28, [X23, X28,LSL #3]

0x45bbac FMUL	D2, D25, D24

0x45bbb0 UBFM	X28, X28, #61, #60

0x45bbb4 LDR	D7, [X20, X28]

0x45bbb8 FADD	D29, D29, D2

0x45bbbc FADD	D20, D20, D2

0x45bbc0 FADD	D3, D7, D2

0x45bbc4 STR	D3, [X20, X28]

0x45bbc8 LDR	X28, [X25, X5,LSL #3]

0x45bbcc LDR	D5, [X20, X5,LSL #3]

0x45bbd0 ADD	X5, X5, #1

0x45bbd4 LDR	D6, [X21, X0,LSL #3]

0x45bbd8 LDR	X28, [X23, X28,LSL #3]

0x45bbdc FMUL	D31, D6, D5

0x45bbe0 UBFM	X28, X28, #61, #60

0x45bbe4 LDR	D4, [X20, X28]

0x45bbe8 FADD	D29, D29, D31

0x45bbec FADD	D20, D20, D31

0x45bbf0 FADD	D16, D4, D31

0x45bbf4 STR	D16, [X20, X28]

0x45bbf8 CMP	X5, X15

0x45bbfc B.EQ	45bcd8

0x45bc00 STP	X26, X22, [SP, #160]

0x45bc04 STP	X6, X13, [SP, #176]

  (864) 0x45bc08 ADD	X13, X5, #1

  (864) 0x45bc0c ADD	X26, X5, #3

  (864) 0x45bc10 ADD	X28, X13, #1

  (864) 0x45bc14 LDR	X22, [X25, X5,LSL #3]

  (864) 0x45bc18 LDR	D19, [X21, X0,LSL #3]

  (864) 0x45bc1c LDR	D21, [X20, X5,LSL #3]

  (864) 0x45bc20 ADD	X5, X5, #4

  (864) 0x45bc24 LDR	X6, [X23, X22,LSL #3]

  (864) 0x45bc28 LDR	X22, [X25, X13,LSL #3]

  (864) 0x45bc2c FMUL	D22, D19, D21

  (864) 0x45bc30 UBFM	X6, X6, #61, #60

  (864) 0x45bc34 LDR	D23, [X20, X6]

  (864) 0x45bc38 LDR	X22, [X23, X22,LSL #3]

  (864) 0x45bc3c FADD	D27, D29, D22

  (864) 0x45bc40 FADD	D30, D20, D22

  (864) 0x45bc44 FADD	D31, D23, D22

  (864) 0x45bc48 UBFM	X22, X22, #61, #60

  (864) 0x45bc4c STR	D31, [X20, X6]

  (864) 0x45bc50 LDR	D18, [X20, X13,LSL #3]

  (864) 0x45bc54 LDR	D28, [X21, X0,LSL #3]

  (864) 0x45bc58 LDR	D17, [X20, X22]

  (864) 0x45bc5c LDR	X13, [X25, X28,LSL #3]

  (864) 0x45bc60 FMUL	D0, D28, D18

  (864) 0x45bc64 LDR	X6, [X25, X26,LSL #3]

  (864) 0x45bc68 LDR	X13, [X23, X13,LSL #3]

  (864) 0x45bc6c LDR	X6, [X23, X6,LSL #3]

  (864) 0x45bc70 FADD	D26, D17, D0

  (864) 0x45bc74 FADD	D1, D27, D0

  (864) 0x45bc78 FADD	D25, D30, D0

  (864) 0x45bc7c UBFM	X13, X13, #61, #60

  (864) 0x45bc80 UBFM	X6, X6, #61, #60

  (864) 0x45bc84 STR	D26, [X20, X22]

  (864) 0x45bc88 LDR	D24, [X21, X0,LSL #3]

  (864) 0x45bc8c LDR	D2, [X20, X28,LSL #3]

  (864) 0x45bc90 LDR	D7, [X20, X13]

  (864) 0x45bc94 FMUL	D3, D24, D2

  (864) 0x45bc98 FADD	D6, D7, D3

  (864) 0x45bc9c FADD	D5, D1, D3

  (864) 0x45bca0 FADD	D4, D25, D3

  (864) 0x45bca4 STR	D6, [X20, X13]

  (864) 0x45bca8 LDR	D29, [X21, X0,LSL #3]

  (864) 0x45bcac LDR	D20, [X20, X26,LSL #3]

  (864) 0x45bcb0 LDR	D16, [X20, X6]

  (864) 0x45bcb4 FMUL	D31, D29, D20

  (864) 0x45bcb8 FADD	D19, D16, D31

  (864) 0x45bcbc FADD	D29, D5, D31

  (864) 0x45bcc0 FADD	D20, D4, D31

  (864) 0x45bcc4 STR	D19, [X20, X6]

  (864) 0x45bcc8 CMP	X5, X15

  (864) 0x45bccc B.NE	45bc08

0x45bcd0 LDP	X26, X22, [SP, #160]

0x45bcd4 LDP	X6, X13, [SP, #176]

0x45bcd8 LDR	X15, [SP, #112]

0x45bcdc LDR	X2, [X15, X2]

0x45bce0 LDR	X28, [X15, X11]

0x45bce4 CMP	X2, X28

0x45bce8 B.GE	45b5ac

0x45bcec SUB	X11, X28, X2

0x45bcf0 ANDS	X5, X11, #4160

0x45bcf4 B.EQ	45bda0

0x45bcf8 CMP	X5, #1

0x45bcfc B.EQ	45bd68

0x45bd00 CMP	X5, #2

0x45bd04 B.EQ	45bd38

0x45bd08 LDR	X15, [X24, X2,LSL #3]

0x45bd0c LDR	D22, [X19, X2,LSL #3]

0x45bd10 ADD	X2, X2, #1

0x45bd14 LDR	D21, [X21, X0,LSL #3]

0x45bd18 LDR	X11, [X22, X15,LSL #3]

0x45bd1c FMUL	D23, D21, D22

0x45bd20 UBFM	X5, X11, #61, #60

0x45bd24 LDR	D27, [X19, X5]

0x45bd28 FADD	D29, D29, D23

0x45bd2c FADD	D20, D20, D23

0x45bd30 FADD	D30, D27, D23

0x45bd34 STR	D30, [X19, X5]

0x45bd38 LDR	X15, [X24, X2,LSL #3]

0x45bd3c LDR	D28, [X19, X2,LSL #3]

0x45bd40 ADD	X2, X2, #1

0x45bd44 LDR	D31, [X21, X0,LSL #3]

0x45bd48 LDR	X11, [X22, X15,LSL #3]

0x45bd4c FMUL	D18, D31, D28

0x45bd50 UBFM	X5, X11, #61, #60

0x45bd54 LDR	D17, [X19, X5]

0x45bd58 FADD	D29, D29, D18

0x45bd5c FADD	D20, D20, D18

0x45bd60 FADD	D0, D17, D18

0x45bd64 STR	D0, [X19, X5]

0x45bd68 LDR	X15, [X24, X2,LSL #3]

0x45bd6c LDR	D1, [X19, X2,LSL #3]

0x45bd70 ADD	X2, X2, #1

0x45bd74 LDR	D26, [X21, X0,LSL #3]

0x45bd78 LDR	X11, [X22, X15,LSL #3]

0x45bd7c FMUL	D31, D26, D1

0x45bd80 UBFM	X5, X11, #61, #60

0x45bd84 LDR	D25, [X19, X5]

0x45bd88 FADD	D29, D29, D31

0x45bd8c FADD	D20, D20, D31

0x45bd90 FADD	D24, D25, D31

0x45bd94 STR	D24, [X19, X5]

0x45bd98 CMP	X2, X28

0x45bd9c B.EQ	45b5ac

0x45bda0 STP	X26, X23, [SP, #160]

  (863) 0x45bda4 ADD	X11, X2, #1

  (863) 0x45bda8 ADD	X23, X2, #3

  (863) 0x45bdac LDR	X26, [X24, X2,LSL #3]

  (863) 0x45bdb0 LDR	D2, [X21, X0,LSL #3]

  (863) 0x45bdb4 LDR	D7, [X19, X2,LSL #3]

  (863) 0x45bdb8 ADD	X2, X2, #4

  (863) 0x45bdbc LDR	X15, [X22, X26,LSL #3]

  (863) 0x45bdc0 ADD	X26, X11, #1

  (863) 0x45bdc4 FMUL	D3, D2, D7

  (863) 0x45bdc8 UBFM	X5, X15, #61, #60

  (863) 0x45bdcc LDR	X15, [X24, X11,LSL #3]

  (863) 0x45bdd0 LDR	D6, [X19, X5]

  (863) 0x45bdd4 FADD	D5, D29, D3

  (863) 0x45bdd8 LDR	X15, [X22, X15,LSL #3]

  (863) 0x45bddc FADD	D4, D20, D3

  (863) 0x45bde0 FADD	D29, D6, D3

  (863) 0x45bde4 UBFM	X15, X15, #61, #60

  (863) 0x45bde8 STR	D29, [X19, X5]

  (863) 0x45bdec LDR	D20, [X21, X0,LSL #3]

  (863) 0x45bdf0 LDR	D16, [X19, X11,LSL #3]

  (863) 0x45bdf4 LDR	D19, [X19, X15]

  (863) 0x45bdf8 LDR	X11, [X24, X26,LSL #3]

  (863) 0x45bdfc FMUL	D21, D20, D16

  (863) 0x45be00 LDR	X5, [X24, X23,LSL #3]

  (863) 0x45be04 LDR	X11, [X22, X11,LSL #3]

  (863) 0x45be08 LDR	X5, [X22, X5,LSL #3]

  (863) 0x45be0c FADD	D22, D19, D21

  (863) 0x45be10 FADD	D23, D5, D21

  (863) 0x45be14 FADD	D27, D4, D21

  (863) 0x45be18 UBFM	X11, X11, #61, #60

  (863) 0x45be1c UBFM	X5, X5, #61, #60

  (863) 0x45be20 STR	D22, [X19, X15]

  (863) 0x45be24 LDR	D31, [X19, X26,LSL #3]

  (863) 0x45be28 LDR	D30, [X21, X0,LSL #3]

  (863) 0x45be2c LDR	D28, [X19, X11]

  (863) 0x45be30 FMUL	D17, D30, D31

  (863) 0x45be34 FADD	D18, D28, D17

  (863) 0x45be38 FADD	D0, D23, D17

  (863) 0x45be3c FADD	D26, D27, D17

  (863) 0x45be40 STR	D18, [X19, X11]

  (863) 0x45be44 LDR	D1, [X21, X0,LSL #3]

  (863) 0x45be48 LDR	D25, [X19, X23,LSL #3]

  (863) 0x45be4c LDR	D24, [X19, X5]

  (863) 0x45be50 FMUL	D31, D1, D25

  (863) 0x45be54 FADD	D2, D24, D31

  (863) 0x45be58 FADD	D29, D0, D31

  (863) 0x45be5c FADD	D20, D26, D31

  (863) 0x45be60 STR	D2, [X19, X5]

  (863) 0x45be64 CMP	X2, X28

  (863) 0x45be68 B.NE	45bda4

0x45be6c LDP	X26, X23, [SP, #160]

0x45be70 B	45b5ac

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1811 - 1837

--------------------------------------------------------------------------------

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

Coverage (%)	Name	Source Location	Module
►99.15+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.56
CQA speedup if FP arith vectorized	1.37
CQA speedup if fully vectorized	1.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1811-1811,par_multi_interp.c:1814-1816,par_multi_interp.c:1819-1824,par_multi_interp.c:1827-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.17
CQA cycles if no scalar integer	11.67
CQA cycles if FP arith vectorized	13.25
CQA cycles if fully vectorized	13.83
Front-end cycles	16.25
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	5.67
P7 cycles	5.67
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	7.75
P11 cycles	7.75
P12 cycles	18.17
P13 cycles	17.83
P14 cycles	18.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	130.00
Nb uops	130.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	1.38
Nb FLOP add-sub	19.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.42
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	52.99
Vector-efficiency ratio load	52.50
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.56
CQA speedup if FP arith vectorized	1.37
CQA speedup if fully vectorized	1.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source	par_multi_interp.c:1811-1811,par_multi_interp.c:1814-1816,par_multi_interp.c:1819-1824,par_multi_interp.c:1827-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.17
CQA cycles if no scalar integer	11.67
CQA cycles if FP arith vectorized	13.25
CQA cycles if fully vectorized	13.83
Front-end cycles	16.25
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	5.67
P3 cycles	5.67
P4 cycles	5.67
P5 cycles	5.67
P6 cycles	5.67
P7 cycles	5.67
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	7.75
P11 cycles	7.75
P12 cycles	18.17
P13 cycles	17.83
P14 cycles	18.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	130.00
Nb uops	130.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	1.38
Nb FLOP add-sub	19.00
Nb FLOP mul	6.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.42
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	52.99
Vector-efficiency ratio load	52.50
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811-1837.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811,1814-1816,1819-1824,1827-1830,1835-1837.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 68 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.17 to 11.67 cycles (1.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 18.17 to 13.83 cycles (1.31x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

19: addition or subtraction
6: multiply

The binary loop is loading 384 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	130
loop length	520
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.50	8.50	5.67	5.67	5.67	5.67	5.67	5.67	7.75	7.75	7.75	7.75	18.17	17.83	18.00	1.50	1.50
cycles	8.50	8.50	5.67	5.67	5.67	5.67	5.67	5.67	7.75	7.75	7.75	7.75	18.17	17.83	18.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.25
Overall L1	18.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.17 cycles. At this rate:

22% of peak load performance is reached (21.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45b5b8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X11, [X27, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X27, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45b5e0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x718>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45b5f4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [X26, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bb34 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X7, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X15, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45b59c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD D20, D20, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45b5b8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X2, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X28, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X28, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45bcd8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X28, X15, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X28, X28, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45bc00 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bbc8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bb98 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xcd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X5, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D0, D18, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X28, X28, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D1, D26, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D1, [X20, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X28, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D24, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X5, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D2, D25, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X28, X28, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D7, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D3, D7, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D3, [X20, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X28, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D5, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X5, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D31, D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X28, X28, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D4, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D16, D4, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D16, [X20, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X5, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bcd8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X13, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X26, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X13, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X15, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X15, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X11, X28, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45bda0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xed8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bd68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xea0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bd38 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X11, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D23, D21, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X5, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X19, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D30, D27, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D30, [X19, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X15, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D28, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D31, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X11, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D18, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X5, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D17, [X19, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D0, D17, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X19, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X15, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D1, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X11, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D31, D26, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X5, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X19, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D24, D25, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D24, [X19, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X2, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X26, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.10
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 68 paths individually, rerun with max-paths=68
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 25 FP arithmetical operations:

19: addition or subtraction
6: multiply

The binary loop is loading 384 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	130
loop length	520
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.50	8.50	5.67	5.67	5.67	5.67	5.67	5.67	7.75	7.75	7.75	7.75	18.17	17.83	18.00	1.50	1.50
cycles	8.50	8.50	5.67	5.67	5.67	5.67	5.67	5.67	7.75	7.75	7.75	7.75	18.17	17.83	18.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.25
Overall L1	18.17

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.17 cycles. At this rate:

22% of peak load performance is reached (21.14 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 45b5b8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X11, [X27, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X27, X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45b5e0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x718>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45b5f4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [X26, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bb34 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X7, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X15, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X18, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45b59c <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D28, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FADD D20, D20, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 45b5b8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X2, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X28, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X28, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45bcd8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X28, X15, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X28, X28, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45bc00 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bbc8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bb98 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xcd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X5, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D18, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D0, D18, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X28, X28, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D1, D26, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D1, [X20, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X28, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D24, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X5, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D2, D25, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X28, X28, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D7, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D3, D7, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D3, [X20, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X28, [X25, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D5, [X20, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X5, X5, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X28, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D31, D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X28, X28, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D4, [X20, X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D16, D4, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D16, [X20, X28]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X5, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bcd8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X13, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X26, X22, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X13, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X15, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [X15, X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X2, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X11, X28, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X5, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45bda0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xed8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bd68 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xea0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 45bd38 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D22, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X11, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D23, D21, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X5, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D27, [X19, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D30, D27, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D30, [X19, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X15, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D28, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D31, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X11, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D18, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X5, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D17, [X19, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D0, D17, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D0, [X19, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR X15, [X24, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D1, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D26, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X11, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D31, D26, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
UBFM X5, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X19, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D29, D29, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D20, D20, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D24, D25, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D24, [X19, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X2, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X26, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X26, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code