OV - exec - Loop 824

	Loop Id: 824	Module: exec	Source: par_multi_interp.c:939-999 [...]	Coverage: 0.06%

0x4577f0 LDR	X14, [SP, #104]

0x4577f4 LDR	X0, [X14, X15,LSL #3]

0x4577f8 UBFM	X10, X0, #61, #60

0x4577fc ADD	X1, X10, #8

0x457800 STR	X6, [X18, X10]

0x457804 ADD	X4, X12, X1

0x457808 STR	X5, [X16, X10]

0x45780c LDR	X3, [X12, X10]

0x457810 LDR	X8, [X12, X1]

0x457814 CMP	X3, X8

0x457818 B.GE	457b88

0x45781c ORR	X28, XZR, X24

0x457820 STR	X9, [SP, #128]

0x457824 ORR	X9, XZR, X4

0x457828 B	457838

  (827) 0x45782c ADD	X3, X3, #1

  (827) 0x457830 CMP	X3, X8

  (827) 0x457834 B.GE	457b80

  (827) 0x457838 LDR	X24, [X27, X3,LSL #3]

  (827) 0x45783c UBFM	X2, X24, #61, #60

  (827) 0x457840 LDR	X17, [X25, X2]

  (827) 0x457844 STR	X2, [SP, #96]

  (827) 0x457848 CMP	X17, X7

  (827) 0x45784c B.NE	45782c

  (827) 0x457850 ADD	X17, X2, #8

  (827) 0x457854 LDR	X8, [X18, X2]

  (827) 0x457858 LDR	X14, [X23, X17]

  (827) 0x45785c ADD	X4, X8, X14

  (827) 0x457860 CMP	X8, X4

  (827) 0x457864 B.GE	4579e0

  (827) 0x457868 LDR	X24, [SP, #144]

  (827) 0x45786c UBFM	X2, X8, #61, #60

  (827) 0x457870 LDUR	X24, [X24, #504]

  (827) 0x457874 ADD	X14, X24, X4,LSL #3

  (827) 0x457878 ADD	X4, X24, X8,LSL #3

  (827) 0x45787c SUB	X8, X14, X4

  (827) 0x457880 SUB	X8, X8, #8

  (827) 0x457884 UBFM	X8, X8, #3, #63

  (827) 0x457888 ADD	X8, X8, #1

  (827) 0x45788c ANDS	X8, X8, #4160

  (827) 0x457890 B.EQ	457930

  (827) 0x457894 CMP	X8, #1

  (827) 0x457898 B.EQ	4578fc

  (827) 0x45789c CMP	X8, #2

  (827) 0x4578a0 B.EQ	4578d0

  (827) 0x4578a4 LDR	X24, [X24, X2]

  (827) 0x4578a8 UBFM	X2, X24, #61, #60

  (827) 0x4578ac LDR	X8, [X20, X2]

  (827) 0x4578b0 CMP	X0, X8

  (827) 0x4578b4 B.EQ	4578cc

  (827) 0x4578b8 LDR	X24, [X23, X1]

  (827) 0x4578bc ADD	X6, X6, #1

  (827) 0x4578c0 ADD	X8, X24, #1

  (827) 0x4578c4 STR	X8, [X23, X1]

  (827) 0x4578c8 STR	X0, [X20, X2]

  (827) 0x4578cc ADD	X4, X4, #8

  (827) 0x4578d0 LDR	X2, [X4]

  (827) 0x4578d4 UBFM	X8, X2, #61, #60

  (827) 0x4578d8 LDR	X24, [X20, X8]

  (827) 0x4578dc CMP	X0, X24

  (827) 0x4578e0 B.EQ	4578f8

  (827) 0x4578e4 LDR	X2, [X23, X1]

  (827) 0x4578e8 ADD	X6, X6, #1

  (827) 0x4578ec ADD	X24, X2, #1

  (827) 0x4578f0 STR	X24, [X23, X1]

  (827) 0x4578f4 STR	X0, [X20, X8]

  (827) 0x4578f8 ADD	X4, X4, #8

  (827) 0x4578fc LDR	X8, [X4]

  (827) 0x457900 UBFM	X2, X8, #61, #60

  (827) 0x457904 LDR	X24, [X20, X2]

  (827) 0x457908 CMP	X0, X24

  (827) 0x45790c B.EQ	457924

  (827) 0x457910 LDR	X8, [X23, X1]

  (827) 0x457914 ADD	X6, X6, #1

  (827) 0x457918 ADD	X24, X8, #1

  (827) 0x45791c STR	X24, [X23, X1]

  (827) 0x457920 STR	X0, [X20, X2]

  (827) 0x457924 ADD	X4, X4, #8

  (827) 0x457928 CMP	X14, X4

  (827) 0x45792c B.EQ	4579e0

    (829) 0x457930 LDR	X2, [X4]

    (829) 0x457934 ADD	X8, X4, #8

    (829) 0x457938 UBFM	X2, X2, #61, #60

    (829) 0x45793c LDR	X24, [X20, X2]

    (829) 0x457940 CMP	X0, X24

    (829) 0x457944 B.EQ	45795c

    (829) 0x457948 LDR	X24, [X23, X1]

    (829) 0x45794c ADD	X6, X6, #1

    (829) 0x457950 ADD	X24, X24, #1

    (829) 0x457954 STR	X24, [X23, X1]

    (829) 0x457958 STR	X0, [X20, X2]

    (829) 0x45795c LDR	X4, [X4, #8]

    (829) 0x457960 UBFM	X2, X4, #61, #60

    (829) 0x457964 LDR	X24, [X20, X2]

    (829) 0x457968 CMP	X0, X24

    (829) 0x45796c B.EQ	457984

    (829) 0x457970 LDR	X4, [X23, X1]

    (829) 0x457974 ADD	X6, X6, #1

    (829) 0x457978 ADD	X24, X4, #1

    (829) 0x45797c STR	X24, [X23, X1]

    (829) 0x457980 STR	X0, [X20, X2]

    (829) 0x457984 LDR	X2, [X8, #8]

    (829) 0x457988 ADD	X4, X8, #24

    (829) 0x45798c UBFM	X2, X2, #61, #60

    (829) 0x457990 LDR	X24, [X20, X2]

    (829) 0x457994 CMP	X0, X24

    (829) 0x457998 B.EQ	4579b0

    (829) 0x45799c LDR	X24, [X23, X1]

    (829) 0x4579a0 ADD	X6, X6, #1

    (829) 0x4579a4 ADD	X24, X24, #1

    (829) 0x4579a8 STR	X24, [X23, X1]

    (829) 0x4579ac STR	X0, [X20, X2]

    (829) 0x4579b0 LDR	X8, [X8, #16]

    (829) 0x4579b4 UBFM	X2, X8, #61, #60

    (829) 0x4579b8 LDR	X24, [X20, X2]

    (829) 0x4579bc CMP	X0, X24

    (829) 0x4579c0 B.EQ	4579d8

    (829) 0x4579c4 LDR	X8, [X23, X1]

    (829) 0x4579c8 ADD	X6, X6, #1

    (829) 0x4579cc ADD	X24, X8, #1

    (829) 0x4579d0 STR	X24, [X23, X1]

    (829) 0x4579d4 STR	X0, [X20, X2]

    (829) 0x4579d8 CMP	X14, X4

    (829) 0x4579dc B.NE	457930

  (827) 0x4579e0 LDR	X14, [SP, #96]

  (827) 0x4579e4 LDR	X17, [X21, X17]

  (827) 0x4579e8 LDR	X4, [X16, X14]

  (827) 0x4579ec ADD	X2, X4, X17

  (827) 0x4579f0 CMP	X4, X2

  (827) 0x4579f4 B.GE	457b6c

  (827) 0x4579f8 LDUR	X17, [X30, #504]

  (827) 0x4579fc UBFM	X24, X4, #61, #60

  (827) 0x457a00 ADD	X8, X17, X2,LSL #3

  (827) 0x457a04 ADD	X2, X17, X4,LSL #3

  (827) 0x457a08 SUB	X14, X8, X2

  (827) 0x457a0c SUB	X4, X14, #8

  (827) 0x457a10 UBFM	X14, X4, #3, #63

  (827) 0x457a14 ADD	X4, X14, #1

  (827) 0x457a18 ANDS	X14, X4, #4160

  (827) 0x457a1c B.EQ	457abc

  (827) 0x457a20 CMP	X14, #1

  (827) 0x457a24 B.EQ	457a88

  (827) 0x457a28 CMP	X14, #2

  (827) 0x457a2c B.EQ	457a5c

  (827) 0x457a30 LDR	X24, [X17, X24]

  (827) 0x457a34 UBFM	X17, X24, #61, #60

  (827) 0x457a38 LDR	X4, [X19, X17]

  (827) 0x457a3c CMP	X0, X4

  (827) 0x457a40 B.EQ	457a58

  (827) 0x457a44 LDR	X14, [X21, X1]

  (827) 0x457a48 ADD	X5, X5, #1

  (827) 0x457a4c ADD	X24, X14, #1

  (827) 0x457a50 STR	X24, [X21, X1]

  (827) 0x457a54 STR	X0, [X19, X17]

  (827) 0x457a58 ADD	X2, X2, #8

  (827) 0x457a5c LDR	X17, [X2]

  (827) 0x457a60 UBFM	X4, X17, #61, #60

  (827) 0x457a64 LDR	X14, [X19, X4]

  (827) 0x457a68 CMP	X0, X14

  (827) 0x457a6c B.EQ	457a84

  (827) 0x457a70 LDR	X24, [X21, X1]

  (827) 0x457a74 ADD	X5, X5, #1

  (827) 0x457a78 ADD	X17, X24, #1

  (827) 0x457a7c STR	X17, [X21, X1]

  (827) 0x457a80 STR	X0, [X19, X4]

  (827) 0x457a84 ADD	X2, X2, #8

  (827) 0x457a88 LDR	X4, [X2]

  (827) 0x457a8c UBFM	X24, X4, #61, #60

  (827) 0x457a90 LDR	X14, [X19, X24]

  (827) 0x457a94 CMP	X0, X14

  (827) 0x457a98 B.EQ	457ab0

  (827) 0x457a9c LDR	X17, [X21, X1]

  (827) 0x457aa0 ADD	X5, X5, #1

  (827) 0x457aa4 ADD	X4, X17, #1

  (827) 0x457aa8 STR	X4, [X21, X1]

  (827) 0x457aac STR	X0, [X19, X24]

  (827) 0x457ab0 ADD	X2, X2, #8

  (827) 0x457ab4 CMP	X2, X8

  (827) 0x457ab8 B.EQ	457b6c

    (828) 0x457abc LDR	X14, [X2]

    (828) 0x457ac0 ADD	X24, X2, #8

    (828) 0x457ac4 UBFM	X4, X14, #61, #60

    (828) 0x457ac8 LDR	X17, [X19, X4]

    (828) 0x457acc CMP	X0, X17

    (828) 0x457ad0 B.EQ	457ae8

    (828) 0x457ad4 LDR	X14, [X21, X1]

    (828) 0x457ad8 ADD	X5, X5, #1

    (828) 0x457adc ADD	X17, X14, #1

    (828) 0x457ae0 STR	X17, [X21, X1]

    (828) 0x457ae4 STR	X0, [X19, X4]

    (828) 0x457ae8 LDR	X2, [X2, #8]

    (828) 0x457aec UBFM	X14, X2, #61, #60

    (828) 0x457af0 LDR	X4, [X19, X14]

    (828) 0x457af4 CMP	X0, X4

    (828) 0x457af8 B.EQ	457b10

    (828) 0x457afc LDR	X17, [X21, X1]

    (828) 0x457b00 ADD	X5, X5, #1

    (828) 0x457b04 ADD	X2, X17, #1

    (828) 0x457b08 STR	X2, [X21, X1]

    (828) 0x457b0c STR	X0, [X19, X14]

    (828) 0x457b10 LDR	X14, [X24, #8]

    (828) 0x457b14 ADD	X2, X24, #24

    (828) 0x457b18 UBFM	X4, X14, #61, #60

    (828) 0x457b1c LDR	X17, [X19, X4]

    (828) 0x457b20 CMP	X0, X17

    (828) 0x457b24 B.EQ	457b3c

    (828) 0x457b28 LDR	X14, [X21, X1]

    (828) 0x457b2c ADD	X5, X5, #1

    (828) 0x457b30 ADD	X17, X14, #1

    (828) 0x457b34 STR	X17, [X21, X1]

    (828) 0x457b38 STR	X0, [X19, X4]

    (828) 0x457b3c LDR	X24, [X24, #16]

    (828) 0x457b40 UBFM	X4, X24, #61, #60

    (828) 0x457b44 LDR	X14, [X19, X4]

    (828) 0x457b48 CMP	X0, X14

    (828) 0x457b4c B.EQ	457b64

    (828) 0x457b50 LDR	X17, [X21, X1]

    (828) 0x457b54 ADD	X5, X5, #1

    (828) 0x457b58 ADD	X24, X17, #1

    (828) 0x457b5c STR	X24, [X21, X1]

    (828) 0x457b60 STR	X0, [X19, X4]

    (828) 0x457b64 CMP	X2, X8

    (828) 0x457b68 B.NE	457abc

  (827) 0x457b6c LDR	X8, [X9]

  (827) 0x457b70 ADD	X3, X3, #1

  (827) 0x457b74 CMP	X3, X8

  (827) 0x457b78 B.LT	457838

0x457b7c HINT	#0

0x457b80 LDR	X9, [SP, #128]

0x457b84 ORR	X24, XZR, X28

0x457b88 LDR	X3, [X11, X10]

0x457b8c ADD	X10, X11, X1

0x457b90 LDR	X4, [X11, X1]

0x457b94 CMP	X3, X4

0x457b98 B.GE	457cc8

0x457b9c LDP	X14, X28, [SP, #112]

0x457ba0 ORR	X2, XZR, X10

0x457ba4 B	457bb4

  (825) 0x457ba8 ADD	X3, X3, #1

  (825) 0x457bac CMP	X3, X4

  (825) 0x457bb0 B.GE	457cc8

  (825) 0x457bb4 LDR	X17, [X26, X3,LSL #3]

  (825) 0x457bb8 UBFM	X8, X17, #61, #60

  (825) 0x457bbc LDR	X10, [X24, X8]

  (825) 0x457bc0 CMP	X10, X7

  (825) 0x457bc4 B.NE	457ba8

  (825) 0x457bc8 ADD	X17, X14, X8

  (825) 0x457bcc LDR	X8, [X13, X8]

  (825) 0x457bd0 LDR	X10, [X17, #8]

  (825) 0x457bd4 ADD	X10, X8, X10

  (825) 0x457bd8 CMP	X8, X10

  (825) 0x457bdc B.GE	457ba8

  (825) 0x457be0 LDR	X17, [X28, X22]

  (825) 0x457be4 UBFM	X4, X8, #61, #60

  (825) 0x457be8 STR	X4, [SP, #96]

  (825) 0x457bec ADD	X10, X17, X10,LSL #3

  (825) 0x457bf0 ADD	X4, X17, X8,LSL #3

  (825) 0x457bf4 SUB	X8, X10, X4

  (825) 0x457bf8 SUB	X8, X8, #8

  (825) 0x457bfc UBFM	X8, X8, #3, #63

  (825) 0x457c00 ADD	X8, X8, #1

  (825) 0x457c04 ANDS	X8, X8, #4160

  (825) 0x457c08 B.EQ	457f04

  (825) 0x457c0c CMP	X8, #1

  (825) 0x457c10 B.EQ	457c80

  (825) 0x457c14 CMP	X8, #2

  (825) 0x457c18 B.EQ	457c50

  (825) 0x457c1c LDR	X8, [SP, #96]

  (825) 0x457c20 LDR	X17, [X17, X8]

  (825) 0x457c24 TBNZ	X17, #63, 458024

  (825) 0x457c28 UBFM	X8, X17, #61, #60

  (825) 0x457c2c LDR	X17, [X19, X8]

  (825) 0x457c30 CMP	X0, X17

  (825) 0x457c34 B.EQ	457c4c

  (825) 0x457c38 LDR	X17, [X21, X1]

  (825) 0x457c3c ADD	X5, X5, #1

  (825) 0x457c40 ADD	X17, X17, #1

  (825) 0x457c44 STR	X17, [X21, X1]

  (825) 0x457c48 STR	X0, [X19, X8]

  (825) 0x457c4c ADD	X4, X4, #8

  (825) 0x457c50 LDR	X8, [X4]

  (825) 0x457c54 TBNZ	X8, #63, 457ff8

  (825) 0x457c58 UBFM	X8, X8, #61, #60

  (825) 0x457c5c LDR	X17, [X19, X8]

  (825) 0x457c60 CMP	X0, X17

  (825) 0x457c64 B.EQ	457c7c

  (825) 0x457c68 LDR	X17, [X21, X1]

  (825) 0x457c6c ADD	X5, X5, #1

  (825) 0x457c70 ADD	X17, X17, #1

  (825) 0x457c74 STR	X17, [X21, X1]

  (825) 0x457c78 STR	X0, [X19, X8]

  (825) 0x457c7c ADD	X4, X4, #8

  (825) 0x457c80 LDR	X8, [X4]

  (825) 0x457c84 TBNZ	X8, #63, 457fcc

  (825) 0x457c88 UBFM	X8, X8, #61, #60

  (825) 0x457c8c LDR	X17, [X19, X8]

  (825) 0x457c90 CMP	X0, X17

  (825) 0x457c94 B.EQ	457cac

  (825) 0x457c98 LDR	X17, [X21, X1]

  (825) 0x457c9c ADD	X5, X5, #1

  (825) 0x457ca0 ADD	X17, X17, #1

  (825) 0x457ca4 STR	X17, [X21, X1]

  (825) 0x457ca8 STR	X0, [X19, X8]

  (825) 0x457cac ADD	X4, X4, #8

  (825) 0x457cb0 CMP	X4, X10

  (825) 0x457cb4 B.NE	457f04

  (825) 0x457cb8 LDR	X4, [X2]

  (825) 0x457cbc ADD	X3, X3, #1

  (825) 0x457cc0 CMP	X3, X4

  (825) 0x457cc4 B.LT	457bb4

0x457cc8 ADD	X15, X15, #1

0x457ccc CMP	X9, X15

0x457cd0 B.GT	4577f0

    (826) 0x457e4c UBFM	X8, X8, #61, #60

    (826) 0x457e50 LDR	X17, [X19, X8]

    (826) 0x457e54 CMP	X0, X17

    (826) 0x457e58 B.EQ	457e70

    (826) 0x457e5c LDR	X17, [X21, X1]

    (826) 0x457e60 ADD	X5, X5, #1

    (826) 0x457e64 ADD	X17, X17, #1

    (826) 0x457e68 STR	X17, [X21, X1]

    (826) 0x457e6c STR	X0, [X19, X8]

    (826) 0x457e70 LDR	X8, [X4, #8]

    (826) 0x457e74 ADD	X4, X4, #8

    (826) 0x457e78 TBNZ	X8, #63, 457f40

    (826) 0x457e7c UBFM	X8, X8, #61, #60

    (826) 0x457e80 LDR	X17, [X19, X8]

    (826) 0x457e84 CMP	X0, X17

    (826) 0x457e88 B.EQ	457ea0

    (826) 0x457e8c LDR	X17, [X21, X1]

    (826) 0x457e90 ADD	X5, X5, #1

    (826) 0x457e94 ADD	X17, X17, #1

    (826) 0x457e98 STR	X17, [X21, X1]

    (826) 0x457e9c STR	X0, [X19, X8]

    (826) 0x457ea0 LDR	X8, [X4, #8]

    (826) 0x457ea4 TBNZ	X8, #63, 457f70

    (826) 0x457ea8 UBFM	X8, X8, #61, #60

    (826) 0x457eac LDR	X17, [X19, X8]

    (826) 0x457eb0 CMP	X0, X17

    (826) 0x457eb4 B.EQ	457ecc

    (826) 0x457eb8 LDR	X17, [X21, X1]

    (826) 0x457ebc ADD	X5, X5, #1

    (826) 0x457ec0 ADD	X17, X17, #1

    (826) 0x457ec4 STR	X17, [X21, X1]

    (826) 0x457ec8 STR	X0, [X19, X8]

    (826) 0x457ecc LDR	X8, [X4, #16]

    (826) 0x457ed0 TBNZ	X8, #63, 457fa0

    (826) 0x457ed4 UBFM	X8, X8, #61, #60

    (826) 0x457ed8 LDR	X17, [X19, X8]

    (826) 0x457edc CMP	X0, X17

    (826) 0x457ee0 B.EQ	457ef8

    (826) 0x457ee4 LDR	X17, [X21, X1]

    (826) 0x457ee8 ADD	X5, X5, #1

    (826) 0x457eec ADD	X17, X17, #1

    (826) 0x457ef0 STR	X17, [X21, X1]

    (826) 0x457ef4 STR	X0, [X19, X8]

    (826) 0x457ef8 ADD	X4, X4, #24

    (826) 0x457efc CMP	X4, X10

    (826) 0x457f00 B.EQ	457cb8

    (826) 0x457f04 LDR	X8, [X4]

    (826) 0x457f08 TBZ	X8, #63, 457e4c

    (826) 0x457f0c ORN	X8, XZR, X8

    (826) 0x457f10 UBFM	X8, X8, #61, #60

    (826) 0x457f14 LDR	X17, [X20, X8]

    (826) 0x457f18 CMP	X0, X17

    (826) 0x457f1c B.EQ	457e70

    (826) 0x457f20 LDR	X17, [X23, X1]

    (826) 0x457f24 ADD	X6, X6, #1

    (826) 0x457f28 ADD	X4, X4, #8

    (826) 0x457f2c ADD	X17, X17, #1

    (826) 0x457f30 STR	X17, [X23, X1]

    (826) 0x457f34 STR	X0, [X20, X8]

    (826) 0x457f38 LDR	X8, [X4]

    (826) 0x457f3c TBZ	X8, #63, 457e7c

    (826) 0x457f40 ORN	X8, XZR, X8

    (826) 0x457f44 UBFM	X8, X8, #61, #60

    (826) 0x457f48 LDR	X17, [X20, X8]

    (826) 0x457f4c CMP	X0, X17

    (826) 0x457f50 B.EQ	457ea0

    (826) 0x457f54 LDR	X17, [X23, X1]

    (826) 0x457f58 ADD	X6, X6, #1

    (826) 0x457f5c ADD	X17, X17, #1

    (826) 0x457f60 STR	X17, [X23, X1]

    (826) 0x457f64 STR	X0, [X20, X8]

    (826) 0x457f68 LDR	X8, [X4, #8]

    (826) 0x457f6c TBZ	X8, #63, 457ea8

    (826) 0x457f70 ORN	X8, XZR, X8

    (826) 0x457f74 UBFM	X8, X8, #61, #60

    (826) 0x457f78 LDR	X17, [X20, X8]

    (826) 0x457f7c CMP	X0, X17

    (826) 0x457f80 B.EQ	457ecc

    (826) 0x457f84 LDR	X17, [X23, X1]

    (826) 0x457f88 ADD	X6, X6, #1

    (826) 0x457f8c ADD	X17, X17, #1

    (826) 0x457f90 STR	X17, [X23, X1]

    (826) 0x457f94 STR	X0, [X20, X8]

    (826) 0x457f98 LDR	X8, [X4, #16]

    (826) 0x457f9c TBZ	X8, #63, 457ed4

    (826) 0x457fa0 ORN	X8, XZR, X8

    (826) 0x457fa4 UBFM	X8, X8, #61, #60

    (826) 0x457fa8 LDR	X17, [X20, X8]

    (826) 0x457fac CMP	X0, X17

    (826) 0x457fb0 B.EQ	457ef8

    (826) 0x457fb4 LDR	X17, [X23, X1]

    (826) 0x457fb8 ADD	X6, X6, #1

    (826) 0x457fbc ADD	X17, X17, #1

    (826) 0x457fc0 STR	X17, [X23, X1]

    (826) 0x457fc4 STR	X0, [X20, X8]

    (826) 0x457fc8 B	457ef8

  (825) 0x457fcc ORN	X8, XZR, X8

  (825) 0x457fd0 UBFM	X8, X8, #61, #60

  (825) 0x457fd4 LDR	X17, [X20, X8]

  (825) 0x457fd8 CMP	X0, X17

  (825) 0x457fdc B.EQ	457cac

  (825) 0x457fe0 LDR	X17, [X23, X1]

  (825) 0x457fe4 ADD	X6, X6, #1

  (825) 0x457fe8 ADD	X17, X17, #1

  (825) 0x457fec STR	X17, [X23, X1]

  (825) 0x457ff0 STR	X0, [X20, X8]

  (825) 0x457ff4 B	457cac

  (825) 0x457ff8 ORN	X8, XZR, X8

  (825) 0x457ffc UBFM	X8, X8, #61, #60

  (825) 0x458000 LDR	X17, [X20, X8]

  (825) 0x458004 CMP	X0, X17

  (825) 0x458008 B.EQ	457c7c

  (825) 0x45800c LDR	X17, [X23, X1]

  (825) 0x458010 ADD	X6, X6, #1

  (825) 0x458014 ADD	X17, X17, #1

  (825) 0x458018 STR	X17, [X23, X1]

  (825) 0x45801c STR	X0, [X20, X8]

  (825) 0x458020 B	457c7c

  (825) 0x458024 ORN	X8, XZR, X17

  (825) 0x458028 UBFM	X8, X8, #61, #60

  (825) 0x45802c LDR	X17, [X20, X8]

  (825) 0x458030 CMP	X0, X17

  (825) 0x458034 B.EQ	457c4c

  (825) 0x458038 LDR	X17, [X23, X1]

  (825) 0x45803c ADD	X6, X6, #1

  (825) 0x458040 ADD	X17, X17, #1

  (825) 0x458044 STR	X17, [X23, X1]

  (825) 0x458048 STR	X0, [X20, X8]

  (825) 0x45804c B	457c4c

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 939 - 999

--------------------------------------------------------------------------------

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

Coverage (%)	Name	Source Location	Module
►98.04+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.96+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	1.92
Front-end cycles	3.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.92
P7 cycles	1.92
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.83
P13 cycles	3.50
P14 cycles	3.67
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	28.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.04
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P12,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:939-944,par_multi_interp.c:976-976
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.83
CQA cycles if FP arith vectorized	3.83
CQA cycles if fully vectorized	1.92
Front-end cycles	3.50
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.92
P7 cycles	1.92
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.83
P13 cycles	3.50
P14 cycles	3.67
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	28.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.04
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-970,976-999.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:939-944,976.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 1.92 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	2.50	2.50	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

19% of peak load performance is reached (18.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4577f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X10, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X6, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X12, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [X16, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X12, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 457b88 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X9, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 457838 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X3, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X11, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X11, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 457cc8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X2, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 457bb4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X15, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 4577f0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:939-999
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 1.92 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50
cycles	2.50	2.50	2.08	2.08	2.00	2.00	1.92	1.92	0.00	0.00	0.00	0.00	3.83	3.50	3.67	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	3.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

19% of peak load performance is reached (18.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4577f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X14, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X10, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X6, [X18, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X12, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X5, [X16, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X12, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X12, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 457b88 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x55c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X9, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 457838 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X3, [X11, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X11, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X11, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 457cc8 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X2, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 457bb4 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x588>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X15, X15, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 4577f0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code