OV - exec - Loop 816

	Loop Id: 816	Module: exec	Source: par_multi_interp.c:1072-1125	Coverage: 0.07%

0x4582c0 LDR	X21, [SP, #104]

0x4582c4 LDR	X6, [X21, X9,LSL #3]

0x4582c8 UBFM	X15, X6, #61, #60

0x4582cc ORN	X0, XZR, X6

0x4582d0 ADD	X14, X15, #8

0x4582d4 LDR	X3, [X12, X15]

0x4582d8 ADD	X5, X12, X14

0x4582dc LDR	X13, [X12, X14]

0x4582e0 CMP	X3, X13

0x4582e4 B.GE	458648

0x4582e8 ORR	X28, XZR, X24

0x4582ec STR	X6, [SP, #128]

0x4582f0 ORR	X6, XZR, X5

0x4582f4 B	458304

  (819) 0x4582f8 ADD	X3, X3, #1

  (819) 0x4582fc CMP	X3, X13

  (819) 0x458300 B.GE	458640

  (819) 0x458304 LDR	X24, [X27, X3,LSL #3]

  (819) 0x458308 UBFM	X1, X24, #61, #60

  (819) 0x45830c LDR	X16, [X25, X1]

  (819) 0x458310 CMP	X16, X7

  (819) 0x458314 B.NE	4582f8

  (819) 0x458318 LDR	X21, [SP, #152]

  (819) 0x45831c ADD	X16, X1, #8

  (819) 0x458320 LDR	X13, [X23, X16]

  (819) 0x458324 LDR	X5, [X21, X1]

  (819) 0x458328 ADD	X13, X5, X13

  (819) 0x45832c CMP	X5, X13

  (819) 0x458330 B.GE	4584b8

  (819) 0x458334 LDR	X24, [SP, #160]

  (819) 0x458338 UBFM	X21, X5, #61, #60

  (819) 0x45833c STR	X21, [SP, #144]

  (819) 0x458340 LDUR	X24, [X24, #504]

  (819) 0x458344 ADD	X13, X24, X13,LSL #3

  (819) 0x458348 ADD	X5, X24, X5,LSL #3

  (819) 0x45834c SUB	X21, X13, X5

  (819) 0x458350 STR	X13, [SP, #96]

  (819) 0x458354 SUB	X21, X21, #8

  (819) 0x458358 UBFM	X21, X21, #3, #63

  (819) 0x45835c ADD	X21, X21, #1

  (819) 0x458360 ANDS	X21, X21, #4160

  (819) 0x458364 B.EQ	458400

  (819) 0x458368 CMP	X21, #1

  (819) 0x45836c B.EQ	4583cc

  (819) 0x458370 CMP	X21, #2

  (819) 0x458374 B.EQ	4583a4

  (819) 0x458378 LDR	X13, [SP, #144]

  (819) 0x45837c LDR	X24, [X24, X13]

  (819) 0x458380 UBFM	X21, X24, #61, #60

  (819) 0x458384 LDR	X13, [X20, X21]

  (819) 0x458388 CMP	X13, X0

  (819) 0x45838c B.EQ	4583a0

  (819) 0x458390 LDR	X13, [X10, X22]

  (819) 0x458394 STR	X24, [X13, X4,LSL #3]

  (819) 0x458398 ADD	X4, X4, #1

  (819) 0x45839c STR	X0, [X20, X21]

  (819) 0x4583a0 ADD	X5, X5, #8

  (819) 0x4583a4 LDR	X24, [X5]

  (819) 0x4583a8 UBFM	X21, X24, #61, #60

  (819) 0x4583ac LDR	X13, [X20, X21]

  (819) 0x4583b0 CMP	X13, X0

  (819) 0x4583b4 B.EQ	4583c8

  (819) 0x4583b8 LDR	X13, [X10, X22]

  (819) 0x4583bc STR	X24, [X13, X4,LSL #3]

  (819) 0x4583c0 ADD	X4, X4, #1

  (819) 0x4583c4 STR	X0, [X20, X21]

  (819) 0x4583c8 ADD	X5, X5, #8

  (819) 0x4583cc LDR	X24, [X5]

  (819) 0x4583d0 UBFM	X21, X24, #61, #60

  (819) 0x4583d4 LDR	X13, [X20, X21]

  (819) 0x4583d8 CMP	X13, X0

  (819) 0x4583dc B.EQ	4583f0

  (819) 0x4583e0 LDR	X13, [X10, X22]

  (819) 0x4583e4 STR	X24, [X13, X4,LSL #3]

  (819) 0x4583e8 ADD	X4, X4, #1

  (819) 0x4583ec STR	X0, [X20, X21]

  (819) 0x4583f0 LDR	X13, [SP, #96]

  (819) 0x4583f4 ADD	X5, X5, #8

  (819) 0x4583f8 CMP	X13, X5

  (819) 0x4583fc B.EQ	4584b8

  (819) 0x458400 ORR	X24, XZR, X2

  (819) 0x458404 STR	X1, [SP, #96]

  (819) 0x458408 STR	X19, [SP, #144]

    (821) 0x45840c LDR	X21, [X5]

    (821) 0x458410 ADD	X2, X5, #8

    (821) 0x458414 UBFM	X19, X21, #61, #60

    (821) 0x458418 LDR	X1, [X20, X19]

    (821) 0x45841c CMP	X1, X0

    (821) 0x458420 B.EQ	458434

    (821) 0x458424 LDR	X1, [X10, X22]

    (821) 0x458428 STR	X21, [X1, X4,LSL #3]

    (821) 0x45842c ADD	X4, X4, #1

    (821) 0x458430 STR	X0, [X20, X19]

    (821) 0x458434 LDR	X19, [X5, #8]

    (821) 0x458438 UBFM	X5, X19, #61, #60

    (821) 0x45843c LDR	X21, [X20, X5]

    (821) 0x458440 CMP	X21, X0

    (821) 0x458444 B.EQ	458458

    (821) 0x458448 LDR	X1, [X10, X22]

    (821) 0x45844c STR	X19, [X1, X4,LSL #3]

    (821) 0x458450 ADD	X4, X4, #1

    (821) 0x458454 STR	X0, [X20, X5]

    (821) 0x458458 LDR	X21, [X2, #8]

    (821) 0x45845c ADD	X5, X2, #24

    (821) 0x458460 UBFM	X19, X21, #61, #60

    (821) 0x458464 LDR	X1, [X20, X19]

    (821) 0x458468 CMP	X1, X0

    (821) 0x45846c B.EQ	458480

    (821) 0x458470 LDR	X1, [X10, X22]

    (821) 0x458474 STR	X21, [X1, X4,LSL #3]

    (821) 0x458478 ADD	X4, X4, #1

    (821) 0x45847c STR	X0, [X20, X19]

    (821) 0x458480 LDR	X19, [X2, #16]

    (821) 0x458484 UBFM	X2, X19, #61, #60

    (821) 0x458488 LDR	X21, [X20, X2]

    (821) 0x45848c CMP	X21, X0

    (821) 0x458490 B.EQ	4584a4

    (821) 0x458494 LDR	X1, [X10, X22]

    (821) 0x458498 STR	X19, [X1, X4,LSL #3]

    (821) 0x45849c ADD	X4, X4, #1

    (821) 0x4584a0 STR	X0, [X20, X2]

    (821) 0x4584a4 CMP	X13, X5

    (821) 0x4584a8 B.NE	45840c

  (819) 0x4584ac LDR	X1, [SP, #96]

  (819) 0x4584b0 ORR	X2, XZR, X24

  (819) 0x4584b4 LDR	X19, [SP, #144]

  (819) 0x4584b8 LDR	X13, [SP, #136]

  (819) 0x4584bc LDR	X16, [X18, X16]

  (819) 0x4584c0 LDR	X24, [X13, X1]

  (819) 0x4584c4 ADD	X5, X24, X16

  (819) 0x4584c8 CMP	X24, X5

  (819) 0x4584cc B.GE	45862c

  (819) 0x4584d0 LDR	X1, [SP, #168]

  (819) 0x4584d4 UBFM	X21, X24, #61, #60

  (819) 0x4584d8 LDUR	X16, [X1, #504]

  (819) 0x4584dc ADD	X1, X16, X24,LSL #3

  (819) 0x4584e0 ADD	X5, X16, X5,LSL #3

  (819) 0x4584e4 SUB	X13, X5, X1

  (819) 0x4584e8 SUB	X24, X13, #8

  (819) 0x4584ec UBFM	X13, X24, #3, #63

  (819) 0x4584f0 ADD	X24, X13, #1

  (819) 0x4584f4 ANDS	X13, X24, #4160

  (819) 0x4584f8 B.EQ	45858c

  (819) 0x4584fc CMP	X13, #1

  (819) 0x458500 B.EQ	45855c

  (819) 0x458504 CMP	X13, #2

  (819) 0x458508 B.EQ	458534

  (819) 0x45850c LDR	X16, [X16, X21]

  (819) 0x458510 UBFM	X24, X16, #61, #60

  (819) 0x458514 LDR	X21, [X19, X24]

  (819) 0x458518 CMP	X21, X0

  (819) 0x45851c B.EQ	458530

  (819) 0x458520 LDR	X13, [X8, X22]

  (819) 0x458524 STR	X16, [X13, X2,LSL #3]

  (819) 0x458528 ADD	X2, X2, #1

  (819) 0x45852c STR	X0, [X19, X24]

  (819) 0x458530 ADD	X1, X1, #8

  (819) 0x458534 LDR	X16, [X1]

  (819) 0x458538 UBFM	X24, X16, #61, #60

  (819) 0x45853c LDR	X21, [X19, X24]

  (819) 0x458540 CMP	X21, X0

  (819) 0x458544 B.EQ	458558

  (819) 0x458548 LDR	X13, [X8, X22]

  (819) 0x45854c STR	X16, [X13, X2,LSL #3]

  (819) 0x458550 ADD	X2, X2, #1

  (819) 0x458554 STR	X0, [X19, X24]

  (819) 0x458558 ADD	X1, X1, #8

  (819) 0x45855c LDR	X16, [X1]

  (819) 0x458560 UBFM	X24, X16, #61, #60

  (819) 0x458564 LDR	X21, [X19, X24]

  (819) 0x458568 CMP	X21, X0

  (819) 0x45856c B.EQ	458580

  (819) 0x458570 LDR	X13, [X8, X22]

  (819) 0x458574 STR	X16, [X13, X2,LSL #3]

  (819) 0x458578 ADD	X2, X2, #1

  (819) 0x45857c STR	X0, [X19, X24]

  (819) 0x458580 ADD	X1, X1, #8

  (819) 0x458584 CMP	X1, X5

  (819) 0x458588 B.EQ	45862c

    (820) 0x45858c LDR	X21, [X1]

    (820) 0x458590 ADD	X13, X1, #8

    (820) 0x458594 UBFM	X16, X21, #61, #60

    (820) 0x458598 LDR	X24, [X19, X16]

    (820) 0x45859c CMP	X24, X0

    (820) 0x4585a0 B.EQ	4585b4

    (820) 0x4585a4 LDR	X24, [X8, X22]

    (820) 0x4585a8 STR	X21, [X24, X2,LSL #3]

    (820) 0x4585ac ADD	X2, X2, #1

    (820) 0x4585b0 STR	X0, [X19, X16]

    (820) 0x4585b4 LDR	X16, [X1, #8]

    (820) 0x4585b8 UBFM	X1, X16, #61, #60

    (820) 0x4585bc LDR	X21, [X19, X1]

    (820) 0x4585c0 CMP	X21, X0

    (820) 0x4585c4 B.EQ	4585d8

    (820) 0x4585c8 LDR	X24, [X8, X22]

    (820) 0x4585cc STR	X16, [X24, X2,LSL #3]

    (820) 0x4585d0 ADD	X2, X2, #1

    (820) 0x4585d4 STR	X0, [X19, X1]

    (820) 0x4585d8 LDR	X21, [X13, #8]

    (820) 0x4585dc ADD	X1, X13, #24

    (820) 0x4585e0 UBFM	X16, X21, #61, #60

    (820) 0x4585e4 LDR	X24, [X19, X16]

    (820) 0x4585e8 CMP	X24, X0

    (820) 0x4585ec B.EQ	458600

    (820) 0x4585f0 LDR	X24, [X8, X22]

    (820) 0x4585f4 STR	X21, [X24, X2,LSL #3]

    (820) 0x4585f8 ADD	X2, X2, #1

    (820) 0x4585fc STR	X0, [X19, X16]

    (820) 0x458600 LDR	X16, [X13, #16]

    (820) 0x458604 UBFM	X13, X16, #61, #60

    (820) 0x458608 LDR	X21, [X19, X13]

    (820) 0x45860c CMP	X21, X0

    (820) 0x458610 B.EQ	458624

    (820) 0x458614 LDR	X24, [X8, X22]

    (820) 0x458618 STR	X16, [X24, X2,LSL #3]

    (820) 0x45861c ADD	X2, X2, #1

    (820) 0x458620 STR	X0, [X19, X13]

    (820) 0x458624 CMP	X1, X5

    (820) 0x458628 B.NE	45858c

  (819) 0x45862c LDR	X13, [X6]

  (819) 0x458630 ADD	X3, X3, #1

  (819) 0x458634 CMP	X3, X13

  (819) 0x458638 B.LT	458304

0x45863c HINT	#0

0x458640 LDR	X6, [SP, #128]

0x458644 ORR	X24, XZR, X28

0x458648 ORN	X6, XZR, X6

0x45864c LDR	X1, [X11, X15]

0x458650 ADD	X15, X11, X14

0x458654 LDR	X3, [X11, X14]

0x458658 CMP	X3, X1

0x45865c B.LE	458780

0x458660 LDP	X21, X28, [SP, #112]

0x458664 B	458674

  (817) 0x458668 ADD	X1, X1, #1

  (817) 0x45866c CMP	X1, X3

  (817) 0x458670 B.GE	458780

  (817) 0x458674 LDR	X0, [X26, X1,LSL #3]

  (817) 0x458678 UBFM	X14, X0, #61, #60

  (817) 0x45867c LDR	X5, [X24, X14]

  (817) 0x458680 CMP	X5, X7

  (817) 0x458684 B.NE	458668

  (817) 0x458688 ADD	X16, X21, X14

  (817) 0x45868c LDR	X0, [X17, X14]

  (817) 0x458690 LDR	X13, [X16, #8]

  (817) 0x458694 ADD	X5, X0, X13

  (817) 0x458698 CMP	X0, X5

  (817) 0x45869c B.GE	458668

  (817) 0x4586a0 LDR	X16, [X28, X22]

  (817) 0x4586a4 UBFM	X14, X0, #61, #60

  (817) 0x4586a8 ADD	X5, X16, X5,LSL #3

  (817) 0x4586ac ADD	X0, X16, X0,LSL #3

  (817) 0x4586b0 SUB	X3, X5, X0

  (817) 0x4586b4 SUB	X13, X3, #8

  (817) 0x4586b8 UBFM	X3, X13, #3, #63

  (817) 0x4586bc ADD	X13, X3, #1

  (817) 0x4586c0 ANDS	X3, X13, #4160

  (817) 0x4586c4 B.EQ	458848

  (817) 0x4586c8 CMP	X3, #1

  (817) 0x4586cc B.EQ	458730

  (817) 0x4586d0 CMP	X3, #2

  (817) 0x4586d4 B.EQ	458704

  (817) 0x4586d8 LDR	X16, [X16, X14]

  (817) 0x4586dc TBNZ	X16, #63, 45898c

  (817) 0x4586e0 UBFM	X13, X16, #61, #60

  (817) 0x4586e4 LDR	X14, [X19, X13]

  (817) 0x4586e8 CMP	X14, X6

  (817) 0x4586ec B.EQ	458700

  (817) 0x4586f0 LDR	X3, [X8, X22]

  (817) 0x4586f4 STR	X16, [X3, X2,LSL #3]

  (817) 0x4586f8 ADD	X2, X2, #1

  (817) 0x4586fc STR	X6, [X19, X13]

  (817) 0x458700 ADD	X0, X0, #8

  (817) 0x458704 LDR	X3, [X0]

  (817) 0x458708 TBNZ	X3, #63, 458960

  (817) 0x45870c UBFM	X13, X3, #61, #60

  (817) 0x458710 LDR	X14, [X19, X13]

  (817) 0x458714 CMP	X14, X6

  (817) 0x458718 B.EQ	45872c

  (817) 0x45871c LDR	X16, [X8, X22]

  (817) 0x458720 STR	X3, [X16, X2,LSL #3]

  (817) 0x458724 ADD	X2, X2, #1

  (817) 0x458728 STR	X6, [X19, X13]

  (817) 0x45872c ADD	X0, X0, #8

  (817) 0x458730 LDR	X16, [X0]

  (817) 0x458734 TBNZ	X16, #63, 458934

  (817) 0x458738 UBFM	X13, X16, #61, #60

  (817) 0x45873c LDR	X14, [X19, X13]

  (817) 0x458740 CMP	X14, X6

  (817) 0x458744 B.EQ	458758

  (817) 0x458748 LDR	X3, [X8, X22]

  (817) 0x45874c STR	X16, [X3, X2,LSL #3]

  (817) 0x458750 ADD	X2, X2, #1

  (817) 0x458754 STR	X6, [X19, X13]

  (817) 0x458758 ADD	X0, X0, #8

  (817) 0x45875c CMP	X0, X5

  (817) 0x458760 B.NE	458848

  (817) 0x458764 LDR	X3, [X15]

  (817) 0x458768 ADD	X1, X1, #1

  (817) 0x45876c CMP	X1, X3

  (817) 0x458770 B.LT	458674

0x458774 HINT	#0

0x458778 HINT	#0

0x45877c HINT	#0

0x458780 ADD	X9, X9, #1

0x458784 CMP	X30, X9

0x458788 B.GT	4582c0

    (818) 0x4587cc UBFM	X13, X16, #61, #60

    (818) 0x4587d0 LDR	X14, [X19, X13]

    (818) 0x4587d4 CMP	X14, X6

    (818) 0x4587d8 B.EQ	4587ec

    (818) 0x4587dc LDR	X3, [X8, X22]

    (818) 0x4587e0 STR	X16, [X3, X2,LSL #3]

    (818) 0x4587e4 ADD	X2, X2, #1

    (818) 0x4587e8 STR	X6, [X19, X13]

    (818) 0x4587ec LDR	X3, [X0, #8]

    (818) 0x4587f0 TBNZ	X3, #63, 4588ac

    (818) 0x4587f4 UBFM	X13, X3, #61, #60

    (818) 0x4587f8 LDR	X14, [X19, X13]

    (818) 0x4587fc CMP	X14, X6

    (818) 0x458800 B.EQ	458814

    (818) 0x458804 LDR	X16, [X8, X22]

    (818) 0x458808 STR	X3, [X16, X2,LSL #3]

    (818) 0x45880c ADD	X2, X2, #1

    (818) 0x458810 STR	X6, [X19, X13]

    (818) 0x458814 LDR	X16, [X0, #16]

    (818) 0x458818 TBNZ	X16, #63, 4588dc

    (818) 0x45881c UBFM	X13, X16, #61, #60

    (818) 0x458820 LDR	X14, [X19, X13]

    (818) 0x458824 CMP	X14, X6

    (818) 0x458828 B.EQ	45883c

    (818) 0x45882c LDR	X3, [X8, X22]

    (818) 0x458830 STR	X16, [X3, X2,LSL #3]

    (818) 0x458834 ADD	X2, X2, #1

    (818) 0x458838 STR	X6, [X19, X13]

    (818) 0x45883c ADD	X0, X0, #24

    (818) 0x458840 CMP	X0, X5

    (818) 0x458844 B.EQ	458764

    (818) 0x458848 LDR	X3, [X0]

    (818) 0x45884c TBNZ	X3, #63, 458908

    (818) 0x458850 UBFM	X13, X3, #61, #60

    (818) 0x458854 LDR	X14, [X19, X13]

    (818) 0x458858 CMP	X14, X6

    (818) 0x45885c B.EQ	458870

    (818) 0x458860 LDR	X16, [X8, X22]

    (818) 0x458864 STR	X3, [X16, X2,LSL #3]

    (818) 0x458868 ADD	X2, X2, #1

    (818) 0x45886c STR	X6, [X19, X13]

    (818) 0x458870 LDR	X16, [X0, #8]

    (818) 0x458874 ADD	X0, X0, #8

    (818) 0x458878 TBZ	X16, #63, 4587cc

    (818) 0x45887c ORN	X13, XZR, X16

    (818) 0x458880 UBFM	X13, X13, #61, #60

    (818) 0x458884 LDR	X14, [X20, X13]

    (818) 0x458888 CMP	X14, X6

    (818) 0x45888c B.EQ	4587ec

    (818) 0x458890 LDR	X14, [X10, X22]

    (818) 0x458894 ORN	X16, XZR, X16

    (818) 0x458898 STR	X16, [X14, X4,LSL #3]

    (818) 0x45889c ADD	X4, X4, #1

    (818) 0x4588a0 STR	X6, [X20, X13]

    (818) 0x4588a4 LDR	X3, [X0, #8]

    (818) 0x4588a8 TBZ	X3, #63, 4587f4

    (818) 0x4588ac ORN	X13, XZR, X3

    (818) 0x4588b0 UBFM	X16, X13, #61, #60

    (818) 0x4588b4 LDR	X14, [X20, X16]

    (818) 0x4588b8 CMP	X14, X6

    (818) 0x4588bc B.EQ	458814

    (818) 0x4588c0 LDR	X13, [X10, X22]

    (818) 0x4588c4 ORN	X3, XZR, X3

    (818) 0x4588c8 STR	X3, [X13, X4,LSL #3]

    (818) 0x4588cc ADD	X4, X4, #1

    (818) 0x4588d0 STR	X6, [X20, X16]

    (818) 0x4588d4 LDR	X16, [X0, #16]

    (818) 0x4588d8 TBZ	X16, #63, 45881c

    (818) 0x4588dc ORN	X13, XZR, X16

    (818) 0x4588e0 UBFM	X13, X13, #61, #60

    (818) 0x4588e4 LDR	X14, [X20, X13]

    (818) 0x4588e8 CMP	X14, X6

    (818) 0x4588ec B.EQ	45883c

    (818) 0x4588f0 LDR	X14, [X10, X22]

    (818) 0x4588f4 ORN	X16, XZR, X16

    (818) 0x4588f8 STR	X16, [X14, X4,LSL #3]

    (818) 0x4588fc ADD	X4, X4, #1

    (818) 0x458900 STR	X6, [X20, X13]

    (818) 0x458904 B	45883c

    (818) 0x458908 ORN	X13, XZR, X3

    (818) 0x45890c UBFM	X16, X13, #61, #60

    (818) 0x458910 LDR	X14, [X20, X16]

    (818) 0x458914 CMP	X14, X6

    (818) 0x458918 B.EQ	458870

    (818) 0x45891c LDR	X13, [X10, X22]

    (818) 0x458920 ORN	X3, XZR, X3

    (818) 0x458924 STR	X3, [X13, X4,LSL #3]

    (818) 0x458928 ADD	X4, X4, #1

    (818) 0x45892c STR	X6, [X20, X16]

    (818) 0x458930 B	458870

  (817) 0x458934 ORN	X13, XZR, X16

  (817) 0x458938 UBFM	X13, X13, #61, #60

  (817) 0x45893c LDR	X14, [X20, X13]

  (817) 0x458940 CMP	X14, X6

  (817) 0x458944 B.EQ	458758

  (817) 0x458948 LDR	X14, [X10, X22]

  (817) 0x45894c ORN	X16, XZR, X16

  (817) 0x458950 STR	X16, [X14, X4,LSL #3]

  (817) 0x458954 ADD	X4, X4, #1

  (817) 0x458958 STR	X6, [X20, X13]

  (817) 0x45895c B	458758

  (817) 0x458960 ORN	X13, XZR, X3

  (817) 0x458964 UBFM	X16, X13, #61, #60

  (817) 0x458968 LDR	X14, [X20, X16]

  (817) 0x45896c CMP	X14, X6

  (817) 0x458970 B.EQ	45872c

  (817) 0x458974 LDR	X13, [X10, X22]

  (817) 0x458978 ORN	X3, XZR, X3

  (817) 0x45897c STR	X3, [X13, X4,LSL #3]

  (817) 0x458980 ADD	X4, X4, #1

  (817) 0x458984 STR	X6, [X20, X16]

  (817) 0x458988 B	45872c

  (817) 0x45898c ORN	X13, XZR, X16

  (817) 0x458990 UBFM	X13, X13, #61, #60

  (817) 0x458994 LDR	X14, [X20, X13]

  (817) 0x458998 CMP	X14, X6

  (817) 0x45899c B.EQ	458700

  (817) 0x4589a0 LDR	X14, [X10, X22]

  (817) 0x4589a4 ORN	X16, XZR, X16

  (817) 0x4589a8 STR	X16, [X14, X4,LSL #3]

  (817) 0x4589ac ADD	X4, X4, #1

  (817) 0x4589b0 STR	X6, [X20, X13]

  (817) 0x4589b4 B	458700

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1072 - 1125

--------------------------------------------------------------------------------

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module
►98.73+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.27+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:891	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	3.38
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	1.69
Front-end cycles	3.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.17
P13 cycles	2.83
P14 cycles	3.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.70
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source	par_multi_interp.c:1072-1075,par_multi_interp.c:1104-1104,par_multi_interp.c:1122-1122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.38
CQA cycles if no scalar integer	3.38
CQA cycles if FP arith vectorized	3.38
CQA cycles if fully vectorized	1.69
Front-end cycles	3.38
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	3.17
P13 cycles	2.83
P14 cycles	3.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	27.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.70
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1125.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1072-1075,1104,1122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 1.69 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	2.50	2.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4582c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X15, X6, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORN X0, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X5, X12, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X13, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 458648 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x101c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X6, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 458304 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X24, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORN X6, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X15, X11, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 458780 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 458674 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X30, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 4582c0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.5
Source file and lines	par_multi_interp.c:1072-1125
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 1.69 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

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Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50
cycles	2.50	2.50	2.25	2.25	2.17	2.17	2.08	2.08	0.00	0.00	0.00	0.00	3.17	2.83	3.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.38
Overall L1	3.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.38 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4582c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X21, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X15, X6, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORN X0, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X5, X12, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X13, [X12, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 458648 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x101c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X28, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X6, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 458304 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xcd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X24, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORN X6, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [X11, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X15, X11, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X3, [X11, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X3, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 458780 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 458674 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X30, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 4582c0 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0xc94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code