OV - exec - Loop 3802

0x5195a4 SDIV	X13, X1, X25

0x5195a8 ADD	X4, X1, #1

0x5195ac ADD	X6, X1, #2

0x5195b0 ADD	X5, X1, #3

0x5195b4 SDIV	X7, X4, X25

0x5195b8 SDIV	X15, X6, X25

0x5195bc MSUB	X9, X13, X25, X1

0x5195c0 ADD	X1, X1, #4

0x5195c4 SDIV	X11, X5, X25

0x5195c8 MADD	X18, X9, X27, X13

0x5195cc MSUB	X3, X7, X25, X4

0x5195d0 MSUB	X14, X15, X25, X6

0x5195d4 UBFM	X8, X18, #61, #60

0x5195d8 LDR	X10, [X20, X8]    [1]

0x5195dc MADD	X0, X3, X27, X7

0x5195e0 MADD	X2, X14, X27, X15

0x5195e4 MSUB	X5, X11, X25, X5

0x5195e8 UBFM	X30, X0, #61, #60

0x5195ec UBFM	X13, X2, #61, #60

0x5195f0 ADD	X12, X10, X17

0x5195f4 MADD	X7, X5, X27, X11

0x5195f8 STR	X12, [X20, X8]    [1]

0x5195fc LDR	X4, [X20, X30]    [1]

0x519600 UBFM	X9, X7, #61, #60

0x519604 ADD	X6, X4, X17

0x519608 STR	X6, [X20, X30]    [1]

0x51960c LDR	X15, [X20, X13]    [1]

0x519610 ADD	X3, X15, X17

0x519614 STR	X3, [X20, X13]    [1]

0x519618 LDR	X18, [X20, X9]    [1]

0x51961c ADD	X0, X18, X17

0x519620 STR	X0, [X20, X9]    [1]

0x519624 CMP	X1, X16

0x519628 B.NE	5195a4

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 527

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

524:      for (i = my_thread_num*num_colsA; i < (my_thread_num + 1)*num_colsA - 1; ++i) {

525:        HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

526:

527:        bucket[transpose_i] += offset;

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67 - 6.67
Bottlenecks	P8, P10,
Function	hypre_CSRMatrixTranspose._omp_fn.0
Source	csr_matop.c:380-380,csr_matop.c:524-527
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00 - 80.00
CQA cycles if no scalar integer	20.00 - 80.00
CQA cycles if FP arith vectorized	20.00 - 80.00
CQA cycles if fully vectorized	10.00 - 40.00
Front-end cycles	4.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.67
P3 cycles	2.58
P4 cycles	2.67
P5 cycles	2.50
P6 cycles	12.00
P7 cycles	2.58
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	2.67
P13 cycles	2.67
P14 cycles	2.67
P15 cycles	2.00
P16 cycles	2.00
DIV/SQRT cycles	20.00 - 80.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.80 - 3.20
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.67 - 6.67
Bottlenecks	P8, P10,
Function	hypre_CSRMatrixTranspose._omp_fn.0
Source	csr_matop.c:380-380,csr_matop.c:524-527
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00 - 80.00
CQA cycles if no scalar integer	20.00 - 80.00
CQA cycles if FP arith vectorized	20.00 - 80.00
CQA cycles if fully vectorized	10.00 - 40.00
Front-end cycles	4.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.67
P3 cycles	2.58
P4 cycles	2.67
P5 cycles	2.50
P6 cycles	12.00
P7 cycles	2.58
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	2.67
P13 cycles	2.67
P14 cycles	2.67
P15 cycles	2.00
P16 cycles	2.00
DIV/SQRT cycles	20.00 - 80.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	34.00
Nb uops	34.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.80 - 3.20
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	1.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixTranspose._omp_fn.0
Source file and lines	csr_matop.c:380-527
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,524-527.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 80.00 to 40.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.67	2.58	2.67	2.50	12.00	2.58	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00
cycles	0.50	0.50	2.67	2.58	2.67	2.50	12.00	2.58	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	20.00-80.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Data deps.	1.00
Overall L1	20.00-80.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 80.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 5195a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SDIV X13, X1, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
ADD X4, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, X1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X7, X4, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
SDIV X15, X6, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X9, X13, X25, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X1, X1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X11, X5, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MADD X18, X9, X27, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MSUB X3, X7, X25, X4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MSUB X14, X15, X25, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X8, X18, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X10, [X20, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X0, X3, X27, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X2, X14, X27, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MSUB X5, X11, X25, X5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X30, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X13, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X12, X10, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X7, X5, X27, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
STR X12, [X20, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X20, X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X9, X7, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X6, X4, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X6, [X20, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X20, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X3, X15, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X3, [X20, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [X20, X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X18, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X0, [X20, X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X1, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 5195a4 <hypre_CSRMatrixTranspose._omp_fn.0+0x71c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixTranspose._omp_fn.0
Source file and lines	csr_matop.c:380-527
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,524-527.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 80.00 to 40.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	34
loop length	136
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.67	2.58	2.67	2.50	12.00	2.58	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00
cycles	0.50	0.50	2.67	2.58	2.67	2.50	12.00	2.58	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	20.00-80.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.25
Data deps.	1.00
Overall L1	20.00-80.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 80.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 5195a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SDIV X13, X1, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	N/A
ADD X4, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X6, X1, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X1, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X7, X4, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
SDIV X15, X6, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X9, X13, X25, X1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X1, X1, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X11, X5, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MADD X18, X9, X27, X13	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MSUB X3, X7, X25, X4	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MSUB X14, X15, X25, X6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X8, X18, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X10, [X20, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X0, X3, X27, X7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X2, X14, X27, X15	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
MSUB X5, X11, X25, X5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X30, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
UBFM X13, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X12, X10, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X7, X5, X27, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (50.0%)
STR X12, [X20, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X20, X30]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X9, X7, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X6, X4, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X6, [X20, X30]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X20, X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X3, X15, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X3, [X20, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [X20, X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X18, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X0, [X20, X9]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X1, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 5195a4 <hypre_CSRMatrixTranspose._omp_fn.0+0x71c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code