OV - exec - Loop 3559

	Loop Id: 3559	Module: exec	Source: IJMatrix_parcsr.c:3240-3500 [...]	Coverage: 0.01%

0x506800 LDR	X30, [SP, #136]

0x506804 LDP	X16, X17, [SP, #120]

0x506808 LDR	X3, [X30]

0x50680c LDR	X25, [X17, X27,LSL #3]

0x506810 LDR	X12, [X16, X27,LSL #3]

0x506814 CMP	X25, X3

0x506818 B.LT	506bd8

0x50681c LDR	X1, [X18]

0x506820 CMP	X25, X1

0x506824 B.GE	506bd8

0x506828 LDR	X16, [SP, #176]

0x50682c SUB	X30, X25, X3

0x506830 UBFM	X13, X30, #61, #60

0x506834 CBNZ	X16, 506f18

0x506bd8 LDR	X2, [SP, #144]

0x506bdc CBNZ	X2, 506c10

  (3560) 0x506be0 ADD	X21, X21, X12

  (3560) 0x506be4 LDR	X12, [SP, #104]

  (3560) 0x506be8 ADD	X27, X27, #1

  (3560) 0x506bec CMP	X12, X27

  (3560) 0x506bf0 B.NE	506800

  (3560) 0x506bf4 LDP	X19, X20, [SP, #16]

  (3560) 0x506bf8 LDP	X21, X22, [SP, #32]

  (3560) 0x506bfc LDP	X23, X24, [SP, #48]

  (3560) 0x506c00 LDP	X25, X26, [SP, #64]

  (3560) 0x506c04 LDP	X27, X28, [SP, #80]

  (3560) 0x506c08 LDP	X29, X30, [SP], #336

  (3560) 0x506c0c RET

  (3560) 0x506c10 LDR	X10, [SP, #152]

  (3560) 0x506c14 CMP	X10, #0

  (3560) 0x506c18 B.LE	506be0

  (3560) 0x506c1c LDP	X2, X0, [SP, #160]

  (3560) 0x506c20 ADD	X15, X28, X12,LSL #3

  (3560) 0x506c24 MOVZ	X14, #0

  (3560) 0x506c28 B	506c38

    (3561) 0x506c2c ADD	X2, X2, #16

    (3561) 0x506c30 CMP	X2, X4

    (3561) 0x506c34 B.EQ	506be0

    (3561) 0x506c38 LDP	X13, X16, [X2]

    (3561) 0x506c3c ORR	X6, XZR, X14

    (3561) 0x506c40 ADD	X14, X14, X16

    (3561) 0x506c44 CMP	X25, X13

    (3561) 0x506c48 B.NE	506c2c

    (3561) 0x506c4c CMP	X12, #0

    (3561) 0x506c50 B.LE	506c2c

    (3561) 0x506c54 CMP	X16, #0

    (3561) 0x506c58 B.LE	506c2c

    (3561) 0x506c5c ADD	X10, X0, X6,LSL #3

    (3561) 0x506c60 ORR	X3, XZR, X28

    (3561) 0x506c64 ADD	X6, X0, X14,LSL #3

      (3563) 0x506c68 SUB	X30, X6, X10

      (3563) 0x506c6c ORR	X1, XZR, X10

      (3563) 0x506c70 SUB	X13, X30, #8

      (3563) 0x506c74 UBFM	X16, X13, #3, #63

      (3563) 0x506c78 ADD	X17, X16, #1

      (3563) 0x506c7c ANDS	X30, X17, #4224

      (3563) 0x506c80 B.EQ	506d58

      (3563) 0x506c84 CMP	X30, #1

      (3563) 0x506c88 B.EQ	506d2c

      (3563) 0x506c8c CMP	X30, #2

      (3563) 0x506c90 B.EQ	506d18

      (3563) 0x506c94 CMP	X30, #3

      (3563) 0x506c98 B.EQ	506d04

      (3563) 0x506c9c CMP	X30, #4

      (3563) 0x506ca0 B.EQ	506cf0

      (3563) 0x506ca4 CMP	X30, #5

      (3563) 0x506ca8 B.EQ	506cdc

      (3563) 0x506cac CMP	X30, #6

      (3563) 0x506cb0 B.EQ	506cc8

      (3563) 0x506cb4 LDR	X13, [X3]

      (3563) 0x506cb8 LDR	X1, [X10]

      (3563) 0x506cbc CMP	X13, X1

      (3563) 0x506cc0 B.EQ	506edc

      (3563) 0x506cc4 ADD	X1, X10, #8

      (3563) 0x506cc8 LDR	X30, [X1]

      (3563) 0x506ccc LDR	X13, [X3]

      (3563) 0x506cd0 CMP	X13, X30

      (3563) 0x506cd4 B.EQ	506ec8

      (3563) 0x506cd8 ADD	X1, X1, #8

      (3563) 0x506cdc LDR	X30, [X1]

      (3563) 0x506ce0 LDR	X13, [X3]

      (3563) 0x506ce4 CMP	X13, X30

      (3563) 0x506ce8 B.EQ	506eb4

      (3563) 0x506cec ADD	X1, X1, #8

      (3563) 0x506cf0 LDR	X30, [X1]

      (3563) 0x506cf4 LDR	X13, [X3]

      (3563) 0x506cf8 CMP	X13, X30

      (3563) 0x506cfc B.EQ	506ea0

      (3563) 0x506d00 ADD	X1, X1, #8

      (3563) 0x506d04 LDR	X30, [X1]

      (3563) 0x506d08 LDR	X13, [X3]

      (3563) 0x506d0c CMP	X13, X30

      (3563) 0x506d10 B.EQ	506e8c

      (3563) 0x506d14 ADD	X1, X1, #8

      (3563) 0x506d18 LDR	X30, [X1]

      (3563) 0x506d1c LDR	X13, [X3]

      (3563) 0x506d20 CMP	X13, X30

      (3563) 0x506d24 B.EQ	506e78

      (3563) 0x506d28 ADD	X1, X1, #8

      (3563) 0x506d2c LDR	X30, [X1]

      (3563) 0x506d30 LDR	X13, [X3]

      (3563) 0x506d34 CMP	X13, X30

      (3563) 0x506d38 B.NE	506d4c

      (3563) 0x506d3c STR	X22, [X1]

      (3563) 0x506d40 LDR	X16, [X20, X19]

      (3563) 0x506d44 ADD	X17, X16, #1

      (3563) 0x506d48 STR	X17, [X20, X19]

      (3563) 0x506d4c ADD	X1, X1, #8

      (3563) 0x506d50 CMP	X1, X6

      (3563) 0x506d54 B.EQ	506e68

        (3562) 0x506d58 LDR	X30, [X1]

        (3562) 0x506d5c LDR	X13, [X3]

        (3562) 0x506d60 CMP	X13, X30

        (3562) 0x506d64 B.NE	506d78

        (3562) 0x506d68 STR	X22, [X1]

        (3562) 0x506d6c LDR	X16, [X20, X19]

        (3562) 0x506d70 ADD	X17, X16, #1

        (3562) 0x506d74 STR	X17, [X20, X19]

        (3562) 0x506d78 LDR	X16, [X3]

        (3562) 0x506d7c ADD	X30, X1, #8

        (3562) 0x506d80 LDR	X13, [X1, #8]

        (3562) 0x506d84 CMP	X16, X13

        (3562) 0x506d88 B.NE	506d9c

        (3562) 0x506d8c STR	X22, [X1, #8]

        (3562) 0x506d90 LDR	X1, [X20, X19]

        (3562) 0x506d94 ADD	X17, X1, #1

        (3562) 0x506d98 STR	X17, [X20, X19]

        (3562) 0x506d9c LDR	X13, [X3]

        (3562) 0x506da0 LDR	X16, [X30, #8]

        (3562) 0x506da4 CMP	X13, X16

        (3562) 0x506da8 B.NE	506dbc

        (3562) 0x506dac STR	X22, [X30, #8]

        (3562) 0x506db0 LDR	X1, [X20, X19]

        (3562) 0x506db4 ADD	X17, X1, #1

        (3562) 0x506db8 STR	X17, [X20, X19]

        (3562) 0x506dbc LDR	X13, [X3]

        (3562) 0x506dc0 LDR	X16, [X30, #16]

        (3562) 0x506dc4 CMP	X13, X16

        (3562) 0x506dc8 B.NE	506ddc

        (3562) 0x506dcc STR	X22, [X30, #16]

        (3562) 0x506dd0 LDR	X1, [X20, X19]

        (3562) 0x506dd4 ADD	X17, X1, #1

        (3562) 0x506dd8 STR	X17, [X20, X19]

        (3562) 0x506ddc LDR	X13, [X3]

        (3562) 0x506de0 LDR	X16, [X30, #24]

        (3562) 0x506de4 CMP	X13, X16

        (3562) 0x506de8 B.NE	506dfc

        (3562) 0x506dec STR	X22, [X30, #24]

        (3562) 0x506df0 LDR	X1, [X20, X19]

        (3562) 0x506df4 ADD	X17, X1, #1

        (3562) 0x506df8 STR	X17, [X20, X19]

        (3562) 0x506dfc LDR	X13, [X3]

        (3562) 0x506e00 LDR	X16, [X30, #32]

        (3562) 0x506e04 CMP	X13, X16

        (3562) 0x506e08 B.NE	506e1c

        (3562) 0x506e0c STR	X22, [X30, #32]

        (3562) 0x506e10 LDR	X1, [X20, X19]

        (3562) 0x506e14 ADD	X17, X1, #1

        (3562) 0x506e18 STR	X17, [X20, X19]

        (3562) 0x506e1c LDR	X13, [X3]

        (3562) 0x506e20 LDR	X16, [X30, #40]

        (3562) 0x506e24 CMP	X13, X16

        (3562) 0x506e28 B.NE	506e3c

        (3562) 0x506e2c STR	X22, [X30, #40]

        (3562) 0x506e30 LDR	X1, [X20, X19]

        (3562) 0x506e34 ADD	X17, X1, #1

        (3562) 0x506e38 STR	X17, [X20, X19]

        (3562) 0x506e3c LDR	X13, [X3]

        (3562) 0x506e40 LDR	X16, [X30, #48]

        (3562) 0x506e44 CMP	X13, X16

        (3562) 0x506e48 B.NE	506e5c

        (3562) 0x506e4c STR	X22, [X30, #48]

        (3562) 0x506e50 LDR	X1, [X20, X19]

        (3562) 0x506e54 ADD	X17, X1, #1

        (3562) 0x506e58 STR	X17, [X20, X19]

        (3562) 0x506e5c ADD	X1, X30, #56

        (3562) 0x506e60 CMP	X1, X6

        (3562) 0x506e64 B.NE	506d58

      (3563) 0x506e68 ADD	X3, X3, #8

      (3563) 0x506e6c CMP	X3, X15

      (3563) 0x506e70 B.NE	506c68

    (3561) 0x506e74 B	506c2c

      (3563) 0x506e78 STR	X22, [X1]

      (3563) 0x506e7c LDR	X16, [X20, X19]

      (3563) 0x506e80 ADD	X17, X16, #1

      (3563) 0x506e84 STR	X17, [X20, X19]

      (3563) 0x506e88 B	506d28

      (3563) 0x506e8c STR	X22, [X1]

      (3563) 0x506e90 LDR	X16, [X20, X19]

      (3563) 0x506e94 ADD	X17, X16, #1

      (3563) 0x506e98 STR	X17, [X20, X19]

      (3563) 0x506e9c B	506d14

      (3563) 0x506ea0 STR	X22, [X1]

      (3563) 0x506ea4 LDR	X16, [X20, X19]

      (3563) 0x506ea8 ADD	X17, X16, #1

      (3563) 0x506eac STR	X17, [X20, X19]

      (3563) 0x506eb0 B	506d00

      (3563) 0x506eb4 STR	X22, [X1]

      (3563) 0x506eb8 LDR	X16, [X20, X19]

      (3563) 0x506ebc ADD	X17, X16, #1

      (3563) 0x506ec0 STR	X17, [X20, X19]

      (3563) 0x506ec4 B	506cec

      (3563) 0x506ec8 STR	X22, [X1]

      (3563) 0x506ecc LDR	X16, [X20, X19]

      (3563) 0x506ed0 ADD	X17, X16, #1

      (3563) 0x506ed4 STR	X17, [X20, X19]

      (3563) 0x506ed8 B	506cd8

      (3563) 0x506edc STR	X22, [X10]

      (3563) 0x506ee0 LDR	X16, [X20, X19]

      (3563) 0x506ee4 ADD	X17, X16, #1

      (3563) 0x506ee8 STR	X17, [X20, X19]

      (3563) 0x506eec B	506cc4

0x506f18 LDR	X2, [SP, #184]

0x506f1c LDR	X15, [SP, #216]

0x506f20 LDR	X14, [SP, #200]

0x506f24 LDR	X2, [X2, X13]

0x506f28 LDR	X10, [X15, X13]

0x506f2c LDR	X16, [SP, #208]

0x506f30 LDR	X6, [X14, X13]

0x506f34 SUB	X3, X10, X2

0x506f38 LDR	X25, [X16, X13]

0x506f3c CMP	X12, X3

0x506f40 B.GT	50741c

0x506f44 CMP	X12, #0

0x506f48 B.LE	506be4

0x506f4c MOVZ	X3, #0

0x506f50 MOVZ	X14, #0

0x506f54 ADD	X12, X21, X12

0x506f58 ORR	X15, XZR, X2

0x506f5c HINT	#0

  (3564) 0x506f60 LDR	X1, [X28, X21,LSL #3]

  (3564) 0x506f64 CMP	X2, #0

  (3564) 0x506f68 B.LE	5070ac

    (3567) 0x506f6c ANDS	X17, X2, #4224

    (3567) 0x506f70 MOVZ	X0, #0

    (3567) 0x506f74 B.EQ	507020

    (3567) 0x506f78 CMP	X17, #1

    (3567) 0x506f7c B.EQ	507008

    (3567) 0x506f80 CMP	X17, #2

    (3567) 0x506f84 B.EQ	506ff8

    (3567) 0x506f88 CMP	X17, #3

    (3567) 0x506f8c B.EQ	506fe8

    (3567) 0x506f90 CMP	X17, #4

    (3567) 0x506f94 B.EQ	506fd8

    (3567) 0x506f98 CMP	X17, #5

    (3567) 0x506f9c B.EQ	506fc8

    (3567) 0x506fa0 CMP	X17, #6

    (3567) 0x506fa4 B.EQ	506fb8

    (3567) 0x506fa8 LDR	X30, [X25]

    (3567) 0x506fac CMP	X30, X1

    (3567) 0x506fb0 B.EQ	507128

    (3567) 0x506fb4 MOVZ	X0, #1

    (3567) 0x506fb8 LDR	X16, [X25, X0,LSL #3]

    (3567) 0x506fbc CMP	X16, X1

    (3567) 0x506fc0 B.EQ	507128

    (3567) 0x506fc4 ADD	X0, X0, #1

    (3567) 0x506fc8 LDR	X17, [X25, X0,LSL #3]

    (3567) 0x506fcc CMP	X17, X1

    (3567) 0x506fd0 B.EQ	507128

    (3567) 0x506fd4 ADD	X0, X0, #1

    (3567) 0x506fd8 LDR	X30, [X25, X0,LSL #3]

    (3567) 0x506fdc CMP	X30, X1

    (3567) 0x506fe0 B.EQ	507128

    (3567) 0x506fe4 ADD	X0, X0, #1

    (3567) 0x506fe8 LDR	X16, [X25, X0,LSL #3]

    (3567) 0x506fec CMP	X16, X1

    (3567) 0x506ff0 B.EQ	507128

    (3567) 0x506ff4 ADD	X0, X0, #1

    (3567) 0x506ff8 LDR	X17, [X25, X0,LSL #3]

    (3567) 0x506ffc CMP	X17, X1

    (3567) 0x507000 B.EQ	507128

    (3567) 0x507004 ADD	X0, X0, #1

    (3567) 0x507008 LDR	X30, [X25, X0,LSL #3]

    (3567) 0x50700c CMP	X30, X1

    (3567) 0x507010 B.EQ	507128

    (3567) 0x507014 ADD	X0, X0, #1

    (3567) 0x507018 CMP	X2, X0

    (3567) 0x50701c B.EQ	5070ac

      (3568) 0x507020 LDR	X16, [X25, X0,LSL #3]

      (3568) 0x507024 CMP	X16, X1

      (3568) 0x507028 B.EQ	507128

      (3568) 0x50702c ADD	X0, X0, #1

      (3568) 0x507030 LDR	X17, [X25, X0,LSL #3]

      (3568) 0x507034 ORR	X30, XZR, X0

      (3568) 0x507038 CMP	X17, X1

      (3568) 0x50703c B.EQ	507128

      (3568) 0x507040 ADD	X0, X0, #1

      (3568) 0x507044 LDR	X16, [X25, X0,LSL #3]

      (3568) 0x507048 CMP	X16, X1

      (3568) 0x50704c B.EQ	507128

      (3568) 0x507050 ADD	X0, X30, #2

      (3568) 0x507054 LDR	X17, [X25, X0,LSL #3]

      (3568) 0x507058 CMP	X17, X1

      (3568) 0x50705c B.EQ	507128

      (3568) 0x507060 ADD	X0, X30, #3

      (3568) 0x507064 LDR	X16, [X25, X0,LSL #3]

      (3568) 0x507068 CMP	X16, X1

      (3568) 0x50706c B.EQ	507128

      (3568) 0x507070 ADD	X0, X30, #4

      (3568) 0x507074 LDR	X17, [X25, X0,LSL #3]

      (3568) 0x507078 CMP	X17, X1

      (3568) 0x50707c B.EQ	507128

      (3568) 0x507080 ADD	X0, X30, #5

      (3568) 0x507084 LDR	X16, [X25, X0,LSL #3]

      (3568) 0x507088 CMP	X16, X1

      (3568) 0x50708c B.EQ	507128

      (3568) 0x507090 ADD	X0, X30, #6

      (3568) 0x507094 LDR	X17, [X25, X0,LSL #3]

      (3568) 0x507098 CMP	X17, X1

      (3568) 0x50709c B.EQ	507128

      (3568) 0x5070a0 ADD	X0, X30, #7

      (3568) 0x5070a4 CMP	X2, X0

      (3568) 0x5070a8 B.NE	507020

  (3564) 0x5070ac LDR	D3, [X26, X21,LSL #3]

  (3564) 0x5070b0 CMP	X10, X15

  (3564) 0x5070b4 B.LE	507144

  (3564) 0x5070b8 UBFM	X16, X15, #61, #60

  (3564) 0x5070bc ADD	X15, X15, #1

  (3564) 0x5070c0 STR	X1, [X25, X16]

  (3564) 0x5070c4 STR	D3, [X6, X16]

  (3564) 0x5070c8 ADD	X21, X21, #1

  (3564) 0x5070cc CMP	X21, X12

  (3564) 0x5070d0 B.NE	506f60

0x5070d4 LDR	X1, [SP, #184]

0x5070d8 ADD	X21, X15, X14

0x5070dc STR	X21, [X1, X13]

0x5070e0 CBNZ	X14, 5071c4

0x5070e4 ORR	X21, XZR, X12

0x5070e8 CBZ	X3, 506be4

0x5070ec ORR	X0, XZR, X3

0x5070f0 STR	X12, [SP, #112]

0x5070f4 STP	X9, X5, [SP, #240]

0x5070f8 STP	X11, X7, [SP, #256]

0x5070fc STR	X8, [SP, #272]

0x507100 STP	X18, X4, [SP, #288]

0x507104 BL	52b3a0

0x507108 LDR	X0, [SP, #240]

0x50710c BL	52b3a0

0x507110 LDR	X21, [SP, #112]

0x507114 MOVZ	X9, #0

0x507118 LDP	X5, X11, [SP, #248]

0x50711c LDP	X7, X8, [SP, #264]

0x507120 LDP	X18, X4, [SP, #288]

0x507124 B	506be4

    (3567) 0x507128 LDR	D4, [X26, X21,LSL #3]

    (3567) 0x50712c ADD	X21, X21, #1

    (3567) 0x507130 STR	D4, [X6, X0,LSL #3]

    (3567) 0x507134 CMP	X21, X12

    (3567) 0x507138 B.EQ	5070d4

    (3567) 0x50713c LDR	X1, [X28, X21,LSL #3]

    (3567) 0x507140 B	506f6c

  (3564) 0x507144 UBFM	X30, X14, #61, #60

  (3564) 0x507148 ADD	X14, X14, #1

  (3564) 0x50714c STR	X1, [X3, X30]

  (3564) 0x507150 STR	D3, [X9, X30]

  (3564) 0x507154 B	5070c8

0x5071c4 LDR	X6, [SP, #208]

0x5071c8 UBFM	X25, X21, #61, #60

0x5071cc ORR	X1, XZR, X25

0x5071d0 STR	X13, [SP, #112]

0x5071d4 STR	X9, [SP, #272]

0x5071d8 LDR	X0, [X6, X13]

0x5071dc STP	X12, X15, [SP, #240]

0x5071e0 STP	X14, X3, [SP, #256]

0x5071e4 STP	X5, X11, [SP, #288]

0x5071e8 STP	X7, X8, [SP, #304]

0x5071ec STP	X18, X4, [SP, #320]

0x5071f0 BL	52b348

0x5071f4 LDR	X3, [SP, #112]

0x5071f8 ORR	X1, XZR, X25

0x5071fc ORR	X9, XZR, X0

0x507200 LDP	X10, X25, [SP, #200]

0x507204 LDR	X0, [X10, X3]

0x507208 STR	X9, [X25, X3]

0x50720c BL	52b348

0x507210 LDR	X2, [SP, #112]

0x507214 ORR	X30, XZR, X0

0x507218 LDP	X12, X15, [SP, #240]

0x50721c LDP	X14, X3, [SP, #256]

0x507220 UBFM	X10, X15, #61, #60

0x507224 LDP	X5, X11, [SP, #288]

0x507228 CMP	X14, #1

0x50722c LDP	X7, X8, [SP, #304]

0x507230 LDP	X18, X4, [SP, #320]

0x507234 LDR	X13, [SP, #200]

0x507238 LDR	X17, [X25, X2]

0x50723c LDR	X9, [SP, #272]

0x507240 STR	X0, [X13, X2]

0x507244 LDR	X0, [SP, #216]

0x507248 STR	X21, [X0, X2]

0x50724c B.EQ	507624

0x507250 ADD	X1, X30, X15,LSL #3

0x507254 ADD	X21, X10, #8

0x507258 ADD	X16, X9, #8

0x50725c ADD	X6, X17, X21

0x507260 ADD	X2, X17, X15,LSL #3

0x507264 ADD	X25, X3, #8

0x507268 CMP	X6, X1

0x50726c CCMP	X16, X1, #4, #1

0x507270 CCMP	X25, X2, #4, #1

0x507274 B.EQ	507624

0x507278 UBFM	X21, X14, #1, #63

0x50727c MOVZ	X0, #0

0x507280 UBFM	X6, X21, #60, #59

0x507284 SUB	X25, X6, #16

0x507288 UBFM	X16, X25, #4, #63

0x50728c ADD	X13, X16, #1

0x507290 ANDS	X21, X13, #4224

0x507294 B.EQ	507348

0x507298 CMP	X21, #1

0x50729c B.EQ	50732c

0x5072a0 CMP	X21, #2

0x5072a4 B.EQ	507318

0x5072a8 CMP	X21, #3

0x5072ac B.EQ	507304

0x5072b0 CMP	X21, #4

0x5072b4 B.EQ	5072f0

0x5072b8 CMP	X21, #5

0x5072bc B.EQ	5072dc

0x5072c0 CMP	X21, #6

0x5072c4 B.NE	5077a8

0x5072c8 LDR	Q7, [X3, X0]

0x5072cc LDR	Q6, [X9, X0]

0x5072d0 STR	Q7, [X2, X0]

0x5072d4 STR	Q6, [X1, X0]

0x5072d8 ADD	X0, X0, #16

0x5072dc LDR	Q17, [X3, X0]

0x5072e0 LDR	Q16, [X9, X0]

0x5072e4 STR	Q17, [X2, X0]

0x5072e8 STR	Q16, [X1, X0]

0x5072ec ADD	X0, X0, #16

0x5072f0 LDR	Q19, [X3, X0]

0x5072f4 LDR	Q18, [X9, X0]

0x5072f8 STR	Q19, [X2, X0]

0x5072fc STR	Q18, [X1, X0]

0x507300 ADD	X0, X0, #16

0x507304 LDR	Q21, [X3, X0]

0x507308 LDR	Q20, [X9, X0]

0x50730c STR	Q21, [X2, X0]

0x507310 STR	Q20, [X1, X0]

0x507314 ADD	X0, X0, #16

0x507318 LDR	Q23, [X3, X0]

0x50731c LDR	Q22, [X9, X0]

0x507320 STR	Q23, [X2, X0]

0x507324 STR	Q22, [X1, X0]

0x507328 ADD	X0, X0, #16

0x50732c LDR	Q25, [X3, X0]

0x507330 LDR	Q24, [X9, X0]

0x507334 STR	Q25, [X2, X0]

0x507338 STR	Q24, [X1, X0]

0x50733c ADD	X0, X0, #16

0x507340 CMP	X6, X0

0x507344 B.EQ	5073f4

0x507348 ORR	X25, XZR, X6

  (3566) 0x50734c LDR	Q27, [X3, X0]

  (3566) 0x507350 ADD	X6, X0, #16

  (3566) 0x507354 ADD	X21, X0, #32

  (3566) 0x507358 ADD	X16, X0, #48

  (3566) 0x50735c ADD	X13, X0, #64

  (3566) 0x507360 LDR	Q26, [X9, X0]

  (3566) 0x507364 ADD	X10, X0, #80

  (3566) 0x507368 STR	Q27, [X2, X0]

  (3566) 0x50736c LDR	Q28, [X3, X6]

  (3566) 0x507370 STR	Q26, [X1, X0]

  (3566) 0x507374 LDR	Q29, [X9, X6]

  (3566) 0x507378 STR	Q28, [X2, X6]

  (3566) 0x50737c LDR	Q0, [X3, X21]

  (3566) 0x507380 STR	Q29, [X1, X6]

  (3566) 0x507384 ADD	X6, X0, #96

  (3566) 0x507388 LDR	Q31, [X9, X21]

  (3566) 0x50738c STR	Q0, [X2, X21]

  (3566) 0x507390 LDR	Q1, [X3, X16]

  (3566) 0x507394 STR	Q31, [X1, X21]

  (3566) 0x507398 ADD	X21, X0, #112

  (3566) 0x50739c ADD	X0, X0, #128

  (3566) 0x5073a0 LDR	Q2, [X9, X16]

  (3566) 0x5073a4 STR	Q1, [X2, X16]

  (3566) 0x5073a8 LDR	Q3, [X3, X13]

  (3566) 0x5073ac STR	Q2, [X1, X16]

  (3566) 0x5073b0 LDR	Q4, [X9, X13]

  (3566) 0x5073b4 STR	Q3, [X2, X13]

  (3566) 0x5073b8 LDR	Q30, [X3, X10]

  (3566) 0x5073bc STR	Q4, [X1, X13]

  (3566) 0x5073c0 LDR	Q5, [X9, X10]

  (3566) 0x5073c4 STR	Q30, [X2, X10]

  (3566) 0x5073c8 LDR	Q6, [X3, X6]

  (3566) 0x5073cc STR	Q5, [X1, X10]

  (3566) 0x5073d0 LDR	Q7, [X9, X6]

  (3566) 0x5073d4 STR	Q6, [X2, X6]

  (3566) 0x5073d8 LDR	Q16, [X3, X21]

  (3566) 0x5073dc STR	Q7, [X1, X6]

  (3566) 0x5073e0 LDR	Q17, [X9, X21]

  (3566) 0x5073e4 STR	Q16, [X2, X21]

  (3566) 0x5073e8 STR	Q17, [X1, X21]

  (3566) 0x5073ec CMP	X25, X0

  (3566) 0x5073f0 B.NE	50734c

0x5073f4 AND	X2, X14, #8127

0x5073f8 ADD	X15, X2, X15

0x5073fc TBZ	W14, #0, 5070ec

0x507400 UBFM	X14, X2, #61, #60

0x507404 UBFM	X1, X15, #61, #60

0x507408 LDR	X0, [X3, X14]

0x50740c LDR	D18, [X9, X14]

0x507410 STR	X0, [X17, X1]

0x507414 STR	D18, [X30, X1]

0x507418 B	5070ec

0x50741c SUB	X9, X12, X3

0x507420 MOVZ	X1, #8

0x507424 STP	X12, X6, [SP, #240]

0x507428 ORR	X0, XZR, X9

0x50742c STR	X9, [SP, #112]

0x507430 STP	X10, X2, [SP, #256]

0x507434 STR	X13, [SP, #272]

0x507438 STP	X5, X11, [SP, #288]

0x50743c STP	X7, X8, [SP, #304]

0x507440 STP	X18, X4, [SP, #320]

0x507444 BL	52b308

0x507448 ORR	X7, XZR, X0

0x50744c LDR	X0, [SP, #112]

0x507450 MOVZ	X1, #8

0x507454 STR	X7, [SP, #112]

0x507458 BL	52b308

0x50745c LDP	X12, X6, [SP, #240]

0x507460 ORR	X9, XZR, X0

0x507464 LDP	X10, X2, [SP, #256]

0x507468 LDP	X5, X11, [SP, #288]

0x50746c LDP	X7, X8, [SP, #304]

0x507470 LDP	X18, X4, [SP, #320]

0x507474 LDR	X3, [SP, #112]

0x507478 LDR	X13, [SP, #272]

0x50747c CMP	X12, #0

0x507480 B.GT	506f50

0x507484 ORR	X12, XZR, X21

0x507488 LDR	X21, [SP, #184]

0x50748c STR	X2, [X21, X13]

0x507490 B	5070e4

0x507624 ANDS	X16, X14, #4224

0x507628 ADD	X21, X17, X10

0x50762c MOVZ	X0, #0

0x507630 ADD	X25, X30, X10

0x507634 B.EQ	5076fc

0x507638 CMP	X16, #1

0x50763c B.EQ	5076e0

0x507640 CMP	X16, #2

0x507644 B.EQ	5076cc

0x507648 CMP	X16, #3

0x50764c B.EQ	5076b8

0x507650 CMP	X16, #4

0x507654 B.EQ	5076a4

0x507658 CMP	X16, #5

0x50765c B.EQ	507690

0x507660 CMP	X16, #6

0x507664 B.EQ	50767c

0x507668 LDR	D19, [X9]

0x50766c MOVZ	X0, #1

0x507670 LDR	X13, [X3]

0x507674 STR	X13, [X17, X10]

0x507678 STR	D19, [X30, X10]

0x50767c LDR	D20, [X9, X0,LSL #3]

0x507680 LDR	X30, [X3, X0,LSL #3]

0x507684 STR	X30, [X21, X0,LSL #3]

0x507688 STR	D20, [X25, X0,LSL #3]

0x50768c ADD	X0, X0, #1

0x507690 LDR	D21, [X9, X0,LSL #3]

0x507694 LDR	X17, [X3, X0,LSL #3]

0x507698 STR	X17, [X21, X0,LSL #3]

0x50769c STR	D21, [X25, X0,LSL #3]

0x5076a0 ADD	X0, X0, #1

0x5076a4 LDR	D22, [X9, X0,LSL #3]

0x5076a8 LDR	X10, [X3, X0,LSL #3]

0x5076ac STR	X10, [X21, X0,LSL #3]

0x5076b0 STR	D22, [X25, X0,LSL #3]

0x5076b4 ADD	X0, X0, #1

0x5076b8 LDR	D23, [X9, X0,LSL #3]

0x5076bc LDR	X6, [X3, X0,LSL #3]

0x5076c0 STR	X6, [X21, X0,LSL #3]

0x5076c4 STR	D23, [X25, X0,LSL #3]

0x5076c8 ADD	X0, X0, #1

0x5076cc LDR	D24, [X9, X0,LSL #3]

0x5076d0 LDR	X2, [X3, X0,LSL #3]

0x5076d4 STR	X2, [X21, X0,LSL #3]

0x5076d8 STR	D24, [X25, X0,LSL #3]

0x5076dc ADD	X0, X0, #1

0x5076e0 LDR	D25, [X9, X0,LSL #3]

0x5076e4 LDR	X15, [X3, X0,LSL #3]

0x5076e8 STR	X15, [X21, X0,LSL #3]

0x5076ec STR	D25, [X25, X0,LSL #3]

0x5076f0 ADD	X0, X0, #1

0x5076f4 CMP	X0, X14

0x5076f8 B.EQ	5070ec

  (3565) 0x5076fc LDR	X16, [X3, X0,LSL #3]

  (3565) 0x507700 ADD	X1, X0, #1

  (3565) 0x507704 ADD	X30, X0, #2

  (3565) 0x507708 ADD	X13, X0, #3

  (3565) 0x50770c ADD	X17, X0, #4

  (3565) 0x507710 LDR	D26, [X9, X0,LSL #3]

  (3565) 0x507714 ADD	X2, X0, #6

  (3565) 0x507718 STR	X16, [X21, X0,LSL #3]

  (3565) 0x50771c ADD	X16, X0, #5

  (3565) 0x507720 LDR	X10, [X3, X1,LSL #3]

  (3565) 0x507724 STR	D26, [X25, X0,LSL #3]

  (3565) 0x507728 LDR	D27, [X9, X1,LSL #3]

  (3565) 0x50772c STR	X10, [X21, X1,LSL #3]

  (3565) 0x507730 LDR	X6, [X3, X30,LSL #3]

  (3565) 0x507734 STR	D27, [X25, X1,LSL #3]

  (3565) 0x507738 ADD	X1, X0, #7

  (3565) 0x50773c ADD	X0, X0, #8

  (3565) 0x507740 LDR	D28, [X9, X30,LSL #3]

  (3565) 0x507744 STR	X6, [X21, X30,LSL #3]

  (3565) 0x507748 LDR	X15, [X3, X13,LSL #3]

  (3565) 0x50774c STR	D28, [X25, X30,LSL #3]

  (3565) 0x507750 LDR	D29, [X9, X13,LSL #3]

  (3565) 0x507754 STR	X15, [X21, X13,LSL #3]

  (3565) 0x507758 LDR	X30, [X3, X17,LSL #3]

  (3565) 0x50775c STR	D29, [X25, X13,LSL #3]

  (3565) 0x507760 LDR	D0, [X9, X17,LSL #3]

  (3565) 0x507764 STR	X30, [X21, X17,LSL #3]

  (3565) 0x507768 LDR	X13, [X3, X16,LSL #3]

  (3565) 0x50776c STR	D0, [X25, X17,LSL #3]

  (3565) 0x507770 LDR	D31, [X9, X16,LSL #3]

  (3565) 0x507774 STR	X13, [X21, X16,LSL #3]

  (3565) 0x507778 LDR	X17, [X3, X2,LSL #3]

  (3565) 0x50777c STR	D31, [X25, X16,LSL #3]

  (3565) 0x507780 LDR	D1, [X9, X2,LSL #3]

  (3565) 0x507784 STR	X17, [X21, X2,LSL #3]

  (3565) 0x507788 LDR	X10, [X3, X1,LSL #3]

  (3565) 0x50778c STR	D1, [X25, X2,LSL #3]

  (3565) 0x507790 LDR	D2, [X9, X1,LSL #3]

  (3565) 0x507794 STR	X10, [X21, X1,LSL #3]

  (3565) 0x507798 STR	D2, [X25, X1,LSL #3]

  (3565) 0x50779c CMP	X0, X14

  (3565) 0x5077a0 B.NE	5076fc

0x5077a4 B	5070ec

0x5077a8 LDR	Q30, [X3]

0x5077ac MOVZ	X0, #16

0x5077b0 LDR	Q5, [X9]

0x5077b4 STR	Q30, [X17, X10]

0x5077b8 STR	Q5, [X30, X10]

0x5077bc B	5072c8

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3500

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

3353:                      local_j = aux_j[row_local];

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

[...]

3446:                                  hypre_printf("Error in row %d ! Too many elements !\n",

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

[...]

3500: 		        col_indx += row_len;

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.53
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P12,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3293-3316,IJMatrix_parcsr.c:3344-3353,IJMatrix_parcsr.c:3359-3362,IJMatrix_parcsr.c:3365-3368,IJMatrix_parcsr.c:3376-3376,IJMatrix_parcsr.c:3446-3446,IJMatrix_parcsr.c:3467-3467
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	43.83
CQA cycles if no scalar integer	17.33
CQA cycles if FP arith vectorized	43.83
CQA cycles if fully vectorized	37.50
Front-end cycles	31.63
P0 cycles	19.50
P1 cycles	19.50
P2 cycles	14.92
P3 cycles	14.92
P4 cycles	14.83
P5 cycles	14.83
P6 cycles	14.75
P7 cycles	14.75
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	43.83
P13 cycles	43.50
P14 cycles	43.67
P15 cycles	16.50
P16 cycles	16.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	254.00
Nb uops	253.00
Nb loads	NA
Nb stores	55.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.13
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	656.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.69
Vectorization ratio load	48.28
Vectorization ratio store	25.45
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	71.56
Vector-efficiency ratio load	84.48
Vector-efficiency ratio store	74.55
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.53
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.00
Bottlenecks	P12,
Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source	IJMatrix_parcsr.c:3293-3316,IJMatrix_parcsr.c:3344-3353,IJMatrix_parcsr.c:3359-3362,IJMatrix_parcsr.c:3365-3368,IJMatrix_parcsr.c:3376-3376,IJMatrix_parcsr.c:3446-3446,IJMatrix_parcsr.c:3467-3467
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	43.83
CQA cycles if no scalar integer	17.33
CQA cycles if FP arith vectorized	43.83
CQA cycles if fully vectorized	37.50
Front-end cycles	31.63
P0 cycles	19.50
P1 cycles	19.50
P2 cycles	14.92
P3 cycles	14.92
P4 cycles	14.83
P5 cycles	14.83
P6 cycles	14.75
P7 cycles	14.75
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	43.83
P13 cycles	43.50
P14 cycles	43.67
P15 cycles	16.50
P16 cycles	16.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	254.00
Nb uops	253.00
Nb loads	NA
Nb stores	55.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	34.13
Bytes prefetched	0.00
Bytes loaded	840.00
Bytes stored	656.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	25.69
Vectorization ratio load	48.28
Vectorization ratio store	25.45
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	71.56
Vector-efficiency ratio load	84.48
Vector-efficiency ratio store	74.55
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3291-3322,3329-3353,3359-3368,3376,3446,3466-3484,3500.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3293-3316,3344-3353,3359-3362,3365-3368,3376,3446,3467.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 43.83 to 17.33 cycles (2.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 71% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 43.83 to 37.50 cycles (1.17x speedup).

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

48% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 43.83 to 3.00 cycles (14.61x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 840 bytes. The binary loop is storing 656 bytes.

General properties

nb instructions	254
loop length	1016
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

31.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	19.50	19.50	14.92	14.92	14.83	14.83	14.75	14.75	11.00	11.00	0.00	0.00	43.83	43.50	43.67	16.50	16.50
cycles	19.50	19.50	14.92	14.92	14.83	14.83	14.75	14.75	11.00	11.00	0.00	0.00	43.83	43.50	43.67	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	31.63
Overall L1	43.83

Vectorization ratios

all	25%
load	48%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.83 cycles. At this rate:

19% of peak load performance is reached (19.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (14.97 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 506800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X16, X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X17, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X16, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X25, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 506bd8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 506bd8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X30, X25, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X13, X30, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X16, 506f18 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xad8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X2, 506c10 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X15, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X14, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X10, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 50741c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 506be4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X14, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X21, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X15, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X1, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X15, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X14, 5071c4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBZ X3, 506be4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X11, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X4, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 506be4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X25, X21, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X6, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X14, X3, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b348 <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X10, X25, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X10, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X25, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b348 <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X12, X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X14, X3, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
UBFM X10, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X25, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X13, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [X0, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.EQ 507624 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X30, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X17, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X17, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X6, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X16, X1, #4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CCMP X25, X2, #4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.EQ 507624 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X21, X14, #1, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X6, X21, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X25, X6, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X16, X25, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X21, X13, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 507348 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 50732c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xeec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 507318 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xed8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 507304 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xec4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5072f0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xeb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5072dc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 5077a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q7, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q6, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q7, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q6, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q17, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q16, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q17, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q16, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q19, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q18, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q19, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q18, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q21, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q20, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q21, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q20, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q22, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q23, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q22, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q25, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q24, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q25, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q24, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X6, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5073f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X2, X14, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X2, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W14, #0, 5070ec <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X1, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X3, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X9, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X0, [X17, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D18, [X30, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 5070ec <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X12, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X12, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X0, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X9, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X10, X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 506f50 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X12, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X21, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X21, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 5070e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ANDS X16, X14, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD X21, X17, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X30, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B.EQ 5076fc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x12bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5076e0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x12a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5076cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x128c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5076b8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5076a4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 507690 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 50767c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x123c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MOVZ X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [X17, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D19, [X30, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D20, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X30, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D20, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X17, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D21, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D22, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X10, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D22, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D23, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D23, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D24, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X15, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D25, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 5070ec <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 5070ec <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVZ X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q5, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q30, [X17, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q5, [X30, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 5072c8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1
Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

25% of VPU instructions are used in vector version (process two or more data elements in vector registers):

48% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 43.83 to 3.00 cycles (14.61x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 840 bytes. The binary loop is storing 656 bytes.

General properties

nb instructions	254
loop length	1016
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

31.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	19.50	19.50	14.92	14.92	14.83	14.83	14.75	14.75	11.00	11.00	0.00	0.00	43.83	43.50	43.67	16.50	16.50
cycles	19.50	19.50	14.92	14.92	14.83	14.83	14.75	14.75	11.00	11.00	0.00	0.00	43.83	43.50	43.67	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	31.63
Overall L1	43.83

Vectorization ratios

all	25%
load	48%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.83 cycles. At this rate:

19% of peak load performance is reached (19.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (14.97 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 506800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X16, X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X30]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X17, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X16, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X25, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 506bd8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X18]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 506bd8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X30, X25, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X13, X30, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X16, 506f18 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xad8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X2, 506c10 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X15, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X14, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X3, X10, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X16, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 50741c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 506be4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X14, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X21, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X15, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X1, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X15, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X21, [X1, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X14, 5071c4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBZ X3, 506be4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X11, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X4, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 506be4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X25, X21, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X6, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X14, X3, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b348 <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X10, X25, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X10, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [X25, X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b348 <hypre_ReAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X30, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X12, X15, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X14, X3, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
UBFM X10, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X25, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X13, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [X0, X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.EQ 507624 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X1, X30, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X16, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X6, X17, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X17, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X6, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X16, X1, #4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CCMP X25, X2, #4, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.EQ 507624 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x11e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X21, X14, #1, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X6, X21, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X25, X6, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X16, X25, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X21, X13, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 507348 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 50732c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xeec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 507318 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xed8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 507304 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xec4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5072f0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xeb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5072dc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 5077a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q7, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q6, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q7, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q6, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q17, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q16, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q17, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q16, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q19, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q18, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q19, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q18, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q21, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q20, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q21, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q20, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q23, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q22, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q23, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q22, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q25, [X3, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q24, [X9, X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q25, [X2, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q24, [X1, X0]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X0, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X6, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5073f4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X2, X14, #8127	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X2, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBZ W14, #0, 5070ec <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X14, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X1, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X3, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D18, [X9, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X0, [X17, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D18, [X30, X1]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 5070ec <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X9, X12, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X12, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X0, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X9, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X10, X2, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X5, X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X8, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X4, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 506f50 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xb10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X12, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X21, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X21, X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 5070e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xca4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ANDS X16, X14, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
ADD X21, X17, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X25, X30, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B.EQ 5076fc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x12bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5076e0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x12a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5076cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x128c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5076b8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5076a4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 507690 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1250>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 50767c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x123c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MOVZ X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X13, [X17, X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D19, [X30, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D20, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X30, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X30, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D20, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D21, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X17, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X17, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D21, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D22, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X10, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D22, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D23, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X6, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D23, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D24, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X2, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D24, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D25, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X15, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D25, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X0, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 5070ec <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 5070ec <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xcac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVZ X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q5, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q30, [X17, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q5, [X30, X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
B 5072c8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xe88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code