OV - exec - Loop 3102

0x4e7a2c LDR	X23, [X16, X12,LSL #3]

0x4e7a30 LDR	D28, [X13, X12,LSL #3]

0x4e7a34 UBFM	X5, X23, #61, #60

0x4e7a38 ADD	X8, X5, #8

0x4e7a3c LDR	X1, [X27, X5]

0x4e7a40 ADD	X15, X27, X8

0x4e7a44 LDR	X14, [X27, X8]

0x4e7a48 CMP	X1, X14

0x4e7a4c B.GE	4e7a8c

  (3104) 0x4e7a50 LDR	X4, [X21, X1,LSL #3]

  (3104) 0x4e7a54 UBFM	X28, X2, #61, #60

  (3104) 0x4e7a58 LDR	D6, [X22, X1,LSL #3]

  (3104) 0x4e7a5c UBFM	X23, X4, #61, #60

  (3104) 0x4e7a60 LDR	X3, [X0, X23]

  (3104) 0x4e7a64 FMUL	D7, D28, D6

  (3104) 0x4e7a68 UBFM	X30, X3, #61, #60

  (3104) 0x4e7a6c CMP	X20, X3

  (3104) 0x4e7a70 B.GT	4e7c24

  (3104) 0x4e7a74 LDR	D16, [X19, X30]

  (3104) 0x4e7a78 ADD	X1, X1, #1

  (3104) 0x4e7a7c FADD	D17, D16, D7

  (3104) 0x4e7a80 STR	D17, [X19, X30]

  (3104) 0x4e7a84 CMP	X1, X14

  (3104) 0x4e7a88 B.LT	4e7a50

0x4e7a8c CBNZ	X17, 4e7c48

0x4e7a90 LDR	X4, [X10, #8]

0x4e7a94 ADD	X12, X12, #1

0x4e7a98 CMP	X4, X12

0x4e7a9c B.GT	4e7a2c

  (3104) 0x4e7c24 STR	X2, [X0, X23]

  (3104) 0x4e7c28 ADD	X1, X1, #1

  (3104) 0x4e7c2c ADD	X2, X2, #1

  (3104) 0x4e7c30 STR	D7, [X19, X28]

  (3104) 0x4e7c34 STR	X4, [X24, X28]

  (3104) 0x4e7c38 LDR	X14, [X15]

  (3104) 0x4e7c3c CMP	X14, X1

  (3104) 0x4e7c40 B.GT	4e7a50

0x4e7c44 CBZ	X17, 4e7a90

0x4e7c48 LDR	X1, [X18, X5]

0x4e7c4c ADD	X4, X18, X8

0x4e7c50 LDR	X30, [X18, X8]

0x4e7c54 CMP	X1, X30

0x4e7c58 B.GE	4e7a90

0x4e7c5c LDR	X28, [SP, #136]

  (3103) 0x4e7c60 UBFM	X23, X9, #61, #60

  (3103) 0x4e7c64 LDR	X5, [X6, X1,LSL #3]

  (3103) 0x4e7c68 LDR	D27, [X7, X1,LSL #3]

  (3103) 0x4e7c6c LDR	X8, [X11, X5,LSL #3]

  (3103) 0x4e7c70 FMUL	D18, D28, D27

  (3103) 0x4e7c74 ADD	X15, X26, X8

  (3103) 0x4e7c78 UBFM	X3, X15, #61, #60

  (3103) 0x4e7c7c LDR	X14, [X0, X3]

  (3103) 0x4e7c80 UBFM	X5, X14, #61, #60

  (3103) 0x4e7c84 CMP	X25, X14

  (3103) 0x4e7c88 B.GT	4e7ca8

  (3103) 0x4e7c8c LDR	D26, [X28, X5]

  (3103) 0x4e7c90 ADD	X1, X1, #1

  (3103) 0x4e7c94 FADD	D19, D26, D18

  (3103) 0x4e7c98 STR	D19, [X28, X5]

  (3103) 0x4e7c9c CMP	X1, X30

  (3103) 0x4e7ca0 B.LT	4e7c60

0x4e7ca4 B	4e7a90

  (3103) 0x4e7ca8 LDR	X30, [SP, #112]

  (3103) 0x4e7cac ADD	X1, X1, #1

  (3103) 0x4e7cb0 STR	X9, [X0, X3]

  (3103) 0x4e7cb4 ADD	X9, X9, #1

  (3103) 0x4e7cb8 STR	D18, [X28, X23]

  (3103) 0x4e7cbc STR	X8, [X30, X23]

  (3103) 0x4e7cc0 LDR	X30, [X4]

  (3103) 0x4e7cc4 CMP	X30, X1

  (3103) 0x4e7cc8 B.GT	4e7c60

0x4e7ccc B	4e7a90

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 937 - 989

--------------------------------------------------------------------------------

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module
►99.50+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.63
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P0, P1,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:937-937,par_csr_matop.c:940-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	1.75
Front-end cycles	2.88
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	1.42
P3 cycles	1.42
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	2.67
P13 cycles	2.67
P14 cycles	2.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.63
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.22
Bottlenecks	P0, P1,
Function	hypre_ParMatmul._omp_fn.3
Source	par_csr_matop.c:937-937,par_csr_matop.c:940-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.50
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	1.75
Front-end cycles	2.88
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	1.42
P3 cycles	1.42
P4 cycles	1.33
P5 cycles	1.33
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	2.67
P13 cycles	2.67
P14 cycles	2.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.29
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:937-989
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937,940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 12 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.33 cycles (2.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 1.75 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	1.42	1.42	1.33	1.33	1.25	1.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	3.50	3.50	1.42	1.42	1.33	1.33	1.25	1.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.88
Overall L1	3.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

19% of peak load performance is reached (18.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4e7a2c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X23, [X16, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR D28, [X13, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
UBFM X5, X23, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
ADD X8, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X1, [X27, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X15, X27, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
LDR X14, [X27, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
CMP X1, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 4e7a8c <hypre_ParMatmul._omp_fn.3+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X17, 4e7c48 <hypre_ParMatmul._omp_fn.3+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X10, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X4, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GT 4e7a2c <hypre_ParMatmul._omp_fn.3+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X17, 4e7a90 <hypre_ParMatmul._omp_fn.3+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X18, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X4, X18, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
LDR X30, [X18, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X1, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 4e7a90 <hypre_ParMatmul._omp_fn.3+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 4e7a90 <hypre_ParMatmul._omp_fn.3+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e7a90 <hypre_ParMatmul._omp_fn.3+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul._omp_fn.3
Source file and lines	par_csr_matop.c:937-989
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937,940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 12 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.33 cycles (2.62x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.50 to 1.75 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	1.42	1.42	1.33	1.33	1.25	1.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	3.50	3.50	1.42	1.42	1.33	1.33	1.25	1.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.88
Overall L1	3.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

19% of peak load performance is reached (18.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4e7a2c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X23, [X16, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR D28, [X13, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
UBFM X5, X23, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
ADD X8, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X1, [X27, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X15, X27, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
LDR X14, [X27, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
CMP X1, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 4e7a8c <hypre_ParMatmul._omp_fn.3+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X17, 4e7c48 <hypre_ParMatmul._omp_fn.3+0x3a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X10, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X4, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GT 4e7a2c <hypre_ParMatmul._omp_fn.3+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X17, 4e7a90 <hypre_ParMatmul._omp_fn.3+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X18, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X4, X18, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
LDR X30, [X18, X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X1, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 4e7a90 <hypre_ParMatmul._omp_fn.3+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 4e7a90 <hypre_ParMatmul._omp_fn.3+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e7a90 <hypre_ParMatmul._omp_fn.3+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code