OV - exec - Loop 3087

	Loop Id: 3087	Module: exec	Source: par_csr_matop.c:127-242 [...]	Coverage: 0.01%

0x4e68d4 ORR	X3, XZR, X20

0x4e68d8 LDR	X18, [SP, #112]

0x4e68dc CBNZ	X18, 4e69b0

0x4e68e4 LDR	X17, [X28, X2,LSL #3]

0x4e68e8 ORR	X7, XZR, X25

0x4e68ec LDR	X12, [X28, X15]

0x4e68f0 CMP	X17, X12

0x4e68f4 B.GE	4e6974

0x4e68f8 HINT	#0

0x4e68fc HINT	#0

  (3091) 0x4e6900 LDR	X25, [X6, X17,LSL #3]

  (3091) 0x4e6904 UBFM	X18, X25, #61, #60

  (3091) 0x4e6908 ADD	X30, X18, #8

  (3091) 0x4e690c LDR	X12, [X23, X18]

  (3091) 0x4e6910 ADD	X25, X23, X30

  (3091) 0x4e6914 LDR	X16, [X23, X30]

  (3091) 0x4e6918 CMP	X12, X16

  (3091) 0x4e691c B.GE	4e695c

  (3091) 0x4e6920 ORR	X13, XZR, X11

  (3091) 0x4e6924 STR	X0, [SP, #104]

    (3094) 0x4e6928 LDR	X11, [X21, X12,LSL #3]

    (3094) 0x4e692c UBFM	X11, X11, #61, #60

    (3094) 0x4e6930 LDR	X0, [X19, X11]

    (3094) 0x4e6934 CMP	X20, X0

    (3094) 0x4e6938 B.LE	4e6a84

    (3094) 0x4e693c STR	X3, [X19, X11]

    (3094) 0x4e6940 ADD	X12, X12, #1

    (3094) 0x4e6944 ADD	X3, X3, #1

    (3094) 0x4e6948 LDR	X16, [X25]

    (3094) 0x4e694c CMP	X16, X12

    (3094) 0x4e6950 B.GT	4e6928

  (3091) 0x4e6954 LDR	X0, [SP, #104]

  (3091) 0x4e6958 ORR	X11, XZR, X13

  (3091) 0x4e695c CBNZ	X5, 4e6acc

  (3091) 0x4e6960 LDR	X18, [X28, X15]

  (3091) 0x4e6964 ADD	X17, X17, #1

  (3091) 0x4e6968 CMP	X18, X17

  (3091) 0x4e696c B.GT	4e6900

0x4e6970 ORR	X25, XZR, X7

0x4e6974 STR	X20, [X0, X2,LSL #3]

0x4e6978 ADD	X15, X15, #8

0x4e697c LDR	X20, [SP, #120]

0x4e6980 STR	X14, [X1, X2,LSL #3]

0x4e6984 ADD	X2, X2, #1

0x4e6988 CMP	X20, X2

0x4e698c B.EQ	4e6b40

0x4e6990 LDR	X13, [SP, #128]

0x4e6994 ORR	X14, XZR, X11

0x4e6998 ORR	X20, XZR, X3

0x4e699c CBZ	X13, 4e68d4

0x4e69b0 LDR	X30, [X10, X2,LSL #3]

0x4e69b4 LDR	X12, [X10, X15]

0x4e69b8 CMP	X30, X12

0x4e69bc B.GE	4e68e0

0x4e69c0 LDR	X7, [SP, #184]

0x4e69c4 ORR	X11, XZR, X14

0x4e69c8 STP	X5, X24, [SP, #144]

  (3086) 0x4e69cc LDR	X24, [X4, X30,LSL #3]

  (3086) 0x4e69d0 UBFM	X5, X24, #61, #60

  (3086) 0x4e69d4 ADD	X24, X5, #8

  (3086) 0x4e69d8 LDR	X12, [X7, X5]

  (3086) 0x4e69dc ADD	X17, X7, X24

  (3086) 0x4e69e0 LDR	X16, [X7, X24]

  (3086) 0x4e69e4 CMP	X12, X16

  (3086) 0x4e69e8 B.GE	4e6a24

  (3086) 0x4e69ec STR	X0, [SP, #104]

    (3089) 0x4e69f0 LDR	X0, [X25, X12,LSL #3]

    (3089) 0x4e69f4 ADD	X13, X22, X0

    (3089) 0x4e69f8 UBFM	X18, X13, #61, #60

    (3089) 0x4e69fc LDR	X0, [X19, X18]

    (3089) 0x4e6a00 CMP	X14, X0

    (3089) 0x4e6a04 B.LE	4e6a9c

    (3089) 0x4e6a08 STR	X11, [X19, X18]

    (3089) 0x4e6a0c ADD	X12, X12, #1

    (3089) 0x4e6a10 ADD	X11, X11, #1

    (3089) 0x4e6a14 LDR	X16, [X17]

    (3089) 0x4e6a18 CMP	X12, X16

    (3089) 0x4e6a1c B.LT	4e69f0

  (3086) 0x4e6a20 LDR	X0, [SP, #104]

  (3086) 0x4e6a24 LDR	X13, [X8, X5]

  (3086) 0x4e6a28 ADD	X5, X8, X24

  (3086) 0x4e6a2c LDR	X18, [X8, X24]

  (3086) 0x4e6a30 CMP	X13, X18

  (3086) 0x4e6a34 B.GE	4e6a6c

  (3086) 0x4e6a38 HINT	#0

  (3086) 0x4e6a3c HINT	#0

    (3088) 0x4e6a40 LDR	X24, [X26, X13,LSL #3]

    (3088) 0x4e6a44 UBFM	X17, X24, #61, #60

    (3088) 0x4e6a48 LDR	X12, [X19, X17]

    (3088) 0x4e6a4c CMP	X20, X12

    (3088) 0x4e6a50 B.LE	4e6aac

    (3088) 0x4e6a54 STR	X3, [X19, X17]

    (3088) 0x4e6a58 ADD	X13, X13, #1

    (3088) 0x4e6a5c ADD	X3, X3, #1

    (3088) 0x4e6a60 LDR	X18, [X5]

    (3088) 0x4e6a64 CMP	X18, X13

    (3088) 0x4e6a68 B.GT	4e6a40

  (3086) 0x4e6a6c LDR	X16, [X10, X15]

  (3086) 0x4e6a70 ADD	X30, X30, #1

  (3086) 0x4e6a74 CMP	X16, X30

  (3086) 0x4e6a78 B.GT	4e69cc

0x4e6a7c LDP	X5, X24, [SP, #144]

0x4e6a80 B	4e68e4

    (3094) 0x4e6a84 ADD	X12, X12, #1

    (3094) 0x4e6a88 CMP	X12, X16

    (3094) 0x4e6a8c B.LT	4e6928

  (3091) 0x4e6a90 LDR	X0, [SP, #104]

  (3091) 0x4e6a94 ORR	X11, XZR, X13

  (3091) 0x4e6a98 B	4e695c

    (3089) 0x4e6a9c ADD	X12, X12, #1

    (3089) 0x4e6aa0 CMP	X12, X16

    (3089) 0x4e6aa4 B.LT	4e69f0

  (3086) 0x4e6aa8 B	4e6a20

    (3088) 0x4e6aac ADD	X13, X13, #1

    (3088) 0x4e6ab0 CMP	X13, X18

    (3088) 0x4e6ab4 B.LT	4e6a40

  (3086) 0x4e6ab8 LDR	X16, [X10, X15]

  (3086) 0x4e6abc ADD	X30, X30, #1

  (3086) 0x4e6ac0 CMP	X16, X30

  (3086) 0x4e6ac4 B.GT	4e69cc

0x4e6ac8 B	4e6a7c

  (3091) 0x4e6acc LDR	X13, [X9, X18]

  (3091) 0x4e6ad0 ADD	X18, X9, X30

  (3091) 0x4e6ad4 LDR	X25, [X9, X30]

  (3091) 0x4e6ad8 CMP	X13, X25

  (3091) 0x4e6adc B.GE	4e6960

    (3092) 0x4e6ae0 LDR	X30, [X27, X13,LSL #3]

    (3092) 0x4e6ae4 LDR	X12, [X24, X30,LSL #3]

    (3092) 0x4e6ae8 ADD	X16, X22, X12

    (3092) 0x4e6aec UBFM	X30, X16, #61, #60

    (3092) 0x4e6af0 LDR	X12, [X19, X30]

    (3092) 0x4e6af4 CMP	X14, X12

    (3092) 0x4e6af8 B.LE	4e6b30

    (3093) 0x4e6afc STR	X11, [X19, X30]

    (3093) 0x4e6b00 ADD	X13, X13, #1

    (3093) 0x4e6b04 ADD	X11, X11, #1

    (3093) 0x4e6b08 LDR	X25, [X18]

    (3093) 0x4e6b0c CMP	X25, X13

    (3093) 0x4e6b10 B.LE	4e6960

    (3093) 0x4e6b14 LDR	X30, [X27, X13,LSL #3]

    (3093) 0x4e6b18 LDR	X12, [X24, X30,LSL #3]

    (3093) 0x4e6b1c ADD	X16, X22, X12

    (3093) 0x4e6b20 UBFM	X30, X16, #61, #60

    (3093) 0x4e6b24 LDR	X12, [X19, X30]

    (3093) 0x4e6b28 CMP	X14, X12

    (3093) 0x4e6b2c B.GT	4e6afc

    (3092) 0x4e6b30 ADD	X13, X13, #1

    (3092) 0x4e6b34 CMP	X25, X13

    (3092) 0x4e6b38 B.GT	4e6ae0

  (3091) 0x4e6b3c B	4e6960

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P12,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	3.50
Front-end cycles	3.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	1.92
P3 cycles	1.92
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.17
P13 cycles	3.83
P14 cycles	4.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	30.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.88
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	55.88
Vector-efficiency ratio load	58.33
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P12,
Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-135,par_csr_matop.c:144-146,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	3.50
Front-end cycles	3.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	1.92
P3 cycles	1.92
P4 cycles	1.83
P5 cycles	1.83
P6 cycles	1.75
P7 cycles	1.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	4.17
P13 cycles	3.83
P14 cycles	4.00
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	30.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.88
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	55.88
Vector-efficiency ratio load	58.33
Vector-efficiency ratio store	66.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-242.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135,144-146,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 55% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 3.50 cycles (1.19x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50
cycles	3.50	3.50	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.75
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4e68e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X3, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X18, 4e69b0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X7, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X28, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4e6974 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X25, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X20, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X15, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X14, [X1, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4e6b40 <hypre_ParMatmul_RowSizes._omp_fn.0+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X14, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CBZ X13, 4e68d4 <hypre_ParMatmul_RowSizes._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X30, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4e68e0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X11, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 4e68e4 <hypre_ParMatmul_RowSizes._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e6a7c <hypre_ParMatmul_RowSizes._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul_RowSizes._omp_fn.0
Source file and lines	par_csr_matop.c:127-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 80 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50
cycles	3.50	3.50	1.92	1.92	1.83	1.83	1.75	1.75	0.00	0.00	0.00	0.00	4.17	3.83	4.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.75
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4e68e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ORR X3, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X18, 4e69b0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X28, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X7, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X28, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X17, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4e6974 <hypre_ParMatmul_RowSizes._omp_fn.0+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X25, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X20, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X15, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X14, [X1, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4e6b40 <hypre_ParMatmul_RowSizes._omp_fn.0+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X14, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X20, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CBZ X13, 4e68d4 <hypre_ParMatmul_RowSizes._omp_fn.0+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X30, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4e68e0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X11, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X5, X24, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 4e68e4 <hypre_ParMatmul_RowSizes._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e6a7c <hypre_ParMatmul_RowSizes._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code