OV - exec - Loop 2621

	Loop Id: 2621	Module: exec	Source: ams.c:3382-3401 [...]	Coverage: 0.02%

0x4c6d8c CMP	X0, X14

0x4c6d90 B.GE	4c707c

0x4c6d94 ADD	X30, X21, X14,LSL #3

0x4c6d98 UBFM	X7, X0, #61, #60

0x4c6d9c MOVI	D31, #0

0x4c6da0 ADD	X0, X21, X0,LSL #3

0x4c6da4 SUB	X4, X30, X0

0x4c6da8 SUB	X17, X4, #8

0x4c6dac UBFM	X8, X17, #3, #63

0x4c6db0 ADD	X16, X8, #1

0x4c6db4 ANDS	X15, X16, #4224

0x4c6db8 B.EQ	4c6e68

0x4c6dbc CMP	X15, #1

0x4c6dc0 B.EQ	4c6e50

0x4c6dc4 CMP	X15, #2

0x4c6dc8 B.EQ	4c6e40

0x4c6dcc CMP	X15, #3

0x4c6dd0 B.EQ	4c6e30

0x4c6dd4 CMP	X15, #4

0x4c6dd8 B.EQ	4c6e20

0x4c6ddc CMP	X15, #5

0x4c6de0 B.EQ	4c6e10

0x4c6de4 CMP	X15, #6

0x4c6de8 B.EQ	4c6e00

0x4c6dec LDR	D1, [X21, X7]

0x4c6df0 ADD	X0, X0, #8

0x4c6df4 FABS	D2, D1

0x4c6df8 FADD	D31, D31, D2

0x4c6dfc STR	D31, [X19, X2,LSL #3]

0x4c6e00 LDR	D3, [X0], #8

0x4c6e04 FABS	D4, D3

0x4c6e08 FADD	D31, D31, D4

0x4c6e0c STR	D31, [X19, X2,LSL #3]

0x4c6e10 LDR	D5, [X0], #8

0x4c6e14 FABS	D7, D5

0x4c6e18 FADD	D31, D31, D7

0x4c6e1c STR	D31, [X19, X2,LSL #3]

0x4c6e20 LDR	D16, [X0], #8

0x4c6e24 FABS	D17, D16

0x4c6e28 FADD	D31, D31, D17

0x4c6e2c STR	D31, [X19, X2,LSL #3]

0x4c6e30 LDR	D18, [X0], #8

0x4c6e34 FABS	D19, D18

0x4c6e38 FADD	D31, D31, D19

0x4c6e3c STR	D31, [X19, X2,LSL #3]

0x4c6e40 LDR	D20, [X0], #8

0x4c6e44 FABS	D21, D20

0x4c6e48 FADD	D31, D31, D21

0x4c6e4c STR	D31, [X19, X2,LSL #3]

0x4c6e50 LDR	D22, [X0], #8

0x4c6e54 FABS	D23, D22

0x4c6e58 FADD	D31, D31, D23

0x4c6e5c STR	D31, [X19, X2,LSL #3]

0x4c6e60 CMP	X0, X30

0x4c6e64 B.EQ	4c6ef8

  (2623) 0x4c6e68 ORR	X17, XZR, X0

  (2623) 0x4c6e6c ADD	X0, X0, #64

  (2623) 0x4c6e70 LDR	D23, [X17], #8

  (2623) 0x4c6e74 FABS	D24, D23

  (2623) 0x4c6e78 FADD	D31, D31, D24

  (2623) 0x4c6e7c STR	D31, [X19, X2,LSL #3]

  (2623) 0x4c6e80 LDUR	D25, [X0, #456]

  (2623) 0x4c6e84 FABS	D26, D25

  (2623) 0x4c6e88 FADD	D29, D31, D26

  (2623) 0x4c6e8c STR	D29, [X19, X2,LSL #3]

  (2623) 0x4c6e90 LDR	D6, [X17, #8]

  (2623) 0x4c6e94 FABS	D30, D6

  (2623) 0x4c6e98 FADD	D27, D29, D30

  (2623) 0x4c6e9c STR	D27, [X19, X2,LSL #3]

  (2623) 0x4c6ea0 LDUR	D28, [X0, #472]

  (2623) 0x4c6ea4 FABS	D0, D28

  (2623) 0x4c6ea8 FADD	D1, D27, D0

  (2623) 0x4c6eac STR	D1, [X19, X2,LSL #3]

  (2623) 0x4c6eb0 LDUR	D2, [X0, #480]

  (2623) 0x4c6eb4 FABS	D3, D2

  (2623) 0x4c6eb8 FADD	D4, D1, D3

  (2623) 0x4c6ebc STR	D4, [X19, X2,LSL #3]

  (2623) 0x4c6ec0 LDUR	D5, [X0, #488]

  (2623) 0x4c6ec4 FABS	D7, D5

  (2623) 0x4c6ec8 FADD	D16, D4, D7

  (2623) 0x4c6ecc STR	D16, [X19, X2,LSL #3]

  (2623) 0x4c6ed0 LDUR	D17, [X0, #496]

  (2623) 0x4c6ed4 FABS	D18, D17

  (2623) 0x4c6ed8 FADD	D31, D16, D18

  (2623) 0x4c6edc STR	D31, [X19, X2,LSL #3]

  (2623) 0x4c6ee0 LDUR	D22, [X0, #504]

  (2623) 0x4c6ee4 FABS	D23, D22

  (2623) 0x4c6ee8 FADD	D31, D31, D23

  (2623) 0x4c6eec STR	D31, [X19, X2,LSL #3]

  (2623) 0x4c6ef0 CMP	X0, X30

  (2623) 0x4c6ef4 B.NE	4c6e68

0x4c6ef8 CBNZ	X27, 4c6f1c

0x4c6efc ADD	X3, X3, #1

0x4c6f00 CMP	X3, X25

0x4c6f04 B.EQ	4c2d90

0x4c6f08 LDR	X0, [X28, X3,LSL #3]

0x4c6f0c ORR	X2, XZR, X3

0x4c6f10 STR	XZR, [X19, X3,LSL #3]

0x4c6f14 LDR	X14, [X11, X3,LSL #3]

0x4c6f18 B	4c6d8c

0x4c6f1c LDR	X14, [X10, X2,LSL #3]

0x4c6f20 LDR	X30, [X18, X2,LSL #3]

0x4c6f24 CMP	X14, X30

0x4c6f28 B.GE	4c6efc

0x4c6f2c ADD	X0, X6, X14,LSL #3

0x4c6f30 UBFM	X17, X14, #61, #60

0x4c6f34 ADD	X7, X6, X30,LSL #3

0x4c6f38 SUB	X4, X7, X0

0x4c6f3c SUB	X8, X4, #8

0x4c6f40 UBFM	X16, X8, #3, #63

0x4c6f44 ADD	X15, X16, #1

0x4c6f48 ANDS	X14, X15, #4224

0x4c6f4c B.EQ	4c6fe8

0x4c6f50 CMP	X14, #1

0x4c6f54 B.EQ	4c6fd0

0x4c6f58 CMP	X14, #2

0x4c6f5c B.EQ	4c6fc0

0x4c6f60 CMP	X14, #3

0x4c6f64 B.EQ	4c6fb0

0x4c6f68 CMP	X14, #4

0x4c6f6c B.EQ	4c6fa0

0x4c6f70 CMP	X14, #5

0x4c6f74 B.EQ	4c6f90

0x4c6f78 CMP	X14, #6

0x4c6f7c B.NE	4c719c

0x4c6f80 LDR	D26, [X0], #8

0x4c6f84 FABS	D29, D26

0x4c6f88 FADD	D31, D31, D29

0x4c6f8c STR	D31, [X19, X2,LSL #3]

0x4c6f90 LDR	D30, [X0], #8

0x4c6f94 FABS	D6, D30

0x4c6f98 FADD	D31, D31, D6

0x4c6f9c STR	D31, [X19, X2,LSL #3]

0x4c6fa0 LDR	D27, [X0], #8

0x4c6fa4 FABS	D28, D27

0x4c6fa8 FADD	D31, D31, D28

0x4c6fac STR	D31, [X19, X2,LSL #3]

0x4c6fb0 LDR	D0, [X0], #8

0x4c6fb4 FABS	D1, D0

0x4c6fb8 FADD	D31, D31, D1

0x4c6fbc STR	D31, [X19, X2,LSL #3]

0x4c6fc0 LDR	D2, [X0], #8

0x4c6fc4 FABS	D3, D2

0x4c6fc8 FADD	D31, D31, D3

0x4c6fcc STR	D31, [X19, X2,LSL #3]

0x4c6fd0 LDR	D4, [X0], #8

0x4c6fd4 FABS	D5, D4

0x4c6fd8 FADD	D31, D31, D5

0x4c6fdc STR	D31, [X19, X2,LSL #3]

0x4c6fe0 CMP	X7, X0

0x4c6fe4 B.EQ	4c6efc

  (2622) 0x4c6fe8 ORR	X30, XZR, X0

  (2622) 0x4c6fec ADD	X0, X0, #64

  (2622) 0x4c6ff0 LDR	D26, [X30], #8

  (2622) 0x4c6ff4 FABS	D29, D26

  (2622) 0x4c6ff8 FADD	D6, D31, D29

  (2622) 0x4c6ffc STR	D6, [X19, X2,LSL #3]

  (2622) 0x4c7000 LDUR	D30, [X0, #456]

  (2622) 0x4c7004 FABS	D27, D30

  (2622) 0x4c7008 FADD	D28, D6, D27

  (2622) 0x4c700c STR	D28, [X19, X2,LSL #3]

  (2622) 0x4c7010 LDR	D0, [X30, #8]

  (2622) 0x4c7014 FABS	D1, D0

  (2622) 0x4c7018 FADD	D2, D28, D1

  (2622) 0x4c701c STR	D2, [X19, X2,LSL #3]

  (2622) 0x4c7020 LDUR	D3, [X0, #472]

  (2622) 0x4c7024 FABS	D4, D3

  (2622) 0x4c7028 FADD	D5, D2, D4

  (2622) 0x4c702c STR	D5, [X19, X2,LSL #3]

  (2622) 0x4c7030 LDUR	D7, [X0, #480]

  (2622) 0x4c7034 FABS	D16, D7

  (2622) 0x4c7038 FADD	D17, D5, D16

  (2622) 0x4c703c STR	D17, [X19, X2,LSL #3]

  (2622) 0x4c7040 LDUR	D18, [X0, #488]

  (2622) 0x4c7044 FABS	D19, D18

  (2622) 0x4c7048 FADD	D20, D17, D19

  (2622) 0x4c704c STR	D20, [X19, X2,LSL #3]

  (2622) 0x4c7050 LDUR	D21, [X0, #496]

  (2622) 0x4c7054 FABS	D22, D21

  (2622) 0x4c7058 FADD	D31, D20, D22

  (2622) 0x4c705c STR	D31, [X19, X2,LSL #3]

  (2622) 0x4c7060 LDUR	D4, [X0, #504]

  (2622) 0x4c7064 FABS	D5, D4

  (2622) 0x4c7068 FADD	D31, D31, D5

  (2622) 0x4c706c STR	D31, [X19, X2,LSL #3]

  (2622) 0x4c7070 CMP	X7, X0

  (2622) 0x4c7074 B.NE	4c6fe8

0x4c7078 B	4c6efc

0x4c707c MOVI	D31, #0

0x4c7080 B	4c6ef8

0x4c719c LDR	D24, [X6, X17]

0x4c71a0 ADD	X0, X0, #8

0x4c71a4 FABS	D25, D24

0x4c71a8 FADD	D31, D31, D25

0x4c71ac STR	D31, [X19, X2,LSL #3]

0x4c71b0 B	4c6f80

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3401

--------------------------------------------------------------------------------

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

[...]

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

Coverage (%)	Name	Source Location	Module
►98.28+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.72+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_ParCSRComputeL1NormsThre[...]	ams.c:3546	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1409	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.66
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.50
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	12.31
CQA cycles if fully vectorized	7.75
Front-end cycles	15.50
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.17
P5 cycles	8.17
P6 cycles	8.08
P7 cycles	8.08
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	11.17
P13 cycles	10.83
P14 cycles	11.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	124.00
Nb uops	124.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.90
Nb FLOP add-sub	14.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.03
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.66
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.50
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	12.31
CQA cycles if fully vectorized	7.75
Front-end cycles	15.50
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.17
P5 cycles	8.17
P6 cycles	8.08
P7 cycles	8.08
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	11.17
P13 cycles	10.83
P14 cycles	11.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	124.00
Nb uops	124.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.90
Nb FLOP add-sub	14.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.03
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3394,3401.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3384,3388-3394,3401.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 272 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.50 to 9.33 cycles (1.66x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 15.50 to 7.75 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

14: addition or subtraction

The binary loop is loading 144 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	124
loop length	496
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	12.00	12.00	8.25	8.25	8.17	8.17	8.08	8.08	11.00	11.00	11.00	11.00	11.17	10.83	11.00	0.50	0.50
cycles	12.00	12.00	8.25	8.25	8.17	8.17	8.08	8.08	11.00	11.00	11.00	11.00	11.17	10.83	11.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.50
Overall L1	15.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.50 cycles. At this rate:

9% of peak load performance is reached (9.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4c6d8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4c707c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x43fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X21, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X7, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
ADD X0, X21, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X30, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X17, X4, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X8, X17, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X15, X16, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e68 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e50 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e40 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e30 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e20 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e10 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X21, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D2, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D3, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D5, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D7, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D16, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D17, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D18, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D19, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D20, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D21, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D22, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D23, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X0, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6ef8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X27, 4c6f1c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x429c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c2d90 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X14, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4c6d8c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x410c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [X18, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4c6efc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x427c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X6, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X17, X14, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X6, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X7, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X8, X4, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X16, X8, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X15, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X14, X15, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fe8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fd0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fc0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fb0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fa0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6f90 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4c719c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x451c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D26, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D29, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D6, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D27, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D28, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D2, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D3, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D4, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X7, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6efc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x427c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4c6efc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x427c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
B 4c6ef8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D24, [X6, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D25, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 4c6f80 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.50 to 9.33 cycles (1.66x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

14: addition or subtraction

The binary loop is loading 144 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	124
loop length	496
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	12.00	12.00	8.25	8.25	8.17	8.17	8.08	8.08	11.00	11.00	11.00	11.00	11.17	10.83	11.00	0.50	0.50
cycles	12.00	12.00	8.25	8.25	8.17	8.17	8.08	8.08	11.00	11.00	11.00	11.00	11.17	10.83	11.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.50
Overall L1	15.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.50 cycles. At this rate:

9% of peak load performance is reached (9.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.74 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4c6d8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
CMP X0, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4c707c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x43fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X21, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X7, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
ADD X0, X21, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X30, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X17, X4, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X8, X17, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X15, X16, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e68 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e50 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e40 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e30 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e20 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x41a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e10 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6e00 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X21, X7]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D2, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D3, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D5, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D7, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D16, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D17, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D18, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D19, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D20, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D21, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D22, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D23, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X0, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6ef8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X27, 4c6f1c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x429c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X3, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c2d90 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X14, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4c6d8c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x410c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [X18, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4c6efc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x427c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X6, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X17, X14, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X6, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X4, X7, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X8, X4, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X16, X8, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X15, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X14, X15, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fe8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fd0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fc0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4340>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fb0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6fa0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6f90 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X14, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4c719c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x451c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D26, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D29, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D30, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D6, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D27, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D28, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D2, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D3, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D4, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X7, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c6efc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x427c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4c6efc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x427c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
B 4c6ef8 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D24, [X6, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D25, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D31, D31, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D31, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 4c6f80 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code