OV - exec - Loop 2610

	Loop Id: 2610	Module: exec	Source: ams.c:3382-3401 [...]	Coverage: 0.01%

0x4c3ddc MOVI	D19, #0

0x4c3de0 CBNZ	X4, 4c4b98

0x4c3de4 ADD	X12, X12, #1

0x4c3de8 CMP	X26, X12

0x4c3dec B.EQ	4c310c

0x4c3df0 LDR	X14, [X7, X12,LSL #3]

0x4c3df4 ORR	X3, XZR, X12

0x4c3df8 LDR	X0, [X24, X12,LSL #3]

0x4c3dfc STR	XZR, [X19, X12,LSL #3]

0x4c3e00 CMP	X14, X0

0x4c3e04 B.LE	4c3ddc

0x4c3e08 ADD	X30, X21, X14,LSL #3

0x4c3e0c UBFM	X14, X0, #61, #60

0x4c3e10 MOVI	D19, #0

0x4c3e14 ADD	X0, X21, X0,LSL #3

0x4c3e18 SUB	X16, X30, X0

0x4c3e1c SUB	X2, X16, #8

0x4c3e20 UBFM	X18, X2, #3, #63

0x4c3e24 ADD	X17, X18, #1

0x4c3e28 ANDS	X11, X17, #4224

0x4c3e2c B.EQ	4c3edc

0x4c3e30 CMP	X11, #1

0x4c3e34 B.EQ	4c3ec4

0x4c3e38 CMP	X11, #2

0x4c3e3c B.EQ	4c3eb4

0x4c3e40 CMP	X11, #3

0x4c3e44 B.EQ	4c3ea4

0x4c3e48 CMP	X11, #4

0x4c3e4c B.EQ	4c3e94

0x4c3e50 CMP	X11, #5

0x4c3e54 B.EQ	4c3e84

0x4c3e58 CMP	X11, #6

0x4c3e5c B.EQ	4c3e74

0x4c3e60 LDR	D26, [X21, X14]

0x4c3e64 ADD	X0, X0, #8

0x4c3e68 FABS	D29, D26

0x4c3e6c FADD	D19, D19, D29

0x4c3e70 STR	D19, [X19, X3,LSL #3]

0x4c3e74 LDR	D6, [X0], #8

0x4c3e78 FABS	D0, D6

0x4c3e7c FADD	D19, D19, D0

0x4c3e80 STR	D19, [X19, X3,LSL #3]

0x4c3e84 LDR	D1, [X0], #8

0x4c3e88 FABS	D31, D1

0x4c3e8c FADD	D19, D19, D31

0x4c3e90 STR	D19, [X19, X3,LSL #3]

0x4c3e94 LDR	D2, [X0], #8

0x4c3e98 FABS	D3, D2

0x4c3e9c FADD	D19, D19, D3

0x4c3ea0 STR	D19, [X19, X3,LSL #3]

0x4c3ea4 LDR	D4, [X0], #8

0x4c3ea8 FABS	D5, D4

0x4c3eac FADD	D19, D19, D5

0x4c3eb0 STR	D19, [X19, X3,LSL #3]

0x4c3eb4 LDR	D7, [X0], #8

0x4c3eb8 FABS	D16, D7

0x4c3ebc FADD	D19, D19, D16

0x4c3ec0 STR	D19, [X19, X3,LSL #3]

0x4c3ec4 LDR	D17, [X0], #8

0x4c3ec8 FABS	D18, D17

0x4c3ecc FADD	D19, D19, D18

0x4c3ed0 STR	D19, [X19, X3,LSL #3]

0x4c3ed4 CMP	X30, X0

0x4c3ed8 B.EQ	4c3de0

  (2612) 0x4c3edc ORR	X14, XZR, X0

  (2612) 0x4c3ee0 ADD	X0, X0, #64

  (2612) 0x4c3ee4 LDR	D20, [X14], #8

  (2612) 0x4c3ee8 FABS	D21, D20

  (2612) 0x4c3eec FADD	D27, D19, D21

  (2612) 0x4c3ef0 STR	D27, [X19, X3,LSL #3]

  (2612) 0x4c3ef4 LDUR	D28, [X0, #456]

  (2612) 0x4c3ef8 FABS	D25, D28

  (2612) 0x4c3efc FADD	D22, D27, D25

  (2612) 0x4c3f00 STR	D22, [X19, X3,LSL #3]

  (2612) 0x4c3f04 LDR	D23, [X14, #8]

  (2612) 0x4c3f08 FABS	D30, D23

  (2612) 0x4c3f0c FADD	D24, D22, D30

  (2612) 0x4c3f10 STR	D24, [X19, X3,LSL #3]

  (2612) 0x4c3f14 LDUR	D26, [X0, #472]

  (2612) 0x4c3f18 FABS	D29, D26

  (2612) 0x4c3f1c FADD	D6, D24, D29

  (2612) 0x4c3f20 STR	D6, [X19, X3,LSL #3]

  (2612) 0x4c3f24 LDUR	D0, [X0, #480]

  (2612) 0x4c3f28 FABS	D1, D0

  (2612) 0x4c3f2c FADD	D31, D6, D1

  (2612) 0x4c3f30 STR	D31, [X19, X3,LSL #3]

  (2612) 0x4c3f34 LDUR	D2, [X0, #488]

  (2612) 0x4c3f38 FABS	D3, D2

  (2612) 0x4c3f3c FADD	D4, D31, D3

  (2612) 0x4c3f40 STR	D4, [X19, X3,LSL #3]

  (2612) 0x4c3f44 LDUR	D5, [X0, #496]

  (2612) 0x4c3f48 FABS	D7, D5

  (2612) 0x4c3f4c FADD	D16, D4, D7

  (2612) 0x4c3f50 STR	D16, [X19, X3,LSL #3]

  (2612) 0x4c3f54 LDUR	D17, [X0, #504]

  (2612) 0x4c3f58 FABS	D18, D17

  (2612) 0x4c3f5c FADD	D19, D16, D18

  (2612) 0x4c3f60 STR	D19, [X19, X3,LSL #3]

  (2612) 0x4c3f64 CMP	X30, X0

  (2612) 0x4c3f68 B.NE	4c3edc

0x4c3f6c B	4c3de0

0x4c4b98 LDR	X30, [X10, X3,LSL #3]

0x4c4b9c LDR	X16, [X15, X3,LSL #3]

0x4c4ba0 CMP	X16, X30

0x4c4ba4 B.LE	4c3de4

0x4c4ba8 ADD	X18, X6, X16,LSL #3

0x4c4bac UBFM	X17, X30, #61, #60

0x4c4bb0 ADD	X0, X6, X30,LSL #3

0x4c4bb4 SUB	X2, X18, X0

0x4c4bb8 SUB	X11, X2, #8

0x4c4bbc UBFM	X14, X11, #3, #63

0x4c4bc0 ADD	X30, X14, #1

0x4c4bc4 ANDS	X16, X30, #4224

0x4c4bc8 B.EQ	4c4c64

0x4c4bcc CMP	X16, #1

0x4c4bd0 B.EQ	4c4c4c

0x4c4bd4 CMP	X16, #2

0x4c4bd8 B.EQ	4c4c3c

0x4c4bdc CMP	X16, #3

0x4c4be0 B.EQ	4c4c2c

0x4c4be4 CMP	X16, #4

0x4c4be8 B.EQ	4c4c1c

0x4c4bec CMP	X16, #5

0x4c4bf0 B.EQ	4c4c0c

0x4c4bf4 CMP	X16, #6

0x4c4bf8 B.NE	4c7184

0x4c4bfc LDR	D27, [X0], #8

0x4c4c00 FABS	D28, D27

0x4c4c04 FADD	D19, D19, D28

0x4c4c08 STR	D19, [X19, X3,LSL #3]

0x4c4c0c LDR	D25, [X0], #8

0x4c4c10 FABS	D22, D25

0x4c4c14 FADD	D19, D19, D22

0x4c4c18 STR	D19, [X19, X3,LSL #3]

0x4c4c1c LDR	D23, [X0], #8

0x4c4c20 FABS	D30, D23

0x4c4c24 FADD	D19, D19, D30

0x4c4c28 STR	D19, [X19, X3,LSL #3]

0x4c4c2c LDR	D24, [X0], #8

0x4c4c30 FABS	D26, D24

0x4c4c34 FADD	D19, D19, D26

0x4c4c38 STR	D19, [X19, X3,LSL #3]

0x4c4c3c LDR	D29, [X0], #8

0x4c4c40 FABS	D6, D29

0x4c4c44 FADD	D19, D19, D6

0x4c4c48 STR	D19, [X19, X3,LSL #3]

0x4c4c4c LDR	D0, [X0], #8

0x4c4c50 FABS	D1, D0

0x4c4c54 FADD	D19, D19, D1

0x4c4c58 STR	D19, [X19, X3,LSL #3]

0x4c4c5c CMP	X0, X18

0x4c4c60 B.EQ	4c3de4

  (2611) 0x4c4c64 ORR	X17, XZR, X0

  (2611) 0x4c4c68 ADD	X0, X0, #64

  (2611) 0x4c4c6c LDR	D31, [X17], #8

  (2611) 0x4c4c70 FABS	D2, D31

  (2611) 0x4c4c74 FADD	D19, D19, D2

  (2611) 0x4c4c78 STR	D19, [X19, X3,LSL #3]

  (2611) 0x4c4c7c LDUR	D3, [X0, #456]

  (2611) 0x4c4c80 FABS	D4, D3

  (2611) 0x4c4c84 FADD	D5, D19, D4

  (2611) 0x4c4c88 STR	D5, [X19, X3,LSL #3]

  (2611) 0x4c4c8c LDR	D7, [X17, #8]

  (2611) 0x4c4c90 FABS	D16, D7

  (2611) 0x4c4c94 FADD	D17, D5, D16

  (2611) 0x4c4c98 STR	D17, [X19, X3,LSL #3]

  (2611) 0x4c4c9c LDUR	D18, [X0, #472]

  (2611) 0x4c4ca0 FABS	D20, D18

  (2611) 0x4c4ca4 FADD	D21, D17, D20

  (2611) 0x4c4ca8 STR	D21, [X19, X3,LSL #3]

  (2611) 0x4c4cac LDUR	D27, [X0, #480]

  (2611) 0x4c4cb0 FABS	D28, D27

  (2611) 0x4c4cb4 FADD	D25, D21, D28

  (2611) 0x4c4cb8 STR	D25, [X19, X3,LSL #3]

  (2611) 0x4c4cbc LDUR	D22, [X0, #488]

  (2611) 0x4c4cc0 FABS	D23, D22

  (2611) 0x4c4cc4 FADD	D24, D25, D23

  (2611) 0x4c4cc8 STR	D24, [X19, X3,LSL #3]

  (2611) 0x4c4ccc LDUR	D30, [X0, #496]

  (2611) 0x4c4cd0 FABS	D26, D30

  (2611) 0x4c4cd4 FADD	D29, D24, D26

  (2611) 0x4c4cd8 STR	D29, [X19, X3,LSL #3]

  (2611) 0x4c4cdc LDUR	D6, [X0, #504]

  (2611) 0x4c4ce0 FABS	D0, D6

  (2611) 0x4c4ce4 FADD	D19, D29, D0

  (2611) 0x4c4ce8 STR	D19, [X19, X3,LSL #3]

  (2611) 0x4c4cec CMP	X0, X18

  (2611) 0x4c4cf0 B.NE	4c4c64

0x4c4cf4 B	4c3de4

0x4c7184 LDR	D20, [X6, X17]

0x4c7188 ADD	X0, X0, #8

0x4c718c FABS	D21, D20

0x4c7190 FADD	D19, D19, D21

0x4c7194 STR	D19, [X19, X3,LSL #3]

0x4c7198 B	4c4bfc

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3382 - 3401

--------------------------------------------------------------------------------

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

[...]

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.65
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.34
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.38
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	12.19
CQA cycles if fully vectorized	7.69
Front-end cycles	15.38
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.17
P5 cycles	8.17
P6 cycles	8.08
P7 cycles	8.08
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	11.17
P13 cycles	10.83
P14 cycles	11.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	123.00
Nb uops	123.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.91
Nb FLOP add-sub	14.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.17
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.65
CQA speedup if FP arith vectorized	1.26
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.34
Bottlenecks	micro-operation queue,
Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source	ams.c:3382-3384,ams.c:3388-3394,ams.c:3401-3401
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.38
CQA cycles if no scalar integer	9.33
CQA cycles if FP arith vectorized	12.19
CQA cycles if fully vectorized	7.69
Front-end cycles	15.38
P0 cycles	11.50
P1 cycles	11.50
P2 cycles	8.25
P3 cycles	8.25
P4 cycles	8.17
P5 cycles	8.17
P6 cycles	8.08
P7 cycles	8.08
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	11.17
P13 cycles	10.83
P14 cycles	11.00
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	123.00
Nb uops	123.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.91
Nb FLOP add-sub	14.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.17
Bytes prefetched	0.00
Bytes loaded	144.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3394,3401.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3382-3384,3388-3394,3401.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 272 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.38 to 9.33 cycles (1.65x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 15.38 to 7.69 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

14: addition or subtraction

The binary loop is loading 144 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	123
loop length	492
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	8.25	8.25	8.17	8.17	8.08	8.08	11.00	11.00	11.00	11.00	11.17	10.83	11.00	0.50	0.50
cycles	11.50	11.50	8.25	8.25	8.17	8.17	8.08	8.08	11.00	11.00	11.00	11.00	11.17	10.83	11.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.38
Overall L1	15.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.38 cycles. At this rate:

9% of peak load performance is reached (9.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4c3e00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVI D19, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
CBNZ X4, 4c4b98 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1f18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X26, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c310c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X7, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X3, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X24, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X14, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c3ddc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x115c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X21, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X14, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D19, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
ADD X0, X21, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X16, X30, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X18, X2, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X11, X17, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3edc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x125c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3ec4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3eb4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3ea4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3e94 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3e84 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3e74 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D26, [X21, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D29, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D6, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D0, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D1, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D31, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D2, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D3, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D4, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D7, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D16, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D17, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D18, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X30, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3de0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4c3de0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X15, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c3de4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X6, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X17, X30, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X6, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X18, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X2, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X14, X11, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X16, X30, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c64 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c4c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c3c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c2c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c1c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1f9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c0c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1f8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4c7184 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D28, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D25, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D22, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D23, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D30, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D24, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D26, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D29, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D6, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X0, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3de4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4c3de4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X6, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D21, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 4c4bfc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1f7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParCSRComputeL1NormsThreads._omp_fn.0
Source file and lines	ams.c:3382-3401
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 272 paths individually, rerun with max-paths=272
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.38 to 9.33 cycles (1.65x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

14: addition or subtraction

The binary loop is loading 144 bytes. The binary loop is storing 120 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	123
loop length	492
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	8.25	8.25	8.17	8.17	8.08	8.08	11.00	11.00	11.00	11.00	11.17	10.83	11.00	0.50	0.50
cycles	11.50	11.50	8.25	8.25	8.17	8.17	8.08	8.08	11.00	11.00	11.00	11.00	11.17	10.83	11.00	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.38
Overall L1	15.38

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.38 cycles. At this rate:

9% of peak load performance is reached (9.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (7.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4c3e00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVI D19, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
CBNZ X4, 4c4b98 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1f18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X26, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c310c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X7, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X3, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X24, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X19, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X14, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c3ddc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x115c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X21, X14,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X14, X0, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D19, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	N/A
ADD X0, X21, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X16, X30, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X18, X2, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X17, X18, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X11, X17, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3edc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x125c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3ec4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3eb4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3ea4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3e94 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3e84 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3e74 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x11f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D26, [X21, X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D29, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D6, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D0, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D1, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D31, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D31	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D2, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D3, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D4, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D5, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D7, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D16, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D16	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D17, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D18, D17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X30, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3de0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4c3de0 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X15, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4c3de4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X6, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X17, X30, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X6, X30,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X2, X18, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X2, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X14, X11, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X30, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X16, X30, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c64 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c4c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c3c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c2c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1fac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c1c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1f9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c4c0c <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1f8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4c7184 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x4504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D27, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D28, D27	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D25, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D22, D25	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D22	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D23, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D30, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D24, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D26, D24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D26	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D29, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D6, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D0, [X0], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FABS D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X0, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4c3de4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4c3de4 <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D20, [X6, X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X0, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FABS D21, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D19, D19, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D19, [X19, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 4c4bfc <hypre_ParCSRComputeL1NormsThreads._omp_fn.0+0x1f7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code