OV - exec - Function hypre_SeqVectorAxpy._omp

	Function: hypre_SeqVectorAxpy._omp_fn.0	Module: exec	Source: vector.c:449-452	Coverage (incl. loops): 1.85% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 449 - 452

--------------------------------------------------------------------------------

449: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

450: #endif

451:    for (i = 0; i < size; i++)

452:       y_data[i] += alpha * x_data[i];

0x523780 STP	X29, X30, [SP, #976]!

0x523784 ADD	X29, SP, #0

0x523788 STP	X19, X20, [SP, #16]

0x52378c ORR	X20, XZR, X0

0x523790 STR	X21, [SP, #32]

0x523794 LDR	X21, [X0, #24]

0x523798 BL	410d60

0x52379c SBFM	X19, X0, #0, #31

0x5237a0 BL	410c90

0x5237a4 SBFM	X1, X0, #0, #31

0x5237a8 SDIV	X4, X21, X19

0x5237ac MSUB	X2, X4, X19, X21

0x5237b0 CMP	X1, X2

0x5237b4 B.LT	5239b8

(4009) 0x5237b8 MADD	X1, X4, X1, X2

(4009) 0x5237bc ADD	X0, X4, X1

(4009) 0x5237c0 CMP	X1, X0

(4009) 0x5237c4 B.GE	5239a8

(4009) 0x5237c8 SUB	X3, X4, #1

(4009) 0x5237cc LDR	D31, [X20]

(4009) 0x5237d0 LDP	X8, X6, [X20, #8]

(4009) 0x5237d4 CMP	X3, #1

(4009) 0x5237d8 B.LS	5239c4

(4009) 0x5237dc UBFM	X9, X1, #61, #60

(4009) 0x5237e0 ADD	X15, X6, X1,LSL #3

(4009) 0x5237e4 ADD	X5, X9, #8

(4009) 0x5237e8 ADD	X7, X8, X5

(4009) 0x5237ec CMP	X15, X7

(4009) 0x5237f0 B.EQ	5239c4

(4009) 0x5237f4 UBFM	X10, X4, #1, #63

(4009) 0x5237f8 DUP	V30.2D, V31.D[0]

(4009) 0x5237fc ADD	X16, X8, X9

(4009) 0x523800 UBFM	X17, X10, #60, #59

(4009) 0x523804 MOVZ	X18, #0

(4009) 0x523808 SUB	X11, X17, #16

(4009) 0x52380c UBFM	X12, X11, #4, #63

(4009) 0x523810 ADD	X13, X12, #1

(4009) 0x523814 ANDS	X14, X13, #4224

(4009) 0x523818 B.EQ	5238e0

(4009) 0x52381c CMP	X14, #1

(4009) 0x523820 B.EQ	5238c4

(4009) 0x523824 CMP	X14, #2

(4009) 0x523828 B.EQ	5238b0

(4009) 0x52382c CMP	X14, #3

(4009) 0x523830 B.EQ	52389c

(4009) 0x523834 CMP	X14, #4

(4009) 0x523838 B.EQ	523888

(4009) 0x52383c CMP	X14, #5

(4009) 0x523840 B.EQ	523874

(4009) 0x523844 CMP	X14, #6

(4009) 0x523848 B.EQ	523860

(4009) 0x52384c LDR	Q22, [X15]

(4009) 0x523850 MOVZ	X18, #16

(4009) 0x523854 LDR	Q23, [X16]

(4009) 0x523858 FMLA	V22.2D, V23.2D, V30.2D

(4009) 0x52385c STR	Q22, [X15]

(4009) 0x523860 LDR	Q21, [X16, X18]

(4009) 0x523864 LDR	Q20, [X15, X18]

(4009) 0x523868 FMLA	V20.2D, V21.2D, V30.2D

(4009) 0x52386c STR	Q20, [X15, X18]

(4009) 0x523870 ADD	X18, X18, #16

(4009) 0x523874 LDR	Q19, [X16, X18]

(4009) 0x523878 LDR	Q18, [X15, X18]

(4009) 0x52387c FMLA	V18.2D, V19.2D, V30.2D

(4009) 0x523880 STR	Q18, [X15, X18]

(4009) 0x523884 ADD	X18, X18, #16

(4009) 0x523888 LDR	Q17, [X16, X18]

(4009) 0x52388c LDR	Q16, [X15, X18]

(4009) 0x523890 FMLA	V16.2D, V17.2D, V30.2D

(4009) 0x523894 STR	Q16, [X15, X18]

(4009) 0x523898 ADD	X18, X18, #16

(4009) 0x52389c LDR	Q7, [X16, X18]

(4009) 0x5238a0 LDR	Q6, [X15, X18]

(4009) 0x5238a4 FMLA	V6.2D, V7.2D, V30.2D

(4009) 0x5238a8 STR	Q6, [X15, X18]

(4009) 0x5238ac ADD	X18, X18, #16

(4009) 0x5238b0 LDR	Q5, [X16, X18]

(4009) 0x5238b4 LDR	Q4, [X15, X18]

(4009) 0x5238b8 FMLA	V4.2D, V5.2D, V30.2D

(4009) 0x5238bc STR	Q4, [X15, X18]

(4009) 0x5238c0 ADD	X18, X18, #16

(4009) 0x5238c4 LDR	Q3, [X16, X18]

(4009) 0x5238c8 LDR	Q2, [X15, X18]

(4009) 0x5238cc FMLA	V2.2D, V3.2D, V30.2D

(4009) 0x5238d0 STR	Q2, [X15, X18]

(4009) 0x5238d4 ADD	X18, X18, #16

(4009) 0x5238d8 CMP	X18, X17

(4009) 0x5238dc B.EQ	523988

  (4011) 0x5238e0 LDR	Q1, [X16, X18]

  (4011) 0x5238e4 ADD	X30, X18, #16

  (4011) 0x5238e8 ADD	X21, X18, #32

  (4011) 0x5238ec ADD	X20, X18, #48

  (4011) 0x5238f0 ADD	X19, X18, #64

  (4011) 0x5238f4 LDR	Q0, [X15, X18]

  (4011) 0x5238f8 ADD	X2, X18, #80

  (4011) 0x5238fc ADD	X0, X18, #96

  (4011) 0x523900 ADD	X3, X18, #112

  (4011) 0x523904 FMLA	V0.2D, V1.2D, V30.2D

  (4011) 0x523908 STR	Q0, [X15, X18]

  (4011) 0x52390c ADD	X18, X18, #128

  (4011) 0x523910 LDR	Q29, [X16, X30]

  (4011) 0x523914 LDR	Q28, [X15, X30]

  (4011) 0x523918 FMLA	V28.2D, V29.2D, V30.2D

  (4011) 0x52391c STR	Q28, [X15, X30]

  (4011) 0x523920 LDR	Q27, [X16, X21]

  (4011) 0x523924 LDR	Q26, [X15, X21]

  (4011) 0x523928 FMLA	V26.2D, V27.2D, V30.2D

  (4011) 0x52392c STR	Q26, [X15, X21]

  (4011) 0x523930 LDR	Q25, [X16, X20]

  (4011) 0x523934 LDR	Q24, [X15, X20]

  (4011) 0x523938 FMLA	V24.2D, V25.2D, V30.2D

  (4011) 0x52393c STR	Q24, [X15, X20]

  (4011) 0x523940 LDR	Q23, [X16, X19]

  (4011) 0x523944 LDR	Q22, [X15, X19]

  (4011) 0x523948 FMLA	V22.2D, V23.2D, V30.2D

  (4011) 0x52394c STR	Q22, [X15, X19]

  (4011) 0x523950 LDR	Q21, [X16, X2]

  (4011) 0x523954 LDR	Q20, [X15, X2]

  (4011) 0x523958 FMLA	V20.2D, V21.2D, V30.2D

  (4011) 0x52395c STR	Q20, [X15, X2]

  (4011) 0x523960 LDR	Q19, [X16, X0]

  (4011) 0x523964 LDR	Q18, [X15, X0]

  (4011) 0x523968 FMLA	V18.2D, V19.2D, V30.2D

  (4011) 0x52396c STR	Q18, [X15, X0]

  (4011) 0x523970 LDR	Q17, [X16, X3]

  (4011) 0x523974 LDR	Q16, [X15, X3]

  (4011) 0x523978 FMLA	V16.2D, V17.2D, V30.2D

  (4011) 0x52397c STR	Q16, [X15, X3]

  (4011) 0x523980 CMP	X18, X17

  (4011) 0x523984 B.NE	5238e0

(4009) 0x523988 AND	X9, X4, #8127

(4009) 0x52398c TBZ	W4, #0, 5239a8

(4009) 0x523990 ADD	X1, X1, X9

(4009) 0x523994 UBFM	X4, X1, #61, #60

(4009) 0x523998 LDR	D30, [X8, X4]

(4009) 0x52399c LDR	D7, [X6, X4]

(4009) 0x5239a0 FMADD	D31, D31, D30, D7

(4009) 0x5239a4 STR	D31, [X6, X4]

(4009) 0x5239a8 LDR	X21, [SP, #32]

(4009) 0x5239ac LDP	X19, X20, [SP, #16]

(4009) 0x5239b0 LDP	X29, X30, [SP], #48

(4009) 0x5239b4 RET

(4009) 0x5239b8 ADD	X4, X4, #1

(4009) 0x5239bc MOVZ	X2, #0

(4009) 0x5239c0 B	5237b8

(4009) 0x5239c4 SUB	X15, X0, X1

(4009) 0x5239c8 ANDS	X5, X15, #4224

(4009) 0x5239cc B.EQ	523a94

(4009) 0x5239d0 CMP	X5, #1

(4009) 0x5239d4 B.EQ	523a78

(4009) 0x5239d8 CMP	X5, #2

(4009) 0x5239dc B.EQ	523a64

(4009) 0x5239e0 CMP	X5, #3

(4009) 0x5239e4 B.EQ	523a50

(4009) 0x5239e8 CMP	X5, #4

(4009) 0x5239ec B.EQ	523a3c

(4009) 0x5239f0 CMP	X5, #5

(4009) 0x5239f4 B.EQ	523a28

(4009) 0x5239f8 CMP	X5, #6

(4009) 0x5239fc B.EQ	523a14

(4009) 0x523a00 LDR	D6, [X8, X1,LSL #3]

(4009) 0x523a04 LDR	D5, [X6, X1,LSL #3]

(4009) 0x523a08 FMADD	D4, D31, D6, D5

(4009) 0x523a0c STR	D4, [X6, X1,LSL #3]

(4009) 0x523a10 ADD	X1, X1, #1

(4009) 0x523a14 LDR	D3, [X8, X1,LSL #3]

(4009) 0x523a18 LDR	D2, [X6, X1,LSL #3]

(4009) 0x523a1c FMADD	D1, D31, D3, D2

(4009) 0x523a20 STR	D1, [X6, X1,LSL #3]

(4009) 0x523a24 ADD	X1, X1, #1

(4009) 0x523a28 LDR	D29, [X8, X1,LSL #3]

(4009) 0x523a2c LDR	D0, [X6, X1,LSL #3]

(4009) 0x523a30 FMADD	D28, D31, D29, D0

(4009) 0x523a34 STR	D28, [X6, X1,LSL #3]

(4009) 0x523a38 ADD	X1, X1, #1

(4009) 0x523a3c LDR	D27, [X8, X1,LSL #3]

(4009) 0x523a40 LDR	D26, [X6, X1,LSL #3]

(4009) 0x523a44 FMADD	D25, D31, D27, D26

(4009) 0x523a48 STR	D25, [X6, X1,LSL #3]

(4009) 0x523a4c ADD	X1, X1, #1

(4009) 0x523a50 LDR	D24, [X8, X1,LSL #3]

(4009) 0x523a54 LDR	D23, [X6, X1,LSL #3]

(4009) 0x523a58 FMADD	D22, D31, D24, D23

(4009) 0x523a5c STR	D22, [X6, X1,LSL #3]

(4009) 0x523a60 ADD	X1, X1, #1

(4009) 0x523a64 LDR	D21, [X8, X1,LSL #3]

(4009) 0x523a68 LDR	D20, [X6, X1,LSL #3]

(4009) 0x523a6c FMADD	D19, D31, D21, D20

(4009) 0x523a70 STR	D19, [X6, X1,LSL #3]

(4009) 0x523a74 ADD	X1, X1, #1

(4009) 0x523a78 LDR	D18, [X8, X1,LSL #3]

(4009) 0x523a7c LDR	D17, [X6, X1,LSL #3]

(4009) 0x523a80 FMADD	D16, D31, D18, D17

(4009) 0x523a84 STR	D16, [X6, X1,LSL #3]

(4009) 0x523a88 ADD	X1, X1, #1

(4009) 0x523a8c CMP	X0, X1

(4009) 0x523a90 B.EQ	5239a8

  (4010) 0x523a94 LDR	D30, [X8, X1,LSL #3]

  (4010) 0x523a98 ADD	X16, X1, #1

  (4010) 0x523a9c ADD	X10, X1, #2

  (4010) 0x523aa0 ADD	X17, X1, #3

  (4010) 0x523aa4 ADD	X7, X1, #4

  (4010) 0x523aa8 LDR	D7, [X6, X1,LSL #3]

  (4010) 0x523aac ADD	X11, X1, #5

  (4010) 0x523ab0 ADD	X12, X1, #6

  (4010) 0x523ab4 ADD	X13, X1, #7

  (4010) 0x523ab8 FMADD	D6, D31, D30, D7

  (4010) 0x523abc STR	D6, [X6, X1,LSL #3]

  (4010) 0x523ac0 ADD	X1, X1, #8

  (4010) 0x523ac4 LDR	D5, [X8, X16,LSL #3]

  (4010) 0x523ac8 LDR	D4, [X6, X16,LSL #3]

  (4010) 0x523acc FMADD	D3, D31, D5, D4

  (4010) 0x523ad0 STR	D3, [X6, X16,LSL #3]

  (4010) 0x523ad4 LDR	D2, [X8, X10,LSL #3]

  (4010) 0x523ad8 LDR	D1, [X6, X10,LSL #3]

  (4010) 0x523adc FMADD	D29, D31, D2, D1

  (4010) 0x523ae0 STR	D29, [X6, X10,LSL #3]

  (4010) 0x523ae4 LDR	D0, [X8, X17,LSL #3]

  (4010) 0x523ae8 LDR	D28, [X6, X17,LSL #3]

  (4010) 0x523aec FMADD	D27, D31, D0, D28

  (4010) 0x523af0 STR	D27, [X6, X17,LSL #3]

  (4010) 0x523af4 LDR	D26, [X8, X7,LSL #3]

  (4010) 0x523af8 LDR	D25, [X6, X7,LSL #3]

  (4010) 0x523afc FMADD	D24, D31, D26, D25

  (4010) 0x523b00 STR	D24, [X6, X7,LSL #3]

  (4010) 0x523b04 LDR	D23, [X8, X11,LSL #3]

  (4010) 0x523b08 LDR	D22, [X6, X11,LSL #3]

  (4010) 0x523b0c FMADD	D21, D31, D23, D22

  (4010) 0x523b10 STR	D21, [X6, X11,LSL #3]

  (4010) 0x523b14 LDR	D20, [X8, X12,LSL #3]

  (4010) 0x523b18 LDR	D19, [X6, X12,LSL #3]

  (4010) 0x523b1c FMADD	D18, D31, D20, D19

  (4010) 0x523b20 STR	D18, [X6, X12,LSL #3]

  (4010) 0x523b24 LDR	D17, [X8, X13,LSL #3]

  (4010) 0x523b28 LDR	D16, [X6, X13,LSL #3]

  (4010) 0x523b2c FMADD	D30, D31, D17, D16

  (4010) 0x523b30 STR	D30, [X6, X13,LSL #3]

  (4010) 0x523b34 CMP	X0, X1

  (4010) 0x523b38 B.NE	523a94

(4009) 0x523b3c B	5239a8

Coverage (%)	Name	Source Location	Module
►98.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	vector.c:449-452
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449-452.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 523780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X4, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X4, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 5239b8 <hypre_SeqVectorAxpy._omp_fn.0+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	vector.c:449-452
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449-452.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 523780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X4, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X4, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 5239b8 <hypre_SeqVectorAxpy._omp_fn.0+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorAxpy._omp_fn.0–	1.85	0.30
▼Loop 4009 - vector.c:449-452 - exec–	0.00	0.00
○Loop 4011 - vector.c:452-452 - exec	1.85	0.23
○Loop 4010 - vector.c:452-452 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code