OV - exec - Function hypre_SeqVectorScale._omp

	Function: hypre_SeqVectorScale._omp_fn.0	Module: exec	Source: vector.c:413-416	Coverage (incl. loops): 0.35% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 413 - 416

--------------------------------------------------------------------------------

413: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

414: #endif

415:    for (i = 0; i < size; i++)

416:       y_data[i] *= alpha;

0x52354c STP	X29, X30, [SP, #976]!

0x523550 ADD	X29, SP, #0

0x523554 STP	X19, X20, [SP, #16]

0x523558 ORR	X20, XZR, X0

0x52355c STR	X21, [SP, #32]

0x523560 LDR	X21, [X0, #16]

0x523564 BL	410d60

0x523568 SBFM	X19, X0, #0, #31

0x52356c BL	410c90

0x523570 SBFM	X2, X0, #0, #31

0x523574 SDIV	X3, X21, X19

0x523578 MSUB	X1, X3, X19, X21

0x52357c CMP	X2, X1

0x523580 B.LT	523774

(4007) 0x523584 MADD	X16, X3, X2, X1

(4007) 0x523588 ADD	X5, X3, X16

(4007) 0x52358c CMP	X16, X5

(4007) 0x523590 B.GE	523764

(4007) 0x523594 SUB	X0, X3, #1

(4007) 0x523598 LDR	D31, [X20]

(4007) 0x52359c LDR	X6, [X20, #8]

(4007) 0x5235a0 CMP	X0, #2

(4007) 0x5235a4 B.LS	52371c

(4007) 0x5235a8 UBFM	X4, X3, #2, #63

(4007) 0x5235ac ADD	X14, X6, X16,LSL #3

(4007) 0x5235b0 DUP	V30.2D, V31.D[0]

(4007) 0x5235b4 UBFM	X7, X4, #59, #58

(4007) 0x5235b8 SUB	X8, X7, #32

(4007) 0x5235bc ADD	X9, X14, X4,LSL #5

(4007) 0x5235c0 UBFM	X10, X8, #5, #63

(4007) 0x5235c4 ADD	X11, X10, #1

(4007) 0x5235c8 ANDS	X12, X11, #4224

(4007) 0x5235cc B.EQ	523678

(4007) 0x5235d0 CMP	X12, #1

(4007) 0x5235d4 B.EQ	523660

(4007) 0x5235d8 CMP	X12, #2

(4007) 0x5235dc B.EQ	523650

(4007) 0x5235e0 CMP	X12, #3

(4007) 0x5235e4 B.EQ	523640

(4007) 0x5235e8 CMP	X12, #4

(4007) 0x5235ec B.EQ	523630

(4007) 0x5235f0 CMP	X12, #5

(4007) 0x5235f4 B.EQ	523620

(4007) 0x5235f8 CMP	X12, #6

(4007) 0x5235fc B.EQ	523610

(4007) 0x523600 LDP	Q7, Q16, [X14]

(4007) 0x523604 FMUL	V0.2D, V7.2D, V30.2D

(4007) 0x523608 FMUL	V1.2D, V16.2D, V30.2D

(4007) 0x52360c STP	Q0, Q1, [X14], #32

(4007) 0x523610 LDP	Q5, Q6, [X14]

(4007) 0x523614 FMUL	V2.2D, V5.2D, V30.2D

(4007) 0x523618 FMUL	V3.2D, V6.2D, V30.2D

(4007) 0x52361c STP	Q2, Q3, [X14], #32

(4007) 0x523620 LDP	Q17, Q4, [X14]

(4007) 0x523624 FMUL	V18.2D, V17.2D, V30.2D

(4007) 0x523628 FMUL	V19.2D, V4.2D, V30.2D

(4007) 0x52362c STP	Q18, Q19, [X14], #32

(4007) 0x523630 LDP	Q20, Q29, [X14]

(4007) 0x523634 FMUL	V21.2D, V20.2D, V30.2D

(4007) 0x523638 FMUL	V22.2D, V29.2D, V30.2D

(4007) 0x52363c STP	Q21, Q22, [X14], #32

(4007) 0x523640 LDP	Q28, Q23, [X14]

(4007) 0x523644 FMUL	V24.2D, V28.2D, V30.2D

(4007) 0x523648 FMUL	V25.2D, V23.2D, V30.2D

(4007) 0x52364c STP	Q24, Q25, [X14], #32

(4007) 0x523650 LDP	Q27, Q26, [X14]

(4007) 0x523654 FMUL	V7.2D, V27.2D, V30.2D

(4007) 0x523658 FMUL	V16.2D, V26.2D, V30.2D

(4007) 0x52365c STP	Q7, Q16, [X14], #32

(4007) 0x523660 LDP	Q0, Q1, [X14]

(4007) 0x523664 FMUL	V5.2D, V0.2D, V30.2D

(4007) 0x523668 FMUL	V6.2D, V1.2D, V30.2D

(4007) 0x52366c STP	Q5, Q6, [X14], #32

(4007) 0x523670 CMP	X14, X9

(4007) 0x523674 B.EQ	52370c

  (4008) 0x523678 LDP	Q2, Q3, [X14]

  (4008) 0x52367c ORR	X13, XZR, X14

  (4008) 0x523680 LDP	Q28, Q18, [X14, #96]

  (4008) 0x523684 LDP	Q21, Q22, [X14, #32]

  (4008) 0x523688 LDP	Q19, Q20, [X14, #64]

  (4008) 0x52368c LDP	Q23, Q24, [X14, #128]

  (4008) 0x523690 FMUL	V17.2D, V2.2D, V30.2D

  (4008) 0x523694 LDP	Q25, Q27, [X14, #160]

  (4008) 0x523698 FMUL	V4.2D, V3.2D, V30.2D

  (4008) 0x52369c LDP	Q26, Q0, [X14, #192]

  (4008) 0x5236a0 FMUL	V21.2D, V21.2D, V30.2D

  (4008) 0x5236a4 LDP	Q1, Q29, [X14, #224]

  (4008) 0x5236a8 ADD	X14, X14, #256

  (4008) 0x5236ac FMUL	V22.2D, V22.2D, V30.2D

  (4008) 0x5236b0 FMUL	V19.2D, V19.2D, V30.2D

  (4008) 0x5236b4 FMUL	V20.2D, V20.2D, V30.2D

  (4008) 0x5236b8 FMUL	V7.2D, V23.2D, V30.2D

  (4008) 0x5236bc FMUL	V16.2D, V24.2D, V30.2D

  (4008) 0x5236c0 FMUL	V5.2D, V25.2D, V30.2D

  (4008) 0x5236c4 FMUL	V6.2D, V27.2D, V30.2D

  (4008) 0x5236c8 FMUL	V3.2D, V26.2D, V30.2D

  (4008) 0x5236cc FMUL	V2.2D, V1.2D, V30.2D

  (4008) 0x5236d0 STP	Q17, Q4, [X14, #1792]

  (4008) 0x5236d4 FMUL	V17.2D, V28.2D, V30.2D

  (4008) 0x5236d8 FMUL	V4.2D, V0.2D, V30.2D

  (4008) 0x5236dc FMUL	V28.2D, V18.2D, V30.2D

  (4008) 0x5236e0 STUR	Q2, [X14, #480]

  (4008) 0x5236e4 FMUL	V18.2D, V29.2D, V30.2D

  (4008) 0x5236e8 STP	Q21, Q22, [X14, #1824]

  (4008) 0x5236ec STP	Q19, Q20, [X14, #1856]

  (4008) 0x5236f0 STP	Q17, Q28, [X14, #1888]

  (4008) 0x5236f4 STP	Q7, Q16, [X14, #1920]

  (4008) 0x5236f8 STP	Q5, Q6, [X14, #1952]

  (4008) 0x5236fc STP	Q3, Q4, [X14, #1984]

  (4008) 0x523700 STR	Q18, [X13, #240]

  (4008) 0x523704 CMP	X14, X9

  (4008) 0x523708 B.NE	523678

(4007) 0x52370c AND	X15, X3, #8062

(4007) 0x523710 ADD	X16, X16, X15

(4007) 0x523714 CMP	X3, X15

(4007) 0x523718 B.EQ	523764

(4007) 0x52371c UBFM	X17, X16, #61, #60

(4007) 0x523720 ADD	X18, X16, #1

(4007) 0x523724 LDR	D30, [X6, X17]

(4007) 0x523728 FMUL	D23, D30, D31

(4007) 0x52372c STR	D23, [X6, X17]

(4007) 0x523730 CMP	X5, X18

(4007) 0x523734 B.LE	523764

(4007) 0x523738 ADD	X30, X17, #8

(4007) 0x52373c ADD	X20, X16, #2

(4007) 0x523740 LDR	D24, [X6, X30]

(4007) 0x523744 FMUL	D25, D24, D31

(4007) 0x523748 STR	D25, [X6, X30]

(4007) 0x52374c CMP	X5, X20

(4007) 0x523750 B.LE	523764

(4007) 0x523754 ADD	X21, X17, #16

(4007) 0x523758 LDR	D27, [X6, X21]

(4007) 0x52375c FMUL	D31, D27, D31

(4007) 0x523760 STR	D31, [X6, X21]

(4007) 0x523764 LDR	X21, [SP, #32]

(4007) 0x523768 LDP	X19, X20, [SP, #16]

(4007) 0x52376c LDP	X29, X30, [SP], #48

(4007) 0x523770 RET

(4007) 0x523774 ADD	X3, X3, #1

(4007) 0x523778 MOVZ	X1, #0

(4007) 0x52377c B	523584

Coverage (%)	Name	Source Location	Module
►98.81+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.07+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_SeqVectorScale	vector.c:413	exec
○	hypre_PCGSolve	pcg.c:709	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 52354c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X1, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 523774 <hypre_SeqVectorScale._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 52354c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X2, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X1, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X2, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 523774 <hypre_SeqVectorScale._omp_fn.0+0x228>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorScale._omp_fn.0–	0.35	0.06
▼Loop 4007 - vector.c:413-416 - exec–	0.00	0.00
○Loop 4008 - vector.c:416-416 - exec	0.35	0.04

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code