OV - exec - Function hypre_SeqVectorSetConstantValues._omp

	Function: hypre_SeqVectorSetConstantValues._omp_fn.0	Module: exec	Source: vector.c:268-271	Coverage (incl. loops): 0.21% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 268 - 271

--------------------------------------------------------------------------------

268: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

269: #endif

270:    for (i = 0; i < size; i++)

271:       vector_data[i] = value;

0x523000 STP	X29, X30, [SP, #976]!

0x523004 ADD	X29, SP, #0

0x523008 STP	X19, X20, [SP, #16]

0x52300c ORR	X20, XZR, X0

0x523010 STR	X21, [SP, #32]

0x523014 LDR	X21, [X0, #16]

0x523018 BL	410d60

0x52301c SBFM	X19, X0, #0, #31

0x523020 BL	410c90

0x523024 SBFM	X1, X0, #0, #31

0x523028 SDIV	X3, X21, X19

0x52302c MSUB	X2, X3, X19, X21

0x523030 CMP	X1, X2

0x523034 B.LT	5231a8

(4002) 0x523038 MADD	X16, X3, X1, X2

(4002) 0x52303c ADD	X4, X3, X16

(4002) 0x523040 CMP	X16, X4

(4002) 0x523044 B.GE	523198

(4002) 0x523048 SUB	X0, X3, #1

(4002) 0x52304c LDR	D30, [X20]

(4002) 0x523050 LDR	X5, [X20, #8]

(4002) 0x523054 CMP	X0, #7

(4002) 0x523058 B.LS	52311c

(4002) 0x52305c UBFM	X6, X3, #2, #63

(4002) 0x523060 ADD	X14, X5, X16,LSL #3

(4002) 0x523064 DUP	V31.2D, V30.D[0]

(4002) 0x523068 UBFM	X7, X6, #59, #58

(4002) 0x52306c SUB	X8, X7, #32

(4002) 0x523070 ADD	X9, X14, X6,LSL #5

(4002) 0x523074 UBFM	X10, X8, #5, #63

(4002) 0x523078 ADD	X11, X10, #1

(4002) 0x52307c ANDS	X12, X11, #4224

(4002) 0x523080 B.EQ	5230d8

(4002) 0x523084 CMP	X12, #1

(4002) 0x523088 B.EQ	5230cc

(4002) 0x52308c CMP	X12, #2

(4002) 0x523090 B.EQ	5230c8

(4002) 0x523094 CMP	X12, #3

(4002) 0x523098 B.EQ	5230c4

(4002) 0x52309c CMP	X12, #4

(4002) 0x5230a0 B.EQ	5230c0

(4002) 0x5230a4 CMP	X12, #5

(4002) 0x5230a8 B.EQ	5230bc

(4002) 0x5230ac CMP	X12, #6

(4002) 0x5230b0 B.EQ	5230b8

(4002) 0x5230b4 STP	Q31, Q31, [X14], #32

(4002) 0x5230b8 STP	Q31, Q31, [X14], #32

(4002) 0x5230bc STP	Q31, Q31, [X14], #32

(4002) 0x5230c0 STP	Q31, Q31, [X14], #32

(4002) 0x5230c4 STP	Q31, Q31, [X14], #32

(4002) 0x5230c8 STP	Q31, Q31, [X14], #32

(4002) 0x5230cc STP	Q31, Q31, [X14], #32

(4002) 0x5230d0 CMP	X9, X14

(4002) 0x5230d4 B.EQ	52310c

  (4003) 0x5230d8 ADD	X13, X14, #32

  (4003) 0x5230dc STR	Q31, [X14, #32]

  (4003) 0x5230e0 ADD	X14, X14, #256

  (4003) 0x5230e4 STP	Q31, Q31, [X14, #1792]

  (4003) 0x5230e8 STP	Q31, Q31, [X13, #16]

  (4003) 0x5230ec STUR	Q31, [X14, #336]

  (4003) 0x5230f0 STP	Q31, Q31, [X14, #1888]

  (4003) 0x5230f4 STP	Q31, Q31, [X14, #1920]

  (4003) 0x5230f8 STP	Q31, Q31, [X14, #1952]

  (4003) 0x5230fc STP	Q31, Q31, [X14, #1984]

  (4003) 0x523100 STP	Q31, Q31, [X14, #2016]

  (4003) 0x523104 CMP	X9, X14

  (4003) 0x523108 B.NE	5230d8

(4002) 0x52310c AND	X15, X3, #8062

(4002) 0x523110 ADD	X16, X16, X15

(4002) 0x523114 CMP	X3, X15

(4002) 0x523118 B.EQ	523198

(4002) 0x52311c UBFM	X17, X16, #61, #60

(4002) 0x523120 ADD	X18, X16, #1

(4002) 0x523124 STR	D30, [X5, X17]

(4002) 0x523128 CMP	X4, X18

(4002) 0x52312c B.LE	523198

(4002) 0x523130 ADD	X30, X5, X17

(4002) 0x523134 ADD	X20, X16, #2

(4002) 0x523138 STR	D30, [X30, #8]

(4002) 0x52313c CMP	X4, X20

(4002) 0x523140 B.LE	523198

(4002) 0x523144 ADD	X21, X16, #3

(4002) 0x523148 STR	D30, [X30, #16]

(4002) 0x52314c CMP	X4, X21

(4002) 0x523150 B.LE	523198

(4002) 0x523154 ADD	X19, X16, #4

(4002) 0x523158 STR	D30, [X30, #24]

(4002) 0x52315c CMP	X4, X19

(4002) 0x523160 B.LE	523198

(4002) 0x523164 ADD	X1, X16, #5

(4002) 0x523168 STR	D30, [X30, #32]

(4002) 0x52316c CMP	X4, X1

(4002) 0x523170 B.LE	523198

(4002) 0x523174 ADD	X3, X16, #6

(4002) 0x523178 STR	D30, [X30, #40]

(4002) 0x52317c CMP	X4, X3

(4002) 0x523180 B.LE	523198

(4002) 0x523184 ADD	X2, X16, #7

(4002) 0x523188 STR	D30, [X30, #48]

(4002) 0x52318c CMP	X4, X2

(4002) 0x523190 B.LE	523198

(4002) 0x523194 STR	D30, [X30, #56]

(4002) 0x523198 LDR	X21, [SP, #32]

(4002) 0x52319c LDP	X19, X20, [SP, #16]

(4002) 0x5231a0 LDP	X29, X30, [SP], #48

(4002) 0x5231a4 RET

(4002) 0x5231a8 ADD	X3, X3, #1

(4002) 0x5231ac MOVZ	X2, #0

(4002) 0x5231b0 B	523038

0x5231b4 HINT	#0

0x5231b8 HINT	#0

0x5231bc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.41+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	vector.c:268-271
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:268-271.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 523000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 5231a8 <hypre_SeqVectorSetConstantValues._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	vector.c:268-271
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/vector.c:268-271.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 523000

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 5231a8 <hypre_SeqVectorSetConstantValues._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorSetConstantValues._omp_fn.0–	0.21	0.03
▼Loop 4002 - vector.c:268-271 - exec–	0.00	0.00
○Loop 4003 - vector.c:271-271 - exec	0.21	0.03

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code