OV - exec - Function hypre_CSRMatrixMatvecT._omp

	Function: hypre_CSRMatrixMatvecT._omp_fn.3	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage (incl. loops): 1.28% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

[...]

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x5206c4 STP	X29, X30, [SP, #912]!

0x5206c8 ADD	X29, SP, #0

0x5206cc STP	X19, X20, [SP, #16]

0x5206d0 STP	X21, X22, [SP, #32]

0x5206d4 STP	X23, X24, [SP, #48]

0x5206d8 STP	X25, X26, [SP, #64]

0x5206dc STP	X27, X28, [SP, #80]

0x5206e0 LDP	X28, X7, [X0]

0x5206e4 LDR	X26, [X0, #64]

0x5206e8 STR	X7, [SP, #104]

0x5206ec LDP	X27, X20, [X0, #16]

0x5206f0 LDP	X25, X23, [X0, #32]

0x5206f4 LDP	X22, X19, [X0, #48]

0x5206f8 BL	52df60

0x5206fc ORR	X24, XZR, X0

0x520700 BL	410d60

0x520704 SBFM	X21, X0, #0, #31

0x520708 BL	410c90

0x52070c SDIV	X12, X20, X21

0x520710 SBFM	X0, X0, #0, #31

0x520714 LDR	X14, [SP, #104]

0x520718 MSUB	X2, X12, X21, X20

0x52071c CMP	X0, X2

0x520720 B.LT	520a58

0x520724 MADD	X2, X12, X0, X2

0x520728 ADD	X15, X12, X2

0x52072c CMP	X2, X15

0x520730 B.GE	520884

0x520734 MADD	X16, X22, X24, XZR

0x520738 ADD	X13, X14, #8

0x52073c HINT	#0

(3961) 0x520740 LDR	X1, [X14, X2,LSL #3]

(3961) 0x520744 LDR	X11, [X13, X2,LSL #3]

(3961) 0x520748 CMP	X1, X11

(3961) 0x52074c B.GE	520878

(3961) 0x520750 SUB	X3, X11, X1

(3961) 0x520754 ANDS	X4, X3, #4160

(3961) 0x520758 B.EQ	5207e0

(3961) 0x52075c CMP	X4, #1

(3961) 0x520760 B.EQ	5207b4

(3961) 0x520764 CMP	X4, #2

(3961) 0x520768 B.EQ	520790

(3961) 0x52076c LDR	X5, [X27, X1,LSL #3]

(3961) 0x520770 LDR	D31, [X28, X1,LSL #3]

(3961) 0x520774 ADD	X1, X1, #1

(3961) 0x520778 LDR	D30, [X25, X2,LSL #3]

(3961) 0x52077c ADD	X6, X16, X5

(3961) 0x520780 UBFM	X8, X6, #61, #60

(3961) 0x520784 LDR	D29, [X19, X8]

(3961) 0x520788 FMADD	D0, D31, D30, D29

(3961) 0x52078c STR	D0, [X19, X8]

(3961) 0x520790 LDR	X9, [X27, X1,LSL #3]

(3961) 0x520794 LDR	D28, [X28, X1,LSL #3]

(3961) 0x520798 ADD	X1, X1, #1

(3961) 0x52079c LDR	D27, [X25, X2,LSL #3]

(3961) 0x5207a0 ADD	X10, X16, X9

(3961) 0x5207a4 UBFM	X17, X10, #61, #60

(3961) 0x5207a8 LDR	D26, [X19, X17]

(3961) 0x5207ac FMADD	D1, D28, D27, D26

(3961) 0x5207b0 STR	D1, [X19, X17]

(3961) 0x5207b4 LDR	X18, [X27, X1,LSL #3]

(3961) 0x5207b8 LDR	D25, [X28, X1,LSL #3]

(3961) 0x5207bc ADD	X1, X1, #1

(3961) 0x5207c0 LDR	D24, [X25, X2,LSL #3]

(3961) 0x5207c4 ADD	X30, X16, X18

(3961) 0x5207c8 UBFM	X7, X30, #61, #60

(3961) 0x5207cc LDR	D23, [X19, X7]

(3961) 0x5207d0 FMADD	D2, D25, D24, D23

(3961) 0x5207d4 STR	D2, [X19, X7]

(3961) 0x5207d8 CMP	X1, X11

(3961) 0x5207dc B.EQ	520878

  (3962) 0x5207e0 LDR	X20, [X27, X1,LSL #3]

  (3962) 0x5207e4 ADD	X24, X1, #1

  (3962) 0x5207e8 ADD	X12, X1, #3

  (3962) 0x5207ec ADD	X8, X1, #2

  (3962) 0x5207f0 LDR	D5, [X28, X1,LSL #3]

  (3962) 0x5207f4 ADD	X1, X1, #4

  (3962) 0x5207f8 LDR	D4, [X25, X2,LSL #3]

  (3962) 0x5207fc ADD	X3, X16, X20

  (3962) 0x520800 UBFM	X6, X3, #61, #60

  (3962) 0x520804 LDR	X5, [X27, X24,LSL #3]

  (3962) 0x520808 LDR	D3, [X19, X6]

  (3962) 0x52080c LDR	X4, [X27, X8,LSL #3]

  (3962) 0x520810 ADD	X9, X16, X5

  (3962) 0x520814 UBFM	X10, X9, #61, #60

  (3962) 0x520818 LDR	X17, [X27, X12,LSL #3]

  (3962) 0x52081c FMADD	D6, D5, D4, D3

  (3962) 0x520820 ADD	X18, X16, X4

  (3962) 0x520824 UBFM	X30, X18, #61, #60

  (3962) 0x520828 ADD	X7, X16, X17

  (3962) 0x52082c UBFM	X20, X7, #61, #60

  (3962) 0x520830 STR	D6, [X19, X6]

  (3962) 0x520834 LDR	D16, [X28, X24,LSL #3]

  (3962) 0x520838 LDR	D7, [X25, X2,LSL #3]

  (3962) 0x52083c LDR	D17, [X19, X10]

  (3962) 0x520840 FMADD	D18, D16, D7, D17

  (3962) 0x520844 STR	D18, [X19, X10]

  (3962) 0x520848 LDR	D19, [X28, X8,LSL #3]

  (3962) 0x52084c LDR	D20, [X25, X2,LSL #3]

  (3962) 0x520850 LDR	D21, [X19, X30]

  (3962) 0x520854 FMADD	D22, D19, D20, D21

  (3962) 0x520858 STR	D22, [X19, X30]

  (3962) 0x52085c LDR	D31, [X28, X12,LSL #3]

  (3962) 0x520860 LDR	D30, [X25, X2,LSL #3]

  (3962) 0x520864 LDR	D29, [X19, X20]

  (3962) 0x520868 FMADD	D0, D31, D30, D29

  (3962) 0x52086c STR	D0, [X19, X20]

  (3962) 0x520870 CMP	X1, X11

  (3962) 0x520874 B.NE	5207e0

(3961) 0x520878 ADD	X2, X2, #1

(3961) 0x52087c CMP	X15, X2

(3961) 0x520880 B.NE	520740

0x520884 STR	X0, [SP, #104]

0x520888 BL	410d30

0x52088c SDIV	X27, X22, X21

0x520890 LDR	X28, [SP, #104]

0x520894 MSUB	X25, X27, X21, X22

0x520898 CMP	X28, X25

0x52089c B.LT	520a4c

0x5208a0 MADD	X1, X27, X28, X25

0x5208a4 ADD	X21, X27, X1

0x5208a8 CMP	X1, X21

0x5208ac B.GE	520a30

0x5208b0 CMP	X26, #0

0x5208b4 B.LE	520a30

0x5208b8 ADD	X19, X19, X1,LSL #3

0x5208bc UBFM	X22, X22, #61, #60

(3960) 0x5208c0 ANDS	X0, X26, #4224

(3960) 0x5208c4 LDR	D2, [X23, X1,LSL #3]

(3960) 0x5208c8 ORR	X15, XZR, X19

(3960) 0x5208cc MOVZ	X14, #0

(3960) 0x5208d0 B.EQ	520998

(3960) 0x5208d4 CMP	X0, #1

(3960) 0x5208d8 B.EQ	52097c

(3960) 0x5208dc CMP	X0, #2

(3960) 0x5208e0 B.EQ	520968

(3960) 0x5208e4 CMP	X0, #3

(3960) 0x5208e8 B.EQ	520954

(3960) 0x5208ec CMP	X0, #4

(3960) 0x5208f0 B.EQ	520940

(3960) 0x5208f4 CMP	X0, #5

(3960) 0x5208f8 B.EQ	52092c

(3960) 0x5208fc CMP	X0, #6

(3960) 0x520900 B.EQ	520918

(3960) 0x520904 LDR	D28, [X19]

(3960) 0x520908 MOVZ	X14, #1

(3960) 0x52090c ADD	X15, X19, X22

(3960) 0x520910 FADD	D2, D2, D28

(3960) 0x520914 STR	D2, [X23, X1,LSL #3]

(3960) 0x520918 LDR	D27, [X15]

(3960) 0x52091c ADD	X14, X14, #1

(3960) 0x520920 ADD	X15, X15, X22

(3960) 0x520924 FADD	D2, D2, D27

(3960) 0x520928 STR	D2, [X23, X1,LSL #3]

(3960) 0x52092c LDR	D26, [X15]

(3960) 0x520930 ADD	X14, X14, #1

(3960) 0x520934 ADD	X15, X15, X22

(3960) 0x520938 FADD	D2, D2, D26

(3960) 0x52093c STR	D2, [X23, X1,LSL #3]

(3960) 0x520940 LDR	D1, [X15]

(3960) 0x520944 ADD	X14, X14, #1

(3960) 0x520948 ADD	X15, X15, X22

(3960) 0x52094c FADD	D2, D2, D1

(3960) 0x520950 STR	D2, [X23, X1,LSL #3]

(3960) 0x520954 LDR	D25, [X15]

(3960) 0x520958 ADD	X14, X14, #1

(3960) 0x52095c ADD	X15, X15, X22

(3960) 0x520960 FADD	D2, D2, D25

(3960) 0x520964 STR	D2, [X23, X1,LSL #3]

(3960) 0x520968 LDR	D24, [X15]

(3960) 0x52096c ADD	X14, X14, #1

(3960) 0x520970 ADD	X15, X15, X22

(3960) 0x520974 FADD	D2, D2, D24

(3960) 0x520978 STR	D2, [X23, X1,LSL #3]

(3960) 0x52097c LDR	D23, [X15]

(3960) 0x520980 ADD	X14, X14, #1

(3960) 0x520984 ADD	X15, X15, X22

(3960) 0x520988 FADD	D2, D2, D23

(3960) 0x52098c STR	D2, [X23, X1,LSL #3]

(3960) 0x520990 CMP	X26, X14

(3960) 0x520994 B.EQ	520a20

  (3959) 0x520998 LDR	D5, [X15]

  (3959) 0x52099c ADD	X16, X15, X22

  (3959) 0x5209a0 ADD	X13, X15, X22,LSL #1

  (3959) 0x5209a4 ADD	X14, X14, #8

  (3959) 0x5209a8 ADD	X11, X13, X22

  (3959) 0x5209ac ADD	X24, X13, X22,LSL #1

  (3959) 0x5209b0 ADD	X12, X24, X22

  (3959) 0x5209b4 ADD	X8, X24, X22,LSL #1

  (3959) 0x5209b8 FADD	D4, D2, D5

  (3959) 0x5209bc STR	D4, [X23, X1,LSL #3]

  (3959) 0x5209c0 LDR	D3, [X15, X22]

  (3959) 0x5209c4 ADD	X15, X8, X22,LSL #1

  (3959) 0x5209c8 FADD	D6, D4, D3

  (3959) 0x5209cc STR	D6, [X23, X1,LSL #3]

  (3959) 0x5209d0 LDR	D16, [X16, X22]

  (3959) 0x5209d4 FADD	D7, D6, D16

  (3959) 0x5209d8 STR	D7, [X23, X1,LSL #3]

  (3959) 0x5209dc LDR	D17, [X13, X22]

  (3959) 0x5209e0 FADD	D18, D7, D17

  (3959) 0x5209e4 STR	D18, [X23, X1,LSL #3]

  (3959) 0x5209e8 LDR	D19, [X11, X22]

  (3959) 0x5209ec FADD	D20, D18, D19

  (3959) 0x5209f0 STR	D20, [X23, X1,LSL #3]

  (3959) 0x5209f4 LDR	D21, [X24, X22]

  (3959) 0x5209f8 FADD	D22, D20, D21

  (3959) 0x5209fc STR	D22, [X23, X1,LSL #3]

  (3959) 0x520a00 LDR	D31, [X12, X22]

  (3959) 0x520a04 FADD	D30, D22, D31

  (3959) 0x520a08 STR	D30, [X23, X1,LSL #3]

  (3959) 0x520a0c LDR	D29, [X8, X22]

  (3959) 0x520a10 FADD	D2, D30, D29

  (3959) 0x520a14 STR	D2, [X23, X1,LSL #3]

  (3959) 0x520a18 CMP	X26, X14

  (3959) 0x520a1c B.NE	520998

(3960) 0x520a20 ADD	X1, X1, #1

(3960) 0x520a24 ADD	X19, X19, #8

(3960) 0x520a28 CMP	X21, X1

(3960) 0x520a2c B.NE	5208c0

0x520a30 LDP	X19, X20, [SP, #16]

0x520a34 LDP	X21, X22, [SP, #32]

0x520a38 LDP	X23, X24, [SP, #48]

0x520a3c LDP	X25, X26, [SP, #64]

0x520a40 LDP	X27, X28, [SP, #80]

0x520a44 LDP	X29, X30, [SP], #112

0x520a48 B	410d30

0x520a4c ADD	X27, X27, #1

0x520a50 MOVZ	X25, #0

0x520a54 B	5208a0

0x520a58 ADD	X12, X12, #1

0x520a5c MOVZ	X2, #0

0x520a60 B	520724

Coverage (%)	Name	Source Location	Module
►98.63+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.31+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_CSRMatrixMatvecT	csr_matvec.c:554	exec
○	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:439	exec
○	hypre_BoomerAMGCycle	par_cycle.c:434	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 69% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 40.00 to 30.00 cycles (1.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	4.67	4.50	4.67	4.67	7.00	4.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	4.67	4.50	4.67	4.67	7.00	4.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

4% of peak load performance is reached (4.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5206c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X28, X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X26, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X20, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X21, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X0, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB X2, X12, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X0, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 520a58 <hypre_CSRMatrixMatvecT._omp_fn.3+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X12, X0, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X15, X12, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 520884 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X16, X22, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X13, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X27, X22, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB X25, X27, X21, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X28, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 520a4c <hypre_CSRMatrixMatvecT._omp_fn.3+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X27, X28, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X21, X27, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X1, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 520a30 <hypre_CSRMatrixMatvecT._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 520a30 <hypre_CSRMatrixMatvecT._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X19, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X22, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 410d30 <@plt_start@+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X25, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 5208a0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 520724 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	59
loop length	236
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.00	6.00	4.67	4.50	4.67	4.67	7.00	4.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	4.67	4.50	4.67	4.67	7.00	4.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

4% of peak load performance is reached (4.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5206c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X28, X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X26, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X20, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X21, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X12, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
SBFM X0, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB X2, X12, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X0, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 520a58 <hypre_CSRMatrixMatvecT._omp_fn.3+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X2, X12, X0, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X15, X12, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 520884 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X16, X22, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X13, X14, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
STR X0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X27, X22, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MSUB X25, X27, X21, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X28, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 520a4c <hypre_CSRMatrixMatvecT._omp_fn.3+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X1, X27, X28, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X21, X27, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X1, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 520a30 <hypre_CSRMatrixMatvecT._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 520a30 <hypre_CSRMatrixMatvecT._omp_fn.3+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X19, X19, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X22, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 410d30 <@plt_start@+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X25, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 5208a0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X12, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 520724 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT._omp_fn.3–	1.28	0.21
▼Loop 3961 - csr_matvec.c:564-567 - exec–	0.84	0.10
○Loop 3962 - csr_matvec.c:564-567 - exec	0.16	0.02
▼Loop 3960 - csr_matvec.c:577-579 - exec–	0.00	0.00
○Loop 3959 - csr_matvec.c:577-579 - exec	0.29	0.04

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Vectorization

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Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code