OV - exec - Function hypre_CSRMatrixMatvecOutOfPlace._omp

	Function: hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6	Module: exec	Source: csr_matvec.c:243-404 [...]	Coverage (incl. loops): 26.00% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 243 - 404

--------------------------------------------------------------------------------

243: #pragma omp parallel private(i,jj,tempx)

244: #endif

245:       {

246:       HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

247:       HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

248:       hypre_assert(iBegin <= iEnd);

249:       hypre_assert(iBegin >= 0 && iBegin <= num_rows);

250:       hypre_assert(iEnd >= 0 && iEnd <= num_rows);

251:

252:       if (0 == temp)

253:       {

254:          if (1 == alpha) // JSP: a common path

255:          {

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

264:             }

265:          } // y = A*x

266:          else if (-1 == alpha)

267:          {

268:             for (i = iBegin; i < iEnd; i++)

269:             {

270:                tempx = 0.0;

271:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

272:                {

273:                   tempx -= A_data[jj] * x_data[A_j[jj]];

274:                }

275:                y_data[i] = tempx;

276:             }

277:          } // y = -A*x

278:          else

279:          {

280:             for (i = iBegin; i < iEnd; i++)

281:             {

282:                tempx = 0.0;

283:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

284:                {

285:                   tempx += A_data[jj] * x_data[A_j[jj]];

286:                }

287:                y_data[i] = alpha*tempx;

288:             }

289:          } // y = alpha*A*x

290:       } // temp == 0

291:       else if (-1 == temp) // beta == -alpha

292:       {

293:          if (1 == alpha) // JSP: a common path

294:          {

295:             for (i = iBegin; i < iEnd; i++)

296:             {

297:                tempx = -b_data[i];

298:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

299:                {

300:                   tempx += A_data[jj] * x_data[A_j[jj]];

301:                }

302:                y_data[i] = tempx;

303:             }

304:          } // y = A*x - y

305:          else if (-1 == alpha) // JSP: a common path

306:          {

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

315:             }

316:          } // y = -A*x + y

317:          else

318:          {

319:             for (i = iBegin; i < iEnd; i++)

320:             {

321:                tempx = -b_data[i];

322:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

323:                {

324:                   tempx += A_data[jj] * x_data[A_j[jj]];

325:                }

326:                y_data[i] = alpha*tempx;

327:             }

328:          } // y = alpha*(A*x - y)

329:       } // temp == -1

330:       else if (1 == temp)

331:       {

332:          if (1 == alpha) // JSP: a common path

333:          {

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

342:             }

343:          } // y = A*x + y

344:          else if (-1 == alpha)

345:          {

346:             for (i = iBegin; i < iEnd; i++)

347:             {

348:                tempx = -b_data[i];

349:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

350:                {

351:                   tempx -= A_data[jj] * x_data[A_j[jj]];

352:                }

353:                y_data[i] = tempx;

354:             }

355:          } // y = -A*x - y

356:          else

357:          {

358:             for (i = iBegin; i < iEnd; i++)

359:             {

360:                tempx = b_data[i];

361:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

362:                {

363:                   tempx += A_data[jj] * x_data[A_j[jj]];

364:                }

365:                y_data[i] = alpha*tempx;

[...]

371:          if (1 == alpha) // JSP: a common path

372:          {

373:             for (i = iBegin; i < iEnd; i++)

374:             {

375:                tempx = b_data[i]*temp;

376:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

377:                {

378:                   tempx += A_data[jj] * x_data[A_j[jj]];

379:                }

380:                y_data[i] = tempx;

381:             }

382:          } // y = A*x + temp*y

383:          else if (-1 == alpha)

384:          {

385:             for (i = iBegin; i < iEnd; i++)

386:             {

387:                tempx = -b_data[i]*temp;

388:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

389:                {

390:                   tempx -= A_data[jj] * x_data[A_j[jj]];

391:                }

392:                y_data[i] = tempx;

393:             }

394:          } // y = -A*x - temp*y

395:          else

396:          {

397:             for (i = iBegin; i < iEnd; i++)

398:             {

399:                tempx = b_data[i]*temp;

400:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

401:                {

402:                   tempx += A_data[jj] * x_data[A_j[jj]];

403:                }

404:                y_data[i] = alpha*tempx;

0x51f7a4 STP	X29, X30, [SP, #912]!

0x51f7a8 ADD	X29, SP, #0

0x51f7ac ORR	X1, XZR, X0

0x51f7b0 STP	X19, X20, [SP, #16]

0x51f7b4 STP	X21, X22, [SP, #32]

0x51f7b8 STP	X23, X24, [SP, #48]

0x51f7bc STP	X25, X26, [SP, #64]

0x51f7c0 STP	D14, D15, [SP, #96]

0x51f7c4 LDR	D14, [X0]

0x51f7c8 LDR	D15, [X0, #72]

0x51f7cc STR	X27, [SP, #80]

0x51f7d0 LDP	X21, X25, [X0, #8]

0x51f7d4 LDP	X22, X24, [X1, #24]

0x51f7d8 ORR	X0, XZR, X21

0x51f7dc LDP	X27, X19, [X1, #40]

0x51f7e0 LDP	X26, X23, [X1, #56]

0x51f7e4 BL	51e490

0x51f7e8 ORR	X20, XZR, X0

0x51f7ec ORR	X0, XZR, X21

0x51f7f0 BL	51e540

0x51f7f4 ORR	X21, XZR, X0

0x51f7f8 CMP	X20, X0

0x51f7fc B.GT	51fb28

0x51f800 CMP	X20, #0

0x51f804 CCMP	X27, X20, #1, #10

0x51f808 B.LT	51faf0

0x51f80c CMP	X21, #0

0x51f810 CCMP	X27, X21, #1, #10

0x51f814 B.LT	51fab8

0x51f818 FCMP	D15, #0

0x51f81c B.EQ	51f8d4

0x51f820 FMOV	D31, #-1.0000000

0x51f824 FCMP	D15, D31

0x51f828 B.NE	51fa1c

0x51f82c FMOV	D26, #1.0000000

0x51f830 FCMP	D14, D26

0x51f834 B.EQ	51fb60

0x51f838 FCMP	D14, D31

0x51f83c B.EQ	51fd94

0x51f840 CMP	X20, X21

0x51f844 B.GE	51f8b4

0x51f848 ADD	X30, X22, #8

0x51f84c CNTD	X27, ALL

(3950) 0x51f850 LDR	D2, [X26, X20,LSL #3]

(3950) 0x51f854 LDR	X4, [X22, X20,LSL #3]

(3950) 0x51f858 LDR	X2, [X30, X20,LSL #3]

(3950) 0x51f85c FNEG	D27, D2

(3950) 0x51f860 CMP	X4, X2

(3950) 0x51f864 B.GE	51f8a0

(3950) 0x51f868 ADD	X5, X25, X4,LSL #3

(3950) 0x51f86c MOVZ	X1, #0

(3950) 0x51f870 SUB	X6, X2, X4

(3950) 0x51f874 WHILELO	P7.D, XZR, X6

(3950) 0x51f878 ADD	X7, X24, X4,LSL #3

(3950) 0x51f87c HINT	#0

  (3951) 0x51f880 LD1D	{Z25.D}, P7/Z, [X7, X1,LSL #3]

  (3951) 0x51f884 LD1D	{Z3.D}, P7/Z, [X5, X1,LSL #3]

  (3951) 0x51f888 LD1D	{Z23.D}, P7/Z, [X19, Z25.D,LSL #3]

  (3951) 0x51f88c ADD	X1, X1, X27

  (3951) 0x51f890 FMUL	Z3.D, P7/M, Z3.D, Z23.D

  (3951) 0x51f894 FADDA	D27, P7, D27, Z3.D

  (3951) 0x51f898 WHILELO	P7.D, X1, X6

  (3951) 0x51f89c B.NE	51f880

(3950) 0x51f8a0 FMUL	D24, D14, D27

(3950) 0x51f8a4 STR	D24, [X23, X20,LSL #3]

(3950) 0x51f8a8 ADD	X20, X20, #1

(3950) 0x51f8ac CMP	X21, X20

(3950) 0x51f8b0 B.NE	51f850

(3924) 0x51f8b4 LDR	X27, [SP, #80]

(3924) 0x51f8b8 LDP	X19, X20, [SP, #16]

(3924) 0x51f8bc LDP	X21, X22, [SP, #32]

(3924) 0x51f8c0 LDP	X23, X24, [SP, #48]

(3924) 0x51f8c4 LDP	X25, X26, [SP, #64]

(3924) 0x51f8c8 LDP	D14, D15, [SP, #96]

(3924) 0x51f8cc LDP	X29, X30, [SP], #112

(3924) 0x51f8d0 RET

(3924) 0x51f8d4 FMOV	D5, #1.0000000

(3924) 0x51f8d8 FCMP	D14, D5

(3924) 0x51f8dc B.NE	51f978

(3924) 0x51f8e0 CMP	X20, X21

(3924) 0x51f8e4 B.GE	51f8b4

(3924) 0x51f8e8 ADD	X16, X22, #8

(3924) 0x51f8ec LDR	X18, [X22, X20,LSL #3]

(3924) 0x51f8f0 CNTD	X17, ALL

(3924) 0x51f8f4 LDR	X30, [X16, X20,LSL #3]

(3924) 0x51f8f8 CMP	X18, X30

(3924) 0x51f8fc B.GE	51f960

  (3932) 0x51f900 MOVI	D27, #0

  (3932) 0x51f904 ADD	X27, X25, X18,LSL #3

  (3932) 0x51f908 MOVZ	X5, #0

  (3932) 0x51f90c SUB	X4, X30, X18

  (3932) 0x51f910 WHILELO	P5.D, XZR, X4

  (3932) 0x51f914 ADD	X26, X24, X18,LSL #3

  (3932) 0x51f918 HINT	#0

  (3932) 0x51f91c HINT	#0

    (3931) 0x51f920 LD1D	{Z25.D}, P5/Z, [X26, X5,LSL #3]

    (3931) 0x51f924 LD1D	{Z2.D}, P5/Z, [X27, X5,LSL #3]

    (3931) 0x51f928 LD1D	{Z3.D}, P5/Z, [X19, Z25.D,LSL #3]

    (3931) 0x51f92c ADD	X5, X5, X17

    (3931) 0x51f930 FMUL	Z2.D, P5/M, Z2.D, Z3.D

    (3931) 0x51f934 FADDA	D27, P5, D27, Z2.D

    (3931) 0x51f938 WHILELO	P5.D, X5, X4

    (3931) 0x51f93c B.NE	51f920

  (3932) 0x51f940 STR	D27, [X23, X20,LSL #3]

  (3932) 0x51f944 ADD	X20, X20, #1

  (3932) 0x51f948 CMP	X21, X20

  (3932) 0x51f94c B.EQ	51f8b4

  (3932) 0x51f950 LDR	X18, [X22, X20,LSL #3]

  (3932) 0x51f954 LDR	X30, [X16, X20,LSL #3]

  (3932) 0x51f958 CMP	X18, X30

  (3932) 0x51f95c B.LT	51f900

  (3933) 0x51f960 MOVI	D27, #0

  (3933) 0x51f964 STR	D27, [X23, X20,LSL #3]

  (3933) 0x51f968 ADD	X20, X20, #1

  (3933) 0x51f96c CMP	X21, X20

  (3933) 0x51f970 B.NE	51f950

(3924) 0x51f974 B	51f8b4

(3924) 0x51f978 FMOV	D6, #-1.0000000

(3924) 0x51f97c FCMP	D14, D6

(3924) 0x51f980 B.NE	51fc84

(3924) 0x51f984 CMP	X20, X21

(3924) 0x51f988 B.GE	51f8b4

(3924) 0x51f98c ADD	X10, X22, #8

(3924) 0x51f990 LDR	X0, [X22, X20,LSL #3]

(3924) 0x51f994 CNTD	X11, ALL

(3924) 0x51f998 PTRUE	P3.B, ALL

(3924) 0x51f99c LDR	X12, [X10, X20,LSL #3]

(3924) 0x51f9a0 CMP	X0, X12

(3924) 0x51f9a4 B.GE	51fa04

  (3929) 0x51f9a8 MOVI	D14, #0

  (3929) 0x51f9ac ADD	X3, X25, X0,LSL #3

  (3929) 0x51f9b0 MOVZ	X15, #0

  (3929) 0x51f9b4 SUB	X13, X12, X0

  (3929) 0x51f9b8 WHILELO	P4.D, XZR, X13

  (3929) 0x51f9bc ADD	X14, X24, X0,LSL #3

    (3928) 0x51f9c0 LD1D	{Z0.D}, P4/Z, [X14, X15,LSL #3]

    (3928) 0x51f9c4 LD1D	{Z28.D}, P4/Z, [X3, X15,LSL #3]

    (3928) 0x51f9c8 LD1D	{Z26.D}, P4/Z, [X19, Z0.D,LSL #3]

    (3928) 0x51f9cc ADD	X15, X15, X11

    (3928) 0x51f9d0 FMUL	Z28.D, P4/M, Z28.D, Z26.D

    (3928) 0x51f9d4 FNEG	Z28.D, P3/M, Z28.D

    (3928) 0x51f9d8 FADDA	D14, P4, D14, Z28.D

    (3928) 0x51f9dc WHILELO	P4.D, X15, X13

    (3928) 0x51f9e0 B.NE	51f9c0

  (3929) 0x51f9e4 STR	D14, [X23, X20,LSL #3]

  (3929) 0x51f9e8 ADD	X20, X20, #1

  (3929) 0x51f9ec CMP	X21, X20

  (3929) 0x51f9f0 B.EQ	51f8b4

  (3929) 0x51f9f4 LDR	X0, [X22, X20,LSL #3]

  (3929) 0x51f9f8 LDR	X12, [X10, X20,LSL #3]

  (3929) 0x51f9fc CMP	X0, X12

  (3929) 0x51fa00 B.LT	51f9a8

  (3930) 0x51fa04 MOVI	D14, #0

  (3930) 0x51fa08 STR	D14, [X23, X20,LSL #3]

  (3930) 0x51fa0c ADD	X20, X20, #1

  (3930) 0x51fa10 CMP	X21, X20

  (3930) 0x51fa14 B.NE	51f9f4

(3924) 0x51fa18 B	51f8b4

0x51fa1c FMOV	D30, #1.0000000

0x51fa20 FCMP	D15, D30

0x51fa24 B.NE	51fbf0

0x51fa28 FCMP	D14, D30

0x51fa2c B.EQ	51fd20

0x51fa30 FCMP	D14, D31

0x51fa34 B.NE	51fe80

0x51fa38 CMP	X20, X21

0x51fa3c B.GE	51f8b4

0x51fa40 ADD	X5, X22, #8

0x51fa44 CNTD	X6, ALL

0x51fa48 PTRUE	P3.B, ALL

(3944) 0x51fa4c LDR	D6, [X26, X20,LSL #3]

(3944) 0x51fa50 LDR	X7, [X22, X20,LSL #3]

(3944) 0x51fa54 LDR	X8, [X5, X20,LSL #3]

(3944) 0x51fa58 FNEG	D14, D6

(3944) 0x51fa5c CMP	X7, X8

(3944) 0x51fa60 B.GE	51faa4

(3944) 0x51fa64 ADD	X3, X25, X7,LSL #3

(3944) 0x51fa68 MOVZ	X0, #0

(3944) 0x51fa6c SUB	X9, X8, X7

(3944) 0x51fa70 WHILELO	P4.D, XZR, X9

(3944) 0x51fa74 ADD	X10, X24, X7,LSL #3

(3944) 0x51fa78 HINT	#0

(3944) 0x51fa7c HINT	#0

  (3945) 0x51fa80 LD1D	{Z15.D}, P4/Z, [X10, X0,LSL #3]

  (3945) 0x51fa84 LD1D	{Z31.D}, P4/Z, [X3, X0,LSL #3]

  (3945) 0x51fa88 LD1D	{Z30.D}, P4/Z, [X19, Z15.D,LSL #3]

  (3945) 0x51fa8c ADD	X0, X0, X6

  (3945) 0x51fa90 FMUL	Z31.D, P4/M, Z31.D, Z30.D

  (3945) 0x51fa94 FNEG	Z31.D, P3/M, Z31.D

  (3945) 0x51fa98 FADDA	D14, P4, D14, Z31.D

  (3945) 0x51fa9c WHILELO	P4.D, X0, X9

  (3945) 0x51faa0 B.NE	51fa80

(3944) 0x51faa4 STR	D14, [X23, X20,LSL #3]

(3944) 0x51faa8 ADD	X20, X20, #1

(3944) 0x51faac CMP	X21, X20

(3944) 0x51fab0 B.NE	51fa4c

0x51fab4 B	51f8b4

0x51fab8 ADRP	X9,

0x51fabc ADRP	X10,

0x51fac0 ADRP	X11,

0x51fac4 ADD	X2, X9, #3168

0x51fac8 ADD	X1, X10, #4072

0x51facc LDR	X0, [X11, #3848]

0x51fad0 BL	52b5d0

0x51fad4 ADRP	X12,

0x51fad8 MOVZ	X3, #0

0x51fadc ADD	X0, X12, #3200

0x51fae0 MOVZ	X2, #1

0x51fae4 MOVZ	X1, #250

0x51fae8 BL	52ede0

0x51faec B	51f818

0x51faf0 ADRP	X5,

0x51faf4 ADRP	X6,

0x51faf8 ADRP	X7,

0x51fafc ADD	X2, X5, #3288

0x51fb00 ADD	X1, X6, #4072

0x51fb04 LDR	X0, [X7, #3848]

0x51fb08 BL	52b5d0

0x51fb0c ADRP	X8,

0x51fb10 MOVZ	X3, #0

0x51fb14 ADD	X0, X8, #3200

0x51fb18 MOVZ	X2, #1

0x51fb1c MOVZ	X1, #249

0x51fb20 BL	52ede0

0x51fb24 B	51f80c

0x51fb28 ADRP	X3,

0x51fb2c ADRP	X2,

0x51fb30 ADRP	X0,

0x51fb34 ADD	X1, X3, #4072

0x51fb38 ADD	X2, X2, #2728

0x51fb3c LDR	X0, [X0, #3848]

0x51fb40 BL	52b5d0

0x51fb44 ADRP	X4,

0x51fb48 MOVZ	X3, #0

0x51fb4c ADD	X0, X4, #3200

0x51fb50 MOVZ	X2, #1

0x51fb54 MOVZ	X1, #248

0x51fb58 BL	52ede0

0x51fb5c B	51f800

0x51fb60 CMP	X20, X21

0x51fb64 B.GE	51f8b4

0x51fb68 ADD	X14, X22, #8

0x51fb6c CNTD	X15, ALL

(3946) 0x51fb70 LDR	D20, [X26, X20,LSL #3]

(3946) 0x51fb74 LDR	X16, [X22, X20,LSL #3]

(3946) 0x51fb78 LDR	X17, [X14, X20,LSL #3]

(3946) 0x51fb7c FNEG	D7, D20

(3946) 0x51fb80 CMP	X16, X17

(3946) 0x51fb84 B.GE	51fbc0

(3946) 0x51fb88 ADD	X18, X25, X16,LSL #3

(3946) 0x51fb8c MOVZ	X4, #0

(3946) 0x51fb90 SUB	X30, X17, X16

(3946) 0x51fb94 WHILELO	P1.D, XZR, X30

(3946) 0x51fb98 ADD	X27, X24, X16,LSL #3

(3946) 0x51fb9c HINT	#0

  (3947) 0x51fba0 LD1D	{Z17.D}, P1/Z, [X27, X4,LSL #3]

  (3947) 0x51fba4 LD1D	{Z18.D}, P1/Z, [X18, X4,LSL #3]

  (3947) 0x51fba8 LD1D	{Z16.D}, P1/Z, [X19, Z17.D,LSL #3]

  (3947) 0x51fbac ADD	X4, X4, X15

  (3947) 0x51fbb0 FMUL	Z18.D, P1/M, Z18.D, Z16.D

  (3947) 0x51fbb4 FADDA	D7, P1, D7, Z18.D

  (3947) 0x51fbb8 WHILELO	P1.D, X4, X30

  (3947) 0x51fbbc B.NE	51fba0

(3946) 0x51fbc0 STR	D7, [X23, X20,LSL #3]

(3946) 0x51fbc4 ADD	X20, X20, #1

(3946) 0x51fbc8 CMP	X21, X20

(3946) 0x51fbcc B.NE	51fb70

0x51fbd0 LDR	X27, [SP, #80]

0x51fbd4 LDP	X19, X20, [SP, #16]

0x51fbd8 LDP	X21, X22, [SP, #32]

0x51fbdc LDP	X23, X24, [SP, #48]

0x51fbe0 LDP	X25, X26, [SP, #64]

0x51fbe4 LDP	D14, D15, [SP, #96]

0x51fbe8 LDP	X29, X30, [SP], #112

0x51fbec RET

0x51fbf0 FCMP	D14, D30

0x51fbf4 B.EQ	51fe08

0x51fbf8 FCMP	D14, D31

0x51fbfc B.NE	51fef8

0x51fc00 CMP	X20, X21

0x51fc04 B.GE	51f8b4

0x51fc08 ADD	X27, X22, #8

0x51fc0c CNTD	X4, ALL

0x51fc10 PTRUE	P6.B, ALL

0x51fc14 HINT	#0

0x51fc18 HINT	#0

0x51fc1c HINT	#0

(3938) 0x51fc20 LDR	D27, [X26, X20,LSL #3]

(3938) 0x51fc24 LDR	X2, [X22, X20,LSL #3]

(3938) 0x51fc28 LDR	X5, [X27, X20,LSL #3]

(3938) 0x51fc2c FNMUL	D3, D27, D15

(3938) 0x51fc30 CMP	X2, X5

(3938) 0x51fc34 B.GE	51fc70

(3938) 0x51fc38 ADD	X3, X25, X2,LSL #3

(3938) 0x51fc3c MOVZ	X0, #0

(3938) 0x51fc40 SUB	X6, X5, X2

(3938) 0x51fc44 WHILELO	P0.D, XZR, X6

(3938) 0x51fc48 ADD	X7, X24, X2,LSL #3

  (3939) 0x51fc4c LD1D	{Z25.D}, P0/Z, [X7, X0,LSL #3]

  (3939) 0x51fc50 LD1D	{Z23.D}, P0/Z, [X3, X0,LSL #3]

  (3939) 0x51fc54 LD1D	{Z24.D}, P0/Z, [X19, Z25.D,LSL #3]

  (3939) 0x51fc58 ADD	X0, X0, X4

  (3939) 0x51fc5c FMUL	Z23.D, P0/M, Z23.D, Z24.D

  (3939) 0x51fc60 FNEG	Z23.D, P6/M, Z23.D

  (3939) 0x51fc64 FADDA	D3, P0, D3, Z23.D

  (3939) 0x51fc68 WHILELO	P0.D, X0, X6

  (3939) 0x51fc6c B.NE	51fc4c

(3938) 0x51fc70 STR	D3, [X23, X20,LSL #3]

(3938) 0x51fc74 ADD	X20, X20, #1

(3938) 0x51fc78 CMP	X21, X20

(3938) 0x51fc7c B.NE	51fc20

0x51fc80 B	51f8b4

(3924) 0x51fc84 CMP	X20, X21

(3924) 0x51fc88 B.GE	51f8b4

(3924) 0x51fc8c ADD	X26, X22, #8

(3924) 0x51fc90 LDR	X6, [X22, X20,LSL #3]

(3924) 0x51fc94 CNTD	X5, ALL

(3924) 0x51fc98 LDR	X2, [X26, X20,LSL #3]

(3924) 0x51fc9c CMP	X6, X2

(3924) 0x51fca0 B.GE	51fd04

  (3926) 0x51fca4 MOVI	D15, #0

  (3926) 0x51fca8 ADD	X7, X25, X6,LSL #3

  (3926) 0x51fcac MOVZ	X1, #0

  (3926) 0x51fcb0 SUB	X8, X2, X6

  (3926) 0x51fcb4 WHILELO	P2.D, XZR, X8

  (3926) 0x51fcb8 ADD	X9, X24, X6,LSL #3

  (3926) 0x51fcbc HINT	#0

    (3925) 0x51fcc0 LD1D	{Z31.D}, P2/Z, [X9, X1,LSL #3]

    (3925) 0x51fcc4 LD1D	{Z30.D}, P2/Z, [X7, X1,LSL #3]

    (3925) 0x51fcc8 LD1D	{Z29.D}, P2/Z, [X19, Z31.D,LSL #3]

    (3925) 0x51fccc ADD	X1, X1, X5

    (3925) 0x51fcd0 FMUL	Z30.D, P2/M, Z30.D, Z29.D

    (3925) 0x51fcd4 FADDA	D15, P2, D15, Z30.D

    (3925) 0x51fcd8 WHILELO	P2.D, X1, X8

    (3925) 0x51fcdc B.NE	51fcc0

  (3926) 0x51fce0 FMUL	D1, D14, D15

  (3926) 0x51fce4 STR	D1, [X23, X20,LSL #3]

  (3926) 0x51fce8 ADD	X20, X20, #1

  (3926) 0x51fcec CMP	X21, X20

  (3926) 0x51fcf0 B.EQ	51f8b4

  (3926) 0x51fcf4 LDR	X6, [X22, X20,LSL #3]

  (3926) 0x51fcf8 LDR	X2, [X26, X20,LSL #3]

  (3926) 0x51fcfc CMP	X6, X2

  (3926) 0x51fd00 B.LT	51fca4

  (3927) 0x51fd04 MOVI	D15, #0

  (3927) 0x51fd08 FMUL	D1, D14, D15

  (3927) 0x51fd0c STR	D1, [X23, X20,LSL #3]

  (3927) 0x51fd10 ADD	X20, X20, #1

  (3927) 0x51fd14 CMP	X21, X20

  (3927) 0x51fd18 B.NE	51fcf4

(3924) 0x51fd1c B	51f8b4

0x51fd20 CMP	X20, X21

0x51fd24 B.GE	51f8b4

0x51fd28 ADD	X11, X22, #8

0x51fd2c CNTD	X12, ALL

(3940) 0x51fd30 LDR	X13, [X22, X20,LSL #3]

(3940) 0x51fd34 LDR	X14, [X11, X20,LSL #3]

(3940) 0x51fd38 LDR	D29, [X26, X20,LSL #3]

(3940) 0x51fd3c CMP	X13, X14

(3940) 0x51fd40 B.GE	51fd80

(3940) 0x51fd44 ADD	X15, X25, X13,LSL #3

(3940) 0x51fd48 MOVZ	X18, #0

(3940) 0x51fd4c SUB	X16, X14, X13

(3940) 0x51fd50 WHILELO	P5.D, XZR, X16

(3940) 0x51fd54 ADD	X17, X24, X13,LSL #3

(3940) 0x51fd58 HINT	#0

(3940) 0x51fd5c HINT	#0

  (3941) 0x51fd60 LD1D	{Z1.D}, P5/Z, [X17, X18,LSL #3]

  (3941) 0x51fd64 LD1D	{Z0.D}, P5/Z, [X15, X18,LSL #3]

  (3941) 0x51fd68 LD1D	{Z28.D}, P5/Z, [X19, Z1.D,LSL #3]

  (3941) 0x51fd6c ADD	X18, X18, X12

  (3941) 0x51fd70 FMUL	Z0.D, P5/M, Z0.D, Z28.D

  (3941) 0x51fd74 FADDA	D29, P5, D29, Z0.D

  (3941) 0x51fd78 WHILELO	P5.D, X18, X16

  (3941) 0x51fd7c B.NE	51fd60

(3940) 0x51fd80 STR	D29, [X23, X20,LSL #3]

(3940) 0x51fd84 ADD	X20, X20, #1

(3940) 0x51fd88 CMP	X21, X20

(3940) 0x51fd8c B.NE	51fd30

0x51fd90 B	51f8b4

0x51fd94 CMP	X20, X21

0x51fd98 B.GE	51f8b4

0x51fd9c ADD	X8, X22, #8

0x51fda0 CNTD	X9, ALL

0x51fda4 PTRUE	P6.B, ALL

(3948) 0x51fda8 LDR	X10, [X22, X20,LSL #3]

(3948) 0x51fdac LDR	X0, [X8, X20,LSL #3]

(3948) 0x51fdb0 LDR	D4, [X26, X20,LSL #3]

(3948) 0x51fdb4 CMP	X10, X0

(3948) 0x51fdb8 B.GE	51fdf4

(3948) 0x51fdbc ADD	X3, X25, X10,LSL #3

(3948) 0x51fdc0 MOVZ	X13, #0

(3948) 0x51fdc4 SUB	X11, X0, X10

(3948) 0x51fdc8 WHILELO	P0.D, XZR, X11

(3948) 0x51fdcc ADD	X12, X24, X10,LSL #3

  (3949) 0x51fdd0 LD1D	{Z21.D}, P0/Z, [X12, X13,LSL #3]

  (3949) 0x51fdd4 LD1D	{Z22.D}, P0/Z, [X3, X13,LSL #3]

  (3949) 0x51fdd8 LD1D	{Z19.D}, P0/Z, [X19, Z21.D,LSL #3]

  (3949) 0x51fddc ADD	X13, X13, X9

  (3949) 0x51fde0 FMUL	Z22.D, P0/M, Z22.D, Z19.D

  (3949) 0x51fde4 FNEG	Z22.D, P6/M, Z22.D

  (3949) 0x51fde8 FADDA	D4, P0, D4, Z22.D

  (3949) 0x51fdec WHILELO	P0.D, X13, X11

  (3949) 0x51fdf0 B.NE	51fdd0

(3948) 0x51fdf4 STR	D4, [X23, X20,LSL #3]

(3948) 0x51fdf8 ADD	X20, X20, #1

(3948) 0x51fdfc CMP	X21, X20

(3948) 0x51fe00 B.NE	51fda8

0x51fe04 B	51f8b4

0x51fe08 CMP	X20, X21

0x51fe0c B.GE	51f8b4

0x51fe10 ADD	X8, X22, #8

0x51fe14 CNTD	X9, ALL

0x51fe18 HINT	#0

0x51fe1c HINT	#0

(3934) 0x51fe20 LDR	D22, [X26, X20,LSL #3]

(3934) 0x51fe24 LDR	X10, [X22, X20,LSL #3]

(3934) 0x51fe28 LDR	X11, [X8, X20,LSL #3]

(3934) 0x51fe2c FMUL	D4, D15, D22

(3934) 0x51fe30 CMP	X10, X11

(3934) 0x51fe34 B.GE	51fe6c

(3934) 0x51fe38 ADD	X12, X25, X10,LSL #3

(3934) 0x51fe3c MOVZ	X15, #0

(3934) 0x51fe40 SUB	X13, X11, X10

(3934) 0x51fe44 WHILELO	P1.D, XZR, X13

(3934) 0x51fe48 ADD	X14, X24, X10,LSL #3

  (3935) 0x51fe4c LD1D	{Z21.D}, P1/Z, [X14, X15,LSL #3]

  (3935) 0x51fe50 LD1D	{Z19.D}, P1/Z, [X12, X15,LSL #3]

  (3935) 0x51fe54 LD1D	{Z20.D}, P1/Z, [X19, Z21.D,LSL #3]

  (3935) 0x51fe58 ADD	X15, X15, X9

  (3935) 0x51fe5c FMUL	Z19.D, P1/M, Z19.D, Z20.D

  (3935) 0x51fe60 FADDA	D4, P1, D4, Z19.D

  (3935) 0x51fe64 WHILELO	P1.D, X15, X13

  (3935) 0x51fe68 B.NE	51fe4c

(3934) 0x51fe6c STR	D4, [X23, X20,LSL #3]

(3934) 0x51fe70 ADD	X20, X20, #1

(3934) 0x51fe74 CMP	X21, X20

(3934) 0x51fe78 B.NE	51fe20

0x51fe7c B	51f8b4

0x51fe80 CMP	X20, X21

0x51fe84 B.GE	51f8b4

0x51fe88 ADD	X16, X22, #8

0x51fe8c CNTD	X17, ALL

(3942) 0x51fe90 LDR	X18, [X22, X20,LSL #3]

(3942) 0x51fe94 LDR	X30, [X16, X20,LSL #3]

(3942) 0x51fe98 LDR	D7, [X26, X20,LSL #3]

(3942) 0x51fe9c CMP	X18, X30

(3942) 0x51fea0 B.GE	51fee0

(3942) 0x51fea4 ADD	X27, X25, X18,LSL #3

(3942) 0x51fea8 MOVZ	X2, #0

(3942) 0x51feac SUB	X1, X30, X18

(3942) 0x51feb0 WHILELO	P2.D, XZR, X1

(3942) 0x51feb4 ADD	X4, X24, X18,LSL #3

(3942) 0x51feb8 HINT	#0

(3942) 0x51febc HINT	#0

  (3943) 0x51fec0 LD1D	{Z18.D}, P2/Z, [X4, X2,LSL #3]

  (3943) 0x51fec4 LD1D	{Z16.D}, P2/Z, [X27, X2,LSL #3]

  (3943) 0x51fec8 LD1D	{Z17.D}, P2/Z, [X19, Z18.D,LSL #3]

  (3943) 0x51fecc ADD	X2, X2, X17

  (3943) 0x51fed0 FMUL	Z16.D, P2/M, Z16.D, Z17.D

  (3943) 0x51fed4 FADDA	D7, P2, D7, Z16.D

  (3943) 0x51fed8 WHILELO	P2.D, X2, X1

  (3943) 0x51fedc B.NE	51fec0

(3942) 0x51fee0 FMUL	D5, D14, D7

(3942) 0x51fee4 STR	D5, [X23, X20,LSL #3]

(3942) 0x51fee8 ADD	X20, X20, #1

(3942) 0x51feec CMP	X21, X20

(3942) 0x51fef0 B.NE	51fe90

0x51fef4 B	51f8b4

0x51fef8 CMP	X20, X21

0x51fefc B.GE	51f8b4

0x51ff00 ADD	X13, X22, #8

0x51ff04 CNTD	X14, ALL

(3936) 0x51ff08 LDR	D29, [X26, X20,LSL #3]

(3936) 0x51ff0c LDR	X15, [X22, X20,LSL #3]

(3936) 0x51ff10 LDR	X16, [X13, X20,LSL #3]

(3936) 0x51ff14 FMUL	D1, D15, D29

(3936) 0x51ff18 CMP	X15, X16

(3936) 0x51ff1c B.GE	51ff60

(3936) 0x51ff20 ADD	X17, X25, X15,LSL #3

(3936) 0x51ff24 MOVZ	X1, #0

(3936) 0x51ff28 SUB	X18, X16, X15

(3936) 0x51ff2c WHILELO	P7.D, XZR, X18

(3936) 0x51ff30 ADD	X30, X24, X15,LSL #3

(3936) 0x51ff34 HINT	#0

(3936) 0x51ff38 HINT	#0

(3936) 0x51ff3c HINT	#0

  (3937) 0x51ff40 LD1D	{Z0.D}, P7/Z, [X30, X1,LSL #3]

  (3937) 0x51ff44 LD1D	{Z28.D}, P7/Z, [X17, X1,LSL #3]

  (3937) 0x51ff48 LD1D	{Z26.D}, P7/Z, [X19, Z0.D,LSL #3]

  (3937) 0x51ff4c ADD	X1, X1, X14

  (3937) 0x51ff50 FMUL	Z28.D, P7/M, Z28.D, Z26.D

  (3937) 0x51ff54 FADDA	D1, P7, D1, Z28.D

  (3937) 0x51ff58 WHILELO	P7.D, X1, X18

  (3937) 0x51ff5c B.NE	51ff40

(3936) 0x51ff60 FMUL	D2, D14, D1

(3936) 0x51ff64 STR	D2, [X23, X20,LSL #3]

(3936) 0x51ff68 ADD	X20, X20, #1

(3936) 0x51ff6c CMP	X21, X20

(3936) 0x51ff70 B.NE	51ff08

0x51ff74 B	51f8b4

0x51ff78 HINT	#0

0x51ff7c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.98+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 2.17 cycles (9.23x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 60% of vector register length is used (average across all VPU instructions).

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

9% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 4.00 cycles (5.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	153
loop length	612
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	20.00	20.00	13.33	13.33	13.33	13.33	13.33	13.33	9.00	1.50	1.25	1.25	7.83	7.50	7.67	3.00	3.00
cycles	20.00	20.00	13.33	13.33	13.33	13.33	13.33	13.33	9.00	1.50	1.25	1.25	7.83	7.50	7.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.25
Overall L1	20.00

Vectorization ratios

INT

all	2%
load	9%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	9%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

10% of peak load performance is reached (10.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 51f7a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X1, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D15, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X25, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X24, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X27, X19, [X1, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X23, [X1, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 51e490 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 51e540 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X20, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 51fb28 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X27, X20, #1, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.LT 51faf0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X27, X21, #1, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.LT 51fab8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51f8d4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D15, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 51fa1c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D26, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D14, D26	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51fb60 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51fd94 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X27, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
FMOV D30, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D15, D30	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 51fbf0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51fd20 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x57c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 51fe80 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X6, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
PTRUE P3.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X9, <535ab8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X10, <534abc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X11, <561ac0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, #3168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X10, #4072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X11, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b5d0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X12, <535ad4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X12, #3200	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X1, #250	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52ede0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51f818 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <535af0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X6, <534af4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X7, <561af8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X5, #3288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X6, #4072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X7, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b5d0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <535b0c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X8, #3200	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X1, #249	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52ede0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51f80c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <534b28>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X2, <535b2c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X0, <561b30>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X3, #4072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X2, #2728	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b5d0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, <535b44>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X4, #3200	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X1, #248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52ede0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51f800 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X15, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51fe08 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 51fef8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X4, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CNTD X12, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X9, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X9, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X17, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CNTD X14, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 2.17 cycles (9.23x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 60% of vector register length is used (average across all VPU instructions).

Details

2% of VPU instructions are used in vector version (process two or more data elements in vector registers):

9% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 4.00 cycles (5.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	153
loop length	612
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	20.00	20.00	13.33	13.33	13.33	13.33	13.33	13.33	9.00	1.50	1.25	1.25	7.83	7.50	7.67	3.00	3.00
cycles	20.00	20.00	13.33	13.33	13.33	13.33	13.33	13.33	9.00	1.50	1.25	1.25	7.83	7.50	7.67	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.25
Overall L1	20.00

Vectorization ratios

INT

all	2%
load	9%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	9%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

10% of peak load performance is reached (10.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (5.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 51f7a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X1, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D15, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X25, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X24, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X27, X19, [X1, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X23, [X1, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 51e490 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 51e540 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X20, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 51fb28 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x384>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X27, X20, #1, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.LT 51faf0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X21, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X27, X21, #1, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.LT 51fab8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D15, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51f8d4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D15, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 51fa1c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x278>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D26, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D14, D26	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51fb60 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51fd94 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X27, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
FMOV D30, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCMP D15, D30	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 51fbf0 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51fd20 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x57c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 51fe80 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X5, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X6, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
PTRUE P3.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X9, <535ab8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X10, <534abc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X11, <561ac0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X9, #3168	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X10, #4072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X11, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b5d0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X12, <535ad4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X12, #3200	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X1, #250	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52ede0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51f818 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X5, <535af0>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X6, <534af4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X7, <561af8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X5, #3288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X6, #4072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X7, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b5d0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, <535b0c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X8, #3200	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X1, #249	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52ede0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51f80c <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <534b28>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X2, <535b2c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADRP X0, <561b30>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X3, #4072	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X2, #2728	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #3848]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b5d0 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X4, <535b44>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X4, #3200	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X1, #248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52ede0 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 51f800 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X14, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X15, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D30	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 51fe08 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x664>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.NE 51fef8 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X4, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X11, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CNTD X12, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X9, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X9, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X17, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X22, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CNTD X14, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
B 51f8b4 <hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6–	26.00	4.16
▼Loop 3948 - csr_matvec.c:307-314 - exec–	0.18	0.02
○Loop 3949 - csr_matvec.c:310-312 - exec	12.84	1.59
▼Loop 3940 - csr_matvec.c:334-341 - exec–	0.16	0.02
○Loop 3941 - csr_matvec.c:337-339 - exec	1.25	0.16
▼Loop 3934 - csr_matvec.c:373-380 - exec–	0.00	0.00
○Loop 3935 - csr_matvec.c:376-378 - exec	0.00	0.00
▼Loop 3946 - csr_matvec.c:295-302 - exec–	0.00	0.00
○Loop 3947 - csr_matvec.c:298-300 - exec	0.00	0.00
▼Loop 3938 - csr_matvec.c:385-392 - exec–	0.00	0.00
○Loop 3939 - csr_matvec.c:388-390 - exec	0.00	0.00
▼Loop 3924 - csr_matvec.c:243-287 - exec–	0.00	0.00
▼Loop 3932 - csr_matvec.c:256-263 - exec–	0.10	0.01
○Loop 3931 - csr_matvec.c:259-261 - exec	11.46	1.42
○Loop 3933 - csr_matvec.c:256-263 - exec	0.00	0.00
▼Loop 3926 - csr_matvec.c:280-287 - exec–	0.00	0.00
○Loop 3925 - csr_matvec.c:283-285 - exec	0.00	0.00
▼Loop 3929 - csr_matvec.c:268-275 - exec–	0.00	0.00
○Loop 3928 - csr_matvec.c:271-273 - exec	0.00	0.00
○Loop 3930 - csr_matvec.c:268-275 - exec	0.00	0.00
○Loop 3927 - csr_matvec.c:280-287 - exec	0.00	0.00
▼Loop 3936 - csr_matvec.c:397-404 - exec–	0.00	0.00
○Loop 3937 - csr_matvec.c:400-402 - exec	0.00	0.00
▼Loop 3950 - csr_matvec.c:319-326 - exec–	0.00	0.00
○Loop 3951 - csr_matvec.c:322-324 - exec	0.00	0.00
▼Loop 3944 - csr_matvec.c:346-353 - exec–	0.00	0.00
○Loop 3945 - csr_matvec.c:349-351 - exec	0.00	0.00
▼Loop 3942 - csr_matvec.c:358-365 - exec–	0.00	0.00
○Loop 3943 - csr_matvec.c:361-363 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code