OV - exec - Function hypre_CSRMatrixTranspose._omp

	Function: hypre_CSRMatrixTranspose._omp_fn.0	Module: exec	Source: csr_matop.c:380-560 [...]	Coverage (incl. loops): 0.15% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 560

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

463: #pragma omp parallel

464: #endif

465:    {

466:    HYPRE_Int num_threads = hypre_NumActiveThreads();

467:    HYPRE_Int my_thread_num = hypre_GetThreadNum();

468:

469:    HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

470:    HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

471:    hypre_assert(iBegin <= iEnd);

472:    hypre_assert(iBegin >= 0 && iBegin <= num_rowsA);

473:    hypre_assert(iEnd >= 0 && iEnd <= num_rowsA);

474:

475:    HYPRE_Int i, j;

476:    memset(bucket + my_thread_num*num_colsA, 0, sizeof(HYPRE_Int)*num_colsA);

[...]

483:    for (j = A_i[iBegin]; j < A_i[iEnd]; ++j) {

484:      HYPRE_Int idx = A_j[j];

485:      bucket[my_thread_num*num_colsA + idx]++;

[...]

493: #pragma omp barrier

494: #endif

495:

496:    for (i = my_thread_num*num_colsA + 1; i < (my_thread_num + 1)*num_colsA; ++i) {

497:      HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

498:      HYPRE_Int transpose_i_minus_1 = transpose_idx(i - 1, num_threads, num_colsA);

499:

500:      bucket[transpose_i] += bucket[transpose_i_minus_1];

501:    }

502:

503: #ifdef HYPRE_USING_OPENMP

504: #pragma omp barrier

505: #pragma omp master

506: #endif

507:    {

508:      for (i = 1; i < num_threads; ++i) {

509:        HYPRE_Int j0 = num_colsA*i - 1, j1 = num_colsA*(i + 1) - 1;

510:        HYPRE_Int transpose_j0 = transpose_idx(j0, num_threads, num_colsA);

511:        HYPRE_Int transpose_j1 = transpose_idx(j1, num_threads, num_colsA);

512:

513:        bucket[transpose_j1] += bucket[transpose_j0];

514:      }

515:    }

516: #ifdef HYPRE_USING_OPENMP

517: #pragma omp barrier

518: #endif

519:

520:    if (my_thread_num > 0) {

521:      HYPRE_Int transpose_i0 = transpose_idx(num_colsA*my_thread_num - 1, num_threads, num_colsA);

522:      HYPRE_Int offset = bucket[transpose_i0];

523:

524:      for (i = my_thread_num*num_colsA; i < (my_thread_num + 1)*num_colsA - 1; ++i) {

525:        HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

526:

527:        bucket[transpose_i] += offset;

528:      }

529:    }

530:

531: #ifdef HYPRE_USING_OPENMP

532: #pragma omp barrier

[...]

539:    if (data) {

540:       for (i = iEnd - 1; i >= iBegin; --i) {

541:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

542:           HYPRE_Int idx = A_j[j];

543:           --bucket[my_thread_num*num_colsA + idx];

544:

545:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

546:

547:           AT_data[offset] = A_data[j];

548:           AT_j[offset] = i;

549:         }

550:       }

551:    }

552:    else {

553:       for (i = iEnd - 1; i >= iBegin; --i) {

554:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

555:           HYPRE_Int idx = A_j[j];

556:           --bucket[my_thread_num*num_colsA + idx];

557:

558:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

559:

560:           AT_j[offset] = i;

0x518e88 STP	X29, X30, [SP, #896]!

0x518e8c ADD	X29, SP, #0

0x518e90 STP	X19, X20, [SP, #16]

0x518e94 STP	X21, X22, [SP, #32]

0x518e98 STP	X23, X24, [SP, #48]

0x518e9c STP	X25, X26, [SP, #64]

0x518ea0 STP	X27, X28, [SP, #80]

0x518ea4 LDP	X19, X1, [X0]

0x518ea8 STR	X1, [SP, #120]

0x518eac LDP	X28, X22, [X0, #16]

0x518eb0 LDP	X23, X21, [X0, #32]

0x518eb4 LDP	X27, X26, [X0, #48]

0x518eb8 LDP	X24, X20, [X0, #64]

0x518ebc BL	52df40

0x518ec0 ORR	X25, XZR, X0

0x518ec4 BL	52df60

0x518ec8 ORR	X2, XZR, X0

0x518ecc ORR	X0, XZR, X19

0x518ed0 STR	X2, [SP, #104]

0x518ed4 BL	51e490

0x518ed8 ORR	X3, XZR, X0

0x518edc ORR	X0, XZR, X19

0x518ee0 STR	X3, [SP, #96]

0x518ee4 BL	51e540

0x518ee8 ORR	X19, XZR, X0

0x518eec LDR	X0, [SP, #96]

0x518ef0 CMP	X0, X19

0x518ef4 B.GT	519480

0x518ef8 LDR	X8, [SP, #96]

0x518efc CMP	X8, #0

0x518f00 CCMP	X21, X8, #1, #10

0x518f04 B.LT	5194c4

(3798) 0x518f08 CMP	X19, #0

(3798) 0x518f0c CCMP	X21, X19, #1, #10

(3798) 0x518f10 B.LT	519504

(3798) 0x518f14 LDR	X16, [SP, #104]

(3798) 0x518f18 UBFM	X2, X27, #61, #60

(3798) 0x518f1c MOVZ	W1, #0

(3798) 0x518f20 MADD	X21, X27, X16, XZR

(3798) 0x518f24 ADD	X0, X20, X21,LSL #3

(3798) 0x518f28 BL	410950

(3798) 0x518f2c LDR	X1, [SP, #96]

(3798) 0x518f30 ADD	X3, X22, X19,LSL #3

(3798) 0x518f34 LDR	X0, [X22, X19,LSL #3]

(3798) 0x518f38 LDR	X2, [X22, X1,LSL #3]

(3798) 0x518f3c CMP	X2, X0

(3798) 0x518f40 B.GE	518f6c

  (3807) 0x518f44 LDR	X17, [X23, X2,LSL #3]

  (3807) 0x518f48 ADD	X2, X2, #1

  (3807) 0x518f4c ADD	X30, X21, X17

  (3807) 0x518f50 UBFM	X4, X30, #61, #60

  (3807) 0x518f54 LDR	X5, [X20, X4]

  (3807) 0x518f58 ADD	X6, X5, #1

  (3807) 0x518f5c STR	X6, [X20, X4]

  (3807) 0x518f60 LDR	X7, [X3]

  (3807) 0x518f64 CMP	X7, X2

  (3807) 0x518f68 B.GT	518f44

(3798) 0x518f6c BL	410d30

(3798) 0x518f70 ADD	X8, X27, X21

(3798) 0x518f74 ADD	X0, X21, #1

(3798) 0x518f78 STR	X8, [SP, #112]

(3798) 0x518f7c CMP	X27, #1

(3798) 0x518f80 B.LE	519100

(3798) 0x518f84 SUB	X9, X8, X0

(3798) 0x518f88 ANDS	X10, X9, #4160

(3798) 0x518f8c B.EQ	519044

(3798) 0x518f90 CMP	X10, #1

(3798) 0x518f94 B.EQ	519004

(3798) 0x518f98 CMP	X10, #2

(3798) 0x518f9c B.EQ	518fd0

(3798) 0x518fa0 SDIV	X11, X0, X25

(3798) 0x518fa4 SDIV	X12, X21, X25

(3798) 0x518fa8 MSUB	X13, X11, X25, X0

(3798) 0x518fac ADD	X0, X0, #1

(3798) 0x518fb0 MADD	X14, X13, X27, X11

(3798) 0x518fb4 MSUB	X15, X12, X25, X21

(3798) 0x518fb8 ADD	X18, X20, X14,LSL #3

(3798) 0x518fbc MADD	X16, X15, X27, X12

(3798) 0x518fc0 LDR	X1, [X18]

(3798) 0x518fc4 LDR	X3, [X20, X16,LSL #3]

(3798) 0x518fc8 ADD	X17, X1, X3

(3798) 0x518fcc STR	X17, [X18]

(3798) 0x518fd0 SDIV	X30, X0, X25

(3798) 0x518fd4 SUB	X2, X0, #1

(3798) 0x518fd8 SDIV	X4, X2, X25

(3798) 0x518fdc MSUB	X5, X30, X25, X0

(3798) 0x518fe0 ADD	X0, X0, #1

(3798) 0x518fe4 MADD	X6, X5, X27, X30

(3798) 0x518fe8 MSUB	X7, X4, X25, X2

(3798) 0x518fec ADD	X8, X20, X6,LSL #3

(3798) 0x518ff0 MADD	X9, X7, X27, X4

(3798) 0x518ff4 LDR	X11, [X8]

(3798) 0x518ff8 LDR	X10, [X20, X9,LSL #3]

(3798) 0x518ffc ADD	X12, X11, X10

(3798) 0x519000 STR	X12, [X8]

(3798) 0x519004 SDIV	X14, X0, X25

(3798) 0x519008 SUB	X13, X0, #1

(3798) 0x51900c LDR	X5, [SP, #112]

(3798) 0x519010 SDIV	X15, X13, X25

(3798) 0x519014 MSUB	X18, X14, X25, X0

(3798) 0x519018 ADD	X0, X0, #1

(3798) 0x51901c MADD	X16, X18, X27, X14

(3798) 0x519020 MSUB	X3, X15, X25, X13

(3798) 0x519024 ADD	X1, X20, X16,LSL #3

(3798) 0x519028 MADD	X17, X3, X27, X15

(3798) 0x51902c LDR	X30, [X1]

(3798) 0x519030 LDR	X2, [X20, X17,LSL #3]

(3798) 0x519034 ADD	X4, X30, X2

(3798) 0x519038 STR	X4, [X1]

(3798) 0x51903c CMP	X0, X5

(3798) 0x519040 B.EQ	519100

  (3806) 0x519044 SUB	X6, X0, #1

  (3806) 0x519048 SDIV	X7, X0, X25

  (3806) 0x51904c ADD	X15, X0, #1

  (3806) 0x519050 ADD	X18, X0, #2

  (3806) 0x519054 ADD	X1, X0, #3

  (3806) 0x519058 ORR	X3, XZR, X18

  (3806) 0x51905c SDIV	X8, X6, X25

  (3806) 0x519060 SDIV	X11, X15, X25

  (3806) 0x519064 MSUB	X9, X7, X25, X0

  (3806) 0x519068 ADD	X0, X0, #4

  (3806) 0x51906c SDIV	X12, X18, X25

  (3806) 0x519070 MSUB	X10, X8, X25, X6

  (3806) 0x519074 MADD	X16, X9, X27, X7

  (3806) 0x519078 MSUB	X30, X11, X25, X15

  (3806) 0x51907c MADD	X14, X10, X27, X8

  (3806) 0x519080 UBFM	X13, X16, #61, #60

  (3806) 0x519084 SDIV	X6, X1, X25

  (3806) 0x519088 LDR	X17, [X20, X13]

  (3806) 0x51908c LDR	X2, [X20, X14,LSL #3]

  (3806) 0x519090 MADD	X4, X30, X27, X11

  (3806) 0x519094 ORR	X11, XZR, X12

  (3806) 0x519098 MSUB	X18, X12, X25, X18

  (3806) 0x51909c UBFM	X7, X4, #61, #60

  (3806) 0x5190a0 ADD	X5, X17, X2

  (3806) 0x5190a4 MADD	X10, X18, X27, X12

  (3806) 0x5190a8 MSUB	X2, X11, X25, X3

  (3806) 0x5190ac STR	X5, [X20, X13]

  (3806) 0x5190b0 LDR	X15, [X20, X16,LSL #3]

  (3806) 0x5190b4 UBFM	X14, X10, #61, #60

  (3806) 0x5190b8 MSUB	X16, X6, X25, X1

  (3806) 0x5190bc MADD	X1, X2, X27, X11

  (3806) 0x5190c0 LDR	X8, [X20, X7]

  (3806) 0x5190c4 MADD	X12, X16, X27, X6

  (3806) 0x5190c8 UBFM	X30, X12, #61, #60

  (3806) 0x5190cc ADD	X9, X8, X15

  (3806) 0x5190d0 STR	X9, [X20, X7]

  (3806) 0x5190d4 LDR	X13, [X20, X4,LSL #3]

  (3806) 0x5190d8 LDR	X17, [X20, X14]

  (3806) 0x5190dc LDR	X7, [SP, #112]

  (3806) 0x5190e0 ADD	X3, X17, X13

  (3806) 0x5190e4 STR	X3, [X20, X14]

  (3806) 0x5190e8 LDR	X4, [X20, X30]

  (3806) 0x5190ec LDR	X5, [X20, X1,LSL #3]

  (3806) 0x5190f0 ADD	X6, X4, X5

  (3806) 0x5190f4 STR	X6, [X20, X30]

  (3806) 0x5190f8 CMP	X0, X7

  (3806) 0x5190fc B.NE	519044

(3798) 0x519100 BL	410d30

(3798) 0x519104 BL	410c90

(3798) 0x519108 CBNZ	W0, 519240

(3798) 0x51910c CMP	X25, #1

(3798) 0x519110 B.LE	519240

(3798) 0x519114 SUB	X15, X27, #1

(3798) 0x519118 MOVZ	X0, #1

(3798) 0x51911c SDIV	X18, X15, X25

(3798) 0x519120 MSUB	X8, X18, X25, X15

(3798) 0x519124 MADD	X11, X8, X27, X18

(3798) 0x519128 LDR	X2, [X20, X11,LSL #3]

(3798) 0x51912c CMP	X27, X0

(3798) 0x519130 B.NE	519654

(3798) 0x519134 SUB	X9, X25, X27

(3798) 0x519138 ANDS	X5, X9, #4160

(3798) 0x51913c B.EQ	5191b8

(3798) 0x519140 CMP	X5, X0

(3798) 0x519144 B.EQ	519190

(3798) 0x519148 CMP	X5, #2

(3798) 0x51914c B.EQ	519170

(3798) 0x519150 SDIV	X6, X27, X25

(3798) 0x519154 MOVZ	X0, #2

(3798) 0x519158 MSUB	X3, X6, X25, X27

(3798) 0x51915c ADD	X7, X6, X3

(3798) 0x519160 ADD	X15, X20, X7,LSL #3

(3798) 0x519164 LDR	X18, [X15]

(3798) 0x519168 ADD	X2, X2, X18

(3798) 0x51916c STR	X2, [X15]

(3798) 0x519170 SDIV	X8, X0, X25

(3798) 0x519174 MSUB	X11, X8, X25, X0

(3798) 0x519178 ADD	X0, X0, #1

(3798) 0x51917c ADD	X10, X8, X11

(3798) 0x519180 ADD	X16, X20, X10,LSL #3

(3798) 0x519184 LDR	X14, [X16]

(3798) 0x519188 ADD	X2, X2, X14

(3798) 0x51918c STR	X2, [X16]

(3798) 0x519190 SDIV	X17, X0, X25

(3798) 0x519194 MSUB	X30, X17, X25, X0

(3798) 0x519198 ADD	X0, X0, #1

(3798) 0x51919c ADD	X12, X17, X30

(3798) 0x5191a0 ADD	X13, X20, X12,LSL #3

(3798) 0x5191a4 LDR	X1, [X13]

(3798) 0x5191a8 ADD	X2, X2, X1

(3798) 0x5191ac STR	X2, [X13]

(3798) 0x5191b0 CMP	X25, X0

(3798) 0x5191b4 B.EQ	519240

  (3805) 0x5191b8 SDIV	X4, X0, X25

  (3805) 0x5191bc ADD	X5, X0, #1

  (3805) 0x5191c0 ADD	X7, X0, #2

  (3805) 0x5191c4 ADD	X6, X0, #3

  (3805) 0x5191c8 SDIV	X15, X5, X25

  (3805) 0x5191cc SDIV	X10, X7, X25

  (3805) 0x5191d0 MSUB	X9, X4, X25, X0

  (3805) 0x5191d4 ADD	X0, X0, #4

  (3805) 0x5191d8 MSUB	X8, X15, X25, X5

  (3805) 0x5191dc ADD	X3, X4, X9

  (3805) 0x5191e0 UBFM	X18, X3, #61, #60

  (3805) 0x5191e4 LDR	X11, [X20, X18]

  (3805) 0x5191e8 ADD	X16, X15, X8

  (3805) 0x5191ec UBFM	X14, X16, #61, #60

  (3805) 0x5191f0 MSUB	X12, X10, X25, X7

  (3805) 0x5191f4 ADD	X1, X10, X12

  (3805) 0x5191f8 ADD	X17, X2, X11

  (3805) 0x5191fc SDIV	X2, X6, X25

  (3805) 0x519200 UBFM	X4, X1, #61, #60

  (3805) 0x519204 STR	X17, [X20, X18]

  (3805) 0x519208 LDR	X30, [X20, X14]

  (3805) 0x51920c ADD	X13, X17, X30

  (3805) 0x519210 MSUB	X5, X2, X25, X6

  (3805) 0x519214 STR	X13, [X20, X14]

  (3805) 0x519218 LDR	X6, [X20, X4]

  (3805) 0x51921c ADD	X7, X2, X5

  (3805) 0x519220 UBFM	X15, X7, #61, #60

  (3805) 0x519224 ADD	X9, X13, X6

  (3805) 0x519228 STR	X9, [X20, X4]

  (3805) 0x51922c LDR	X3, [X20, X15]

  (3805) 0x519230 ADD	X2, X9, X3

  (3805) 0x519234 STR	X2, [X20, X15]

  (3805) 0x519238 CMP	X25, X0

  (3805) 0x51923c B.NE	5191b8

(3798) 0x519240 BL	410d30

(3798) 0x519244 LDR	X0, [SP, #104]

(3798) 0x519248 CMP	X0, #0

(3798) 0x51924c B.LE	51936c

(3798) 0x519250 SUB	X18, X21, #1

(3798) 0x519254 LDR	X8, [SP, #112]

(3798) 0x519258 SDIV	X11, X18, X25

(3798) 0x51925c SUB	X16, X8, #1

(3798) 0x519260 MSUB	X10, X11, X25, X18

(3798) 0x519264 MADD	X14, X10, X27, X11

(3798) 0x519268 LDR	X17, [X20, X14,LSL #3]

(3798) 0x51926c CMP	X21, X16

(3798) 0x519270 B.GE	51936c

(3798) 0x519274 ORR	X18, XZR, X21

(3798) 0x519278 CMP	X27, #1

(3798) 0x51927c B.NE	51953c

(3798) 0x519280 SUB	X27, X16, X21

(3798) 0x519284 ANDS	X1, X27, #4160

(3798) 0x519288 B.EQ	5192e4

(3798) 0x51928c CMP	X1, #1

(3798) 0x519290 B.EQ	5192bc

(3798) 0x519294 CMP	X1, #2

(3798) 0x519298 B.NE	519630

(3798) 0x51929c SDIV	X12, X18, X25

(3798) 0x5192a0 MSUB	X13, X12, X25, X18

(3798) 0x5192a4 ADD	X18, X18, #1

(3798) 0x5192a8 ADD	X4, X12, X13

(3798) 0x5192ac ADD	X5, X20, X4,LSL #3

(3798) 0x5192b0 LDR	X6, [X5]

(3798) 0x5192b4 ADD	X7, X6, X17

(3798) 0x5192b8 STR	X7, [X5]

(3798) 0x5192bc SDIV	X15, X18, X25

(3798) 0x5192c0 MSUB	X9, X15, X25, X18

(3798) 0x5192c4 ADD	X18, X18, #1

(3798) 0x5192c8 ADD	X3, X15, X9

(3798) 0x5192cc ADD	X0, X20, X3,LSL #3

(3798) 0x5192d0 LDR	X27, [X0]

(3798) 0x5192d4 ADD	X1, X27, X17

(3798) 0x5192d8 STR	X1, [X0]

(3798) 0x5192dc CMP	X16, X18

(3798) 0x5192e0 B.EQ	51936c

  (3803) 0x5192e4 SDIV	X8, X18, X25

  (3803) 0x5192e8 ADD	X14, X18, #1

  (3803) 0x5192ec ADD	X11, X18, #2

  (3803) 0x5192f0 ADD	X10, X18, #3

  (3803) 0x5192f4 SDIV	X30, X14, X25

  (3803) 0x5192f8 SDIV	X2, X11, X25

  (3803) 0x5192fc MSUB	X12, X8, X25, X18

  (3803) 0x519300 ADD	X18, X18, #4

  (3803) 0x519304 SDIV	X15, X10, X25

  (3803) 0x519308 ADD	X4, X8, X12

  (3803) 0x51930c UBFM	X5, X4, #61, #60

  (3803) 0x519310 LDR	X6, [X20, X5]

  (3803) 0x519314 MSUB	X13, X30, X25, X14

  (3803) 0x519318 MSUB	X0, X2, X25, X11

  (3803) 0x51931c ADD	X7, X30, X13

  (3803) 0x519320 UBFM	X3, X7, #61, #60

  (3803) 0x519324 ADD	X27, X2, X0

  (3803) 0x519328 ADD	X9, X6, X17

  (3803) 0x51932c UBFM	X8, X27, #61, #60

  (3803) 0x519330 MSUB	X14, X15, X25, X10

  (3803) 0x519334 STR	X9, [X20, X5]

  (3803) 0x519338 LDR	X1, [X20, X3]

  (3803) 0x51933c ADD	X11, X15, X14

  (3803) 0x519340 UBFM	X30, X11, #61, #60

  (3803) 0x519344 ADD	X10, X1, X17

  (3803) 0x519348 STR	X10, [X20, X3]

  (3803) 0x51934c LDR	X2, [X20, X8]

  (3803) 0x519350 ADD	X12, X2, X17

  (3803) 0x519354 STR	X12, [X20, X8]

  (3803) 0x519358 LDR	X13, [X20, X30]

  (3803) 0x51935c ADD	X4, X13, X17

  (3803) 0x519360 STR	X4, [X20, X30]

  (3803) 0x519364 CMP	X16, X18

  (3803) 0x519368 B.NE	5192e4

(3798) 0x51936c BL	410d30

(3798) 0x519370 LDR	X25, [SP, #120]

(3798) 0x519374 SUB	X3, X19, #1

(3798) 0x519378 CBNZ	X25, 5193f8

(3798) 0x51937c LDR	X28, [SP, #96]

(3798) 0x519380 CMP	X28, X3

(3798) 0x519384 B.GT	5193dc

(3798) 0x519388 SUB	X26, X28, #1

(3798) 0x51938c ADD	X19, X22, #8

  (3800) 0x519390 LDR	X16, [X19, X3,LSL #3]

  (3800) 0x519394 LDR	X17, [X22, X3,LSL #3]

  (3800) 0x519398 SUB	X5, X16, #1

  (3800) 0x51939c CMP	X5, X17

  (3800) 0x5193a0 B.LT	5193d0

    (3801) 0x5193a4 LDR	X18, [X23, X5,LSL #3]

    (3801) 0x5193a8 SUB	X5, X5, #1

    (3801) 0x5193ac ADD	X6, X21, X18

    (3801) 0x5193b0 UBFM	X7, X6, #61, #60

    (3801) 0x5193b4 LDR	X15, [X20, X7]

    (3801) 0x5193b8 SUB	X0, X15, #1

    (3801) 0x5193bc STR	X0, [X20, X7]

    (3801) 0x5193c0 STR	X3, [X24, X0,LSL #3]

    (3801) 0x5193c4 LDR	X9, [X22, X3,LSL #3]

    (3801) 0x5193c8 CMP	X9, X5

    (3801) 0x5193cc B.LE	5193a4

  (3800) 0x5193d0 SUB	X3, X3, #1

  (3800) 0x5193d4 CMP	X3, X26

  (3800) 0x5193d8 B.NE	519390

  (3796) 0x5193dc LDP	X19, X20, [SP, #16]

  (3796) 0x5193e0 LDP	X21, X22, [SP, #32]

  (3796) 0x5193e4 LDP	X23, X24, [SP, #48]

  (3796) 0x5193e8 LDP	X25, X26, [SP, #64]

  (3796) 0x5193ec LDP	X27, X28, [SP, #80]

  (3796) 0x5193f0 LDP	X29, X30, [SP], #128

  (3796) 0x5193f4 RET

  (3796) 0x5193f8 LDR	X27, [SP, #96]

  (3796) 0x5193fc CMP	X27, X3

  (3796) 0x519400 B.GT	5193dc

(3798) 0x519404 SUB	X14, X27, #1

(3798) 0x519408 ADD	X8, X22, #8

  (3797) 0x51940c LDR	X1, [X8, X3,LSL #3]

  (3797) 0x519410 LDR	X10, [X22, X3,LSL #3]

  (3797) 0x519414 SUB	X30, X1, #1

  (3797) 0x519418 CMP	X30, X10

  (3797) 0x51941c B.LT	519458

    (3799) 0x519420 LDR	X11, [X23, X30,LSL #3]

    (3799) 0x519424 LDR	D31, [X28, X30,LSL #3]

    (3799) 0x519428 SUB	X30, X30, #1

    (3799) 0x51942c ADD	X2, X21, X11

    (3799) 0x519430 UBFM	X12, X2, #61, #60

    (3799) 0x519434 LDR	X13, [X20, X12]

    (3799) 0x519438 SUB	X4, X13, #1

    (3799) 0x51943c UBFM	X25, X4, #61, #60

    (3799) 0x519440 STR	X4, [X20, X12]

    (3799) 0x519444 STR	D31, [X26, X25]

    (3799) 0x519448 STR	X3, [X24, X25]

    (3799) 0x51944c LDR	X19, [X22, X3,LSL #3]

    (3799) 0x519450 CMP	X19, X30

    (3799) 0x519454 B.LE	519420

  (3797) 0x519458 SUB	X3, X3, #1

  (3797) 0x51945c CMP	X3, X14

  (3797) 0x519460 B.NE	51940c

(3798) 0x519464 LDP	X19, X20, [SP, #16]

(3798) 0x519468 LDP	X21, X22, [SP, #32]

(3798) 0x51946c LDP	X23, X24, [SP, #48]

(3798) 0x519470 LDP	X25, X26, [SP, #64]

(3798) 0x519474 LDP	X27, X28, [SP, #80]

(3798) 0x519478 LDP	X29, X30, [SP], #128

(3798) 0x51947c RET

(3798) 0x519480 ADRP	X4,

(3798) 0x519484 ADRP	X5,

(3798) 0x519488 ADRP	X6,

(3798) 0x51948c ADD	X2, X4, #2728

(3798) 0x519490 ADD	X1, X5, #4072

(3798) 0x519494 LDR	X0, [X6, #3848]

(3798) 0x519498 BL	52b5d0

(3798) 0x51949c ADRP	X7,

(3798) 0x5194a0 MOVZ	X3, #0

(3798) 0x5194a4 ADD	X0, X7, #2600

(3798) 0x5194a8 MOVZ	X2, #1

(3798) 0x5194ac MOVZ	X1, #471

(3798) 0x5194b0 BL	52ede0

(3798) 0x5194b4 LDR	X8, [SP, #96]

(3798) 0x5194b8 CMP	X8, #0

(3798) 0x5194bc CCMP	X21, X8, #1, #10

(3798) 0x5194c0 B.GE	518f08

(3798) 0x5194c4 ADRP	X9,

(3798) 0x5194c8 ADRP	X10,

(3798) 0x5194cc ADRP	X11,

(3798) 0x5194d0 ADD	X2, X9, #2688

(3798) 0x5194d4 ADD	X1, X10, #4072

(3798) 0x5194d8 LDR	X0, [X11, #3848]

(3798) 0x5194dc BL	52b5d0

(3798) 0x5194e0 ADRP	X12,

(3798) 0x5194e4 MOVZ	X3, #0

(3798) 0x5194e8 ADD	X0, X12, #2600

(3798) 0x5194ec MOVZ	X2, #1

(3798) 0x5194f0 MOVZ	X1, #472

(3798) 0x5194f4 BL	52ede0

(3798) 0x5194f8 CMP	X19, #0

(3798) 0x5194fc CCMP	X21, X19, #1, #10

(3798) 0x519500 B.GE	518f14

(3798) 0x519504 ADRP	X13,

(3798) 0x519508 ADRP	X14,

(3798) 0x51950c ADRP	X15,

(3798) 0x519510 ADD	X2, X13, #2568

(3798) 0x519514 ADD	X1, X14, #4072

(3798) 0x519518 LDR	X0, [X15, #3848]

(3798) 0x51951c BL	52b5d0

(3798) 0x519520 ADRP	X18,

(3798) 0x519524 MOVZ	X3, #0

(3798) 0x519528 ADD	X0, X18, #2600

(3798) 0x51952c MOVZ	X2, #1

(3798) 0x519530 MOVZ	X1, #473

(3798) 0x519534 BL	52ede0

(3798) 0x519538 B	518f14

(3798) 0x51953c SUB	X2, X16, X21

(3798) 0x519540 ORR	X1, XZR, X21

(3798) 0x519544 ANDS	X30, X2, #4160

(3798) 0x519548 B.EQ	5195a4

(3798) 0x51954c CMP	X30, #1

(3798) 0x519550 B.EQ	51957c

(3798) 0x519554 CMP	X30, #2

(3798) 0x519558 B.NE	51977c

(3798) 0x51955c SDIV	X15, X1, X25

(3798) 0x519560 MSUB	X9, X15, X25, X1

(3798) 0x519564 ADD	X1, X1, #1

(3798) 0x519568 MADD	X3, X9, X27, X15

(3798) 0x51956c ADD	X0, X20, X3,LSL #3

(3798) 0x519570 LDR	X18, [X0]

(3798) 0x519574 ADD	X8, X18, X17

(3798) 0x519578 STR	X8, [X0]

(3798) 0x51957c SDIV	X11, X1, X25

(3798) 0x519580 MSUB	X10, X11, X25, X1

(3798) 0x519584 ADD	X1, X1, #1

(3798) 0x519588 MADD	X14, X10, X27, X11

(3798) 0x51958c ADD	X30, X20, X14,LSL #3

(3798) 0x519590 LDR	X2, [X30]

(3798) 0x519594 ADD	X12, X2, X17

(3798) 0x519598 STR	X12, [X30]

(3798) 0x51959c CMP	X1, X16

(3798) 0x5195a0 B.EQ	51936c

  (3802) 0x5195a4 SDIV	X13, X1, X25

  (3802) 0x5195a8 ADD	X4, X1, #1

  (3802) 0x5195ac ADD	X6, X1, #2

  (3802) 0x5195b0 ADD	X5, X1, #3

  (3802) 0x5195b4 SDIV	X7, X4, X25

  (3802) 0x5195b8 SDIV	X15, X6, X25

  (3802) 0x5195bc MSUB	X9, X13, X25, X1

  (3802) 0x5195c0 ADD	X1, X1, #4

  (3802) 0x5195c4 SDIV	X11, X5, X25

  (3802) 0x5195c8 MADD	X18, X9, X27, X13

  (3802) 0x5195cc MSUB	X3, X7, X25, X4

  (3802) 0x5195d0 MSUB	X14, X15, X25, X6

  (3802) 0x5195d4 UBFM	X8, X18, #61, #60

  (3802) 0x5195d8 LDR	X10, [X20, X8]

  (3802) 0x5195dc MADD	X0, X3, X27, X7

  (3802) 0x5195e0 MADD	X2, X14, X27, X15

  (3802) 0x5195e4 MSUB	X5, X11, X25, X5

  (3802) 0x5195e8 UBFM	X30, X0, #61, #60

  (3802) 0x5195ec UBFM	X13, X2, #61, #60

  (3802) 0x5195f0 ADD	X12, X10, X17

  (3802) 0x5195f4 MADD	X7, X5, X27, X11

  (3802) 0x5195f8 STR	X12, [X20, X8]

  (3802) 0x5195fc LDR	X4, [X20, X30]

  (3802) 0x519600 UBFM	X9, X7, #61, #60

  (3802) 0x519604 ADD	X6, X4, X17

  (3802) 0x519608 STR	X6, [X20, X30]

  (3802) 0x51960c LDR	X15, [X20, X13]

  (3802) 0x519610 ADD	X3, X15, X17

  (3802) 0x519614 STR	X3, [X20, X13]

  (3802) 0x519618 LDR	X18, [X20, X9]

  (3802) 0x51961c ADD	X0, X18, X17

  (3802) 0x519620 STR	X0, [X20, X9]

  (3802) 0x519624 CMP	X1, X16

  (3802) 0x519628 B.NE	5195a4

(3798) 0x51962c B	51936c

(3798) 0x519630 SDIV	X8, X21, X25

(3798) 0x519634 ADD	X18, X21, #1

(3798) 0x519638 MSUB	X14, X8, X25, X21

(3798) 0x51963c ADD	X10, X8, X14

(3798) 0x519640 ADD	X11, X20, X10,LSL #3

(3798) 0x519644 LDR	X30, [X11]

(3798) 0x519648 ADD	X2, X30, X17

(3798) 0x51964c STR	X2, [X11]

(3798) 0x519650 B	51929c

(3798) 0x519654 SUB	X16, X25, X0

(3798) 0x519658 UBFM	X10, X27, #63, #62

(3798) 0x51965c ANDS	X14, X16, #4160

(3798) 0x519660 SUB	X9, X10, #1

(3798) 0x519664 B.EQ	5196ec

(3798) 0x519668 CMP	X14, #1

(3798) 0x51966c B.EQ	5196c0

(3798) 0x519670 CMP	X14, #2

(3798) 0x519674 B.EQ	51969c

(3798) 0x519678 SDIV	X13, X9, X25

(3798) 0x51967c MOVZ	X0, #2

(3798) 0x519680 MSUB	X12, X13, X25, X9

(3798) 0x519684 ADD	X9, X9, X27

(3798) 0x519688 MADD	X17, X12, X27, X13

(3798) 0x51968c ADD	X30, X20, X17,LSL #3

(3798) 0x519690 LDR	X1, [X30]

(3798) 0x519694 ADD	X2, X2, X1

(3798) 0x519698 STR	X2, [X30]

(3798) 0x51969c SDIV	X3, X9, X25

(3798) 0x5196a0 ADD	X0, X0, #1

(3798) 0x5196a4 MSUB	X4, X3, X25, X9

(3798) 0x5196a8 ADD	X9, X9, X27

(3798) 0x5196ac MADD	X5, X4, X27, X3

(3798) 0x5196b0 ADD	X6, X20, X5,LSL #3

(3798) 0x5196b4 LDR	X7, [X6]

(3798) 0x5196b8 ADD	X2, X2, X7

(3798) 0x5196bc STR	X2, [X6]

(3798) 0x5196c0 SDIV	X15, X9, X25

(3798) 0x5196c4 ADD	X0, X0, #1

(3798) 0x5196c8 MSUB	X18, X15, X25, X9

(3798) 0x5196cc ADD	X9, X9, X27

(3798) 0x5196d0 MADD	X8, X18, X27, X15

(3798) 0x5196d4 ADD	X11, X20, X8,LSL #3

(3798) 0x5196d8 LDR	X10, [X11]

(3798) 0x5196dc ADD	X2, X2, X10

(3798) 0x5196e0 STR	X2, [X11]

(3798) 0x5196e4 CMP	X25, X0

(3798) 0x5196e8 B.EQ	519240

  (3804) 0x5196ec SDIV	X16, X9, X25

  (3804) 0x5196f0 ADD	X14, X9, X27

  (3804) 0x5196f4 ADD	X0, X0, #4

  (3804) 0x5196f8 ADD	X17, X14, X27

  (3804) 0x5196fc ADD	X30, X17, X27

  (3804) 0x519700 SDIV	X12, X14, X25

  (3804) 0x519704 SDIV	X5, X17, X25

  (3804) 0x519708 MSUB	X13, X16, X25, X9

  (3804) 0x51970c ADD	X9, X30, X27

  (3804) 0x519710 SDIV	X15, X30, X25

  (3804) 0x519714 MADD	X1, X13, X27, X16

  (3804) 0x519718 MSUB	X4, X12, X25, X14

  (3804) 0x51971c MSUB	X10, X5, X25, X17

  (3804) 0x519720 UBFM	X6, X1, #61, #60

  (3804) 0x519724 LDR	X3, [X20, X6]

  (3804) 0x519728 MADD	X7, X4, X27, X12

  (3804) 0x51972c MSUB	X14, X15, X25, X30

  (3804) 0x519730 UBFM	X8, X7, #61, #60

  (3804) 0x519734 ADD	X18, X2, X3

  (3804) 0x519738 MADD	X2, X10, X27, X5

  (3804) 0x51973c MADD	X12, X14, X27, X15

  (3804) 0x519740 STR	X18, [X20, X6]

  (3804) 0x519744 LDR	X11, [X20, X8]

  (3804) 0x519748 UBFM	X17, X2, #61, #60

  (3804) 0x51974c UBFM	X13, X12, #61, #60

  (3804) 0x519750 ADD	X16, X18, X11

  (3804) 0x519754 STR	X16, [X20, X8]

  (3804) 0x519758 LDR	X30, [X20, X17]

  (3804) 0x51975c ADD	X1, X16, X30

  (3804) 0x519760 STR	X1, [X20, X17]

  (3804) 0x519764 LDR	X4, [X20, X13]

  (3804) 0x519768 ADD	X2, X1, X4

  (3804) 0x51976c STR	X2, [X20, X13]

  (3804) 0x519770 CMP	X25, X0

  (3804) 0x519774 B.NE	5196ec

(3798) 0x519778 B	519240

(3798) 0x51977c SDIV	X12, X21, X25

(3798) 0x519780 ADD	X1, X21, #1

(3798) 0x519784 MSUB	X13, X12, X25, X21

(3798) 0x519788 MADD	X4, X13, X27, X12

(3798) 0x51978c ADD	X5, X20, X4,LSL #3

(3798) 0x519790 LDR	X6, [X5]

(3798) 0x519794 ADD	X7, X6, X17

(3798) 0x519798 STR	X7, [X5]

(3798) 0x51979c B	51955c

Coverage (%)	Name	Source Location	Module
►99.16+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 75% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.50 to 5.00 cycles (1.10x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50
cycles	3.00	3.00	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
45% of peak store performance is reached (21.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 518e88

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X19, X1, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X22, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X26, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X20, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 51e490 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X3, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 51e540 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 519480 <hypre_CSRMatrixTranspose._omp_fn.0+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X21, X8, #1, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	1	N/A
B.LT 5194c4 <hypre_CSRMatrixTranspose._omp_fn.0+0x63c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50
cycles	3.00	3.00	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
45% of peak store performance is reached (21.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 518e88

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #896]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X19, X1, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X22, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X26, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X20, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 51e490 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X3, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 51e540 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 519480 <hypre_CSRMatrixTranspose._omp_fn.0+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X21, X8, #1, #10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	1	N/A
B.LT 5194c4 <hypre_CSRMatrixTranspose._omp_fn.0+0x63c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixTranspose._omp_fn.0–	0.15	0.02
▼Loop 3798 - csr_matop.c:380-560 - exec–	0.00	0.00
○Loop 3806 - csr_matop.c:380-500 - exec	0.03	0.01
○Loop 3802 - csr_matop.c:380-527 - exec	0.03	0.01
○Loop 3807 - csr_matop.c:483-485 - exec	0.01	0.00
▼Loop 3797 - csr_matop.c:540-548 - exec–	0.00	0.01
○Loop 3799 - csr_matop.c:541-548 - exec	0.07	0.01
▼Loop 3800 - csr_matop.c:553-560 - exec–	0.00	0.00
○Loop 3801 - csr_matop.c:554-560 - exec	0.00	0.00
○Loop 3803 - csr_matop.c:380-527 - exec	0.00	0.00
○Loop 3804 - csr_matop.c:380-513 - exec	0.00	0.00
○Loop 3805 - csr_matop.c:380-513 - exec	0.00	0.00
○Loop 3796 - csr_matop.c:463-540 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code