OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR._omp

	Function: hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1	Module: exec	Source: IJMatrix_parcsr.c:3240-3500 [...]	Coverage (incl. loops): 0.26% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3500

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

[...]

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

3353:                      local_j = aux_j[row_local];

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

3378: 	          cnt_diag = diag_indx;

3379: 	          cnt_offd = offd_indx;

3380: 	          diag_space = diag_i[row_local+1];

3381: 	          offd_space = offd_i[row_local+1];

3382: 	          not_found = 1;

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

3393: 		              not_found = 0;

3394: 		              break;

3395: 		           }

3396: 	                }

3397: 	                if (not_found)

3398: 	                {

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

3412:                                  hypre_printf("Error in row %d ! Too many elements!\n",

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

3427: 		              not_found = 0;

3428: 		              break;

3429: 		           }

3430: 	                }

3431: 	                if (not_found)

3432: 	                {

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

3446:                                  hypre_printf("Error in row %d ! Too many elements !\n",

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

[...]

3500: 		        col_indx += row_len;

0x506440 STP	X29, X30, [SP, #688]!

0x506444 ADD	X29, SP, #0

0x506448 ORR	X12, XZR, X0

0x50644c STP	X19, X20, [SP, #16]

0x506450 STP	X21, X22, [SP, #32]

0x506454 STP	X23, X24, [SP, #48]

0x506458 STP	X25, X26, [SP, #64]

0x50645c STP	X27, X28, [SP, #80]

0x506460 LDP	X22, X0, [X0]

0x506464 STR	X0, [SP, #120]

0x506468 LDP	X1, X28, [X12, #16]

0x50646c STR	X1, [SP, #128]

0x506470 LDP	X5, X2, [X12, #32]

0x506474 STR	X2, [SP, #144]

0x506478 STR	X5, [SP, #264]

0x50647c LDP	X3, X8, [X12, #48]

0x506480 STR	X3, [SP, #136]

0x506484 STR	X8, [SP, #256]

0x506488 LDP	X7, X4, [X12, #64]

0x50648c STR	X4, [SP, #208]

0x506490 STR	X7, [SP, #248]

0x506494 LDP	X6, X9, [X12, #80]

0x506498 STR	X9, [SP, #184]

0x50649c STR	X6, [SP, #200]

0x5064a0 LDP	X10, X11, [X12, #96]

0x5064a4 STR	X11, [SP, #176]

0x5064a8 STR	X10, [SP, #216]

0x5064ac LDP	X13, X24, [X12, #112]

0x5064b0 STR	X13, [SP, #192]

0x5064b4 LDP	X14, X15, [X12, #128]

0x5064b8 STP	X14, X15, [SP, #232]

0x5064bc LDP	X23, X16, [X12, #144]

0x5064c0 STR	X16, [SP, #224]

0x5064c4 LDP	X17, X18, [X12, #160]

0x5064c8 STR	X17, [SP, #112]

0x5064cc STR	X18, [SP, #152]

0x5064d0 LDP	X19, X20, [X12, #176]

0x5064d4 STP	X19, X20, [SP, #160]

0x5064d8 LDP	X25, X26, [X12, #208]

0x5064dc LDP	X21, X20, [X12, #192]

0x5064e0 STR	X12, [SP, #104]

0x5064e4 STR	X25, [SP, #280]

0x5064e8 BL	52df40

0x5064ec ORR	X27, XZR, X0

0x5064f0 BL	52df60

0x5064f4 SDIV	X1, X22, X27

0x5064f8 LDR	X12, [SP, #104]

0x5064fc ORR	X25, XZR, X0

0x506500 LDP	X6, X7, [SP, #240]

0x506504 LDP	X8, X5, [SP, #256]

0x506508 MSUB	X22, X1, X27, X22

0x50650c CMP	X0, X22

0x506510 B.GE	507158

0x506514 MADD	X27, X1, X0, X0

0x506518 ADD	X2, X1, #1

0x50651c UBFM	X19, X25, #61, #60

0x506520 ADD	X22, X21, X25,LSL #3

0x506524 STR	XZR, [X21, X19]

0x506528 ADD	X3, X2, X27

0x50652c STR	X3, [SP, #104]

0x506530 CMP	X27, X3

0x506534 B.GE	507180

0x506538 LDR	X4, [SP, #120]

0x50653c MOVZ	X0, #0

0x506540 ADD	X1, X4, X27,LSL #3

0x506544 ADD	X9, X4, X3,LSL #3

0x506548 SUB	X10, X9, X1

0x50654c SUB	X11, X10, #8

0x506550 UBFM	X13, X11, #3, #63

0x506554 ADD	X14, X13, #1

0x506558 ANDS	X15, X14, #4224

0x50655c B.EQ	5065e0

0x506560 CMP	X15, #1

0x506564 B.EQ	5065cc

0x506568 CMP	X15, #2

0x50656c B.EQ	5065c0

0x506570 CMP	X15, #3

0x506574 B.EQ	5065b4

0x506578 CMP	X15, #4

0x50657c B.EQ	5065a8

0x506580 CMP	X15, #5

0x506584 B.EQ	50659c

0x506588 CMP	X15, #6

0x50658c B.NE	507534

0x506590 LDR	X16, [X1], #8

0x506594 ADD	X0, X0, X16

0x506598 STR	X0, [X22]

0x50659c LDR	X17, [X1], #8

0x5065a0 ADD	X0, X0, X17

0x5065a4 STR	X0, [X22]

0x5065a8 LDR	X18, [X1], #8

0x5065ac ADD	X0, X0, X18

0x5065b0 STR	X0, [X22]

0x5065b4 LDR	X30, [X1], #8

0x5065b8 ADD	X0, X0, X30

0x5065bc STR	X0, [X22]

0x5065c0 LDR	X2, [X1], #8

0x5065c4 ADD	X0, X0, X2

0x5065c8 STR	X0, [X22]

0x5065cc LDR	X3, [X1], #8

0x5065d0 ADD	X0, X0, X3

0x5065d4 STR	X0, [X22]

0x5065d8 CMP	X1, X9

0x5065dc B.EQ	506650

(3558) 0x5065e0 ORR	X10, XZR, X1

(3558) 0x5065e4 ADD	X1, X1, #64

(3558) 0x5065e8 LDR	X4, [X10], #8

(3558) 0x5065ec ADD	X11, X0, X4

(3558) 0x5065f0 STR	X11, [X22]

(3558) 0x5065f4 LDUR	X13, [X1, #456]

(3558) 0x5065f8 ADD	X14, X11, X13

(3558) 0x5065fc STR	X14, [X22]

(3558) 0x506600 LDR	X15, [X10, #8]

(3558) 0x506604 ADD	X16, X14, X15

(3558) 0x506608 STR	X16, [X22]

(3558) 0x50660c LDUR	X17, [X1, #472]

(3558) 0x506610 ADD	X18, X16, X17

(3558) 0x506614 STR	X18, [X22]

(3558) 0x506618 LDUR	X30, [X1, #480]

(3558) 0x50661c ADD	X3, X18, X30

(3558) 0x506620 STR	X3, [X22]

(3558) 0x506624 LDUR	X2, [X1, #488]

(3558) 0x506628 ADD	X0, X3, X2

(3558) 0x50662c STR	X0, [X22]

(3558) 0x506630 LDUR	X10, [X1, #496]

(3558) 0x506634 ADD	X4, X0, X10

(3558) 0x506638 STR	X4, [X22]

(3558) 0x50663c LDUR	X11, [X1, #504]

(3558) 0x506640 ADD	X0, X4, X11

(3558) 0x506644 STR	X0, [X22]

(3558) 0x506648 CMP	X1, X9

(3558) 0x50664c B.NE	5065e0

0x506650 STP	X6, X7, [SP, #240]

0x506654 STP	X8, X5, [SP, #256]

0x506658 STR	X12, [SP, #272]

0x50665c BL	410d30

0x506660 LDR	X12, [SP, #272]

0x506664 LDP	X9, X7, [SP, #240]

0x506668 LDP	X8, X5, [SP, #256]

0x50666c CBNZ	X25, 507494

0x506670 CMP	X26, #0

0x506674 B.LE	506788

0x506678 ORR	X1, XZR, X21

0x50667c UBFM	X21, X26, #61, #60

0x506680 SUB	X25, X21, #8

0x506684 LDR	X0, [X1], #8

0x506688 UBFM	X6, X25, #3, #63

0x50668c ADD	X22, X6, #1

0x506690 ANDS	X13, X22, #4224

0x506694 ADD	X26, X1, X26,LSL #3

0x506698 B.EQ	506728

0x50669c CMP	X13, #1

0x5066a0 B.EQ	506714

0x5066a4 CMP	X13, #2

0x5066a8 B.EQ	506708

0x5066ac CMP	X13, #3

0x5066b0 B.EQ	5066fc

0x5066b4 CMP	X13, #4

0x5066b8 B.EQ	5066f0

0x5066bc CMP	X13, #5

0x5066c0 B.EQ	5066e4

0x5066c4 CMP	X13, #6

0x5066c8 B.EQ	5066d8

0x5066cc LDR	X14, [X1]

0x5066d0 ADD	X0, X0, X14

0x5066d4 STR	X0, [X1], #8

0x5066d8 LDR	X15, [X1]

0x5066dc ADD	X0, X0, X15

0x5066e0 STR	X0, [X1], #8

0x5066e4 LDR	X16, [X1]

0x5066e8 ADD	X0, X0, X16

0x5066ec STR	X0, [X1], #8

0x5066f0 LDR	X17, [X1]

0x5066f4 ADD	X0, X0, X17

0x5066f8 STR	X0, [X1], #8

0x5066fc LDR	X18, [X1]

0x506700 ADD	X0, X0, X18

0x506704 STR	X0, [X1], #8

0x506708 LDR	X30, [X1]

0x50670c ADD	X0, X0, X30

0x506710 STR	X0, [X1], #8

0x506714 LDR	X3, [X1]

0x506718 ADD	X0, X0, X3

0x50671c STR	X0, [X1], #8

0x506720 CMP	X1, X26

0x506724 B.EQ	506788

(3576) 0x506728 LDR	X10, [X1]

(3576) 0x50672c ORR	X2, XZR, X1

(3576) 0x506730 ADD	X11, X0, X10

(3576) 0x506734 STR	X11, [X2], #8

(3576) 0x506738 LDR	X4, [X1, #8]

(3576) 0x50673c ADD	X21, X11, X4

(3576) 0x506740 STR	X21, [X1, #8]

(3576) 0x506744 LDR	X25, [X2, #8]

(3576) 0x506748 ADD	X6, X21, X25

(3576) 0x50674c STR	X6, [X2, #8]

(3576) 0x506750 LDP	X22, X13, [X1, #24]

(3576) 0x506754 LDP	X15, X16, [X1, #40]

(3576) 0x506758 ADD	X1, X1, #64

(3576) 0x50675c ADD	X14, X6, X22

(3576) 0x506760 ADD	X17, X14, X13

(3576) 0x506764 LDUR	X3, [X1, #504]

(3576) 0x506768 ADD	X18, X17, X15

(3576) 0x50676c STP	X14, X17, [X1, #984]

(3576) 0x506770 ADD	X30, X18, X16

(3576) 0x506774 STP	X18, X30, [X1, #1000]

(3576) 0x506778 ADD	X0, X30, X3

(3576) 0x50677c STUR	X0, [X1, #504]

(3576) 0x506780 CMP	X1, X26

(3576) 0x506784 B.NE	506728

0x506788 STP	X9, X7, [SP, #240]

0x50678c MOVZ	X21, #0

0x506790 STP	X8, X5, [SP, #256]

0x506794 STR	X12, [SP, #272]

0x506798 BL	410d30

0x50679c LDR	X12, [SP, #272]

0x5067a0 LDP	X11, X7, [SP, #240]

0x5067a4 LDP	X8, X5, [SP, #256]

0x5067a8 LDR	X9, [SP, #104]

0x5067ac CMP	X27, X9

0x5067b0 B.GE	506a40

0x5067b4 LDR	X0, [SP, #152]

0x5067b8 MOVZ	X9, #0

0x5067bc MOVN	X22, #0

0x5067c0 ORR	X26, XZR, X5

0x5067c4 LDR	X2, [SP, #112]

0x5067c8 LDR	X10, [SP, #136]

0x5067cc SUB	X4, X0, #1

0x5067d0 LDR	X14, [SP, #160]

0x5067d4 UBFM	X6, X4, #1, #63

0x5067d8 LDR	X5, [SP, #224]

0x5067dc ADD	X25, X10, X2,LSL #3

0x5067e0 STR	X12, [SP, #224]

0x5067e4 ADD	X15, X14, #16

0x5067e8 ADD	X18, X25, #8

0x5067ec ADD	X4, X15, X6,LSL #4

0x5067f0 STR	X25, [SP, #136]

0x5067f4 HINT	#0

0x5067f8 HINT	#0

0x5067fc HINT	#0

      (3559) 0x506800 LDR	X30, [SP, #136]

      (3559) 0x506804 LDP	X16, X17, [SP, #120]

      (3559) 0x506808 LDR	X3, [X30]

      (3559) 0x50680c LDR	X25, [X17, X27,LSL #3]

      (3559) 0x506810 LDR	X12, [X16, X27,LSL #3]

      (3559) 0x506814 CMP	X25, X3

      (3559) 0x506818 B.LT	506bd8

      (3559) 0x50681c LDR	X1, [X18]

      (3559) 0x506820 CMP	X25, X1

      (3559) 0x506824 B.GE	506bd8

      (3559) 0x506828 LDR	X16, [SP, #176]

      (3559) 0x50682c SUB	X30, X25, X3

      (3559) 0x506830 UBFM	X13, X30, #61, #60

      (3559) 0x506834 CBNZ	X16, 506f18

    (3569) 0x506838 LDR	X1, [SP, #144]

    (3569) 0x50683c ADD	X17, X13, #8

    (3569) 0x506840 ADD	X16, X12, X21

    (3569) 0x506844 LDR	X15, [SP, #192]

    (3569) 0x506848 LDR	X30, [X11, X17]

    (3569) 0x50684c ADD	X0, X1, #56

    (3569) 0x506850 LDP	X10, X2, [X0]

    (3569) 0x506854 LDR	X17, [X15, X17]

    (3569) 0x506858 ADD	X1, X2, X13

    (3569) 0x50685c ADD	X0, X10, X13

    (3569) 0x506860 LDR	X2, [X2, X13]

    (3569) 0x506864 LDR	X3, [X10, X13]

    (3569) 0x506868 ORR	X14, XZR, X2

    (3569) 0x50686c ORR	X15, XZR, X3

    (3569) 0x506870 CMP	X12, #0

    (3569) 0x506874 B.LE	5077c0

    (3569) 0x506878 LDR	X10, [SP, #192]

    (3569) 0x50687c ORR	X6, XZR, X0

    (3569) 0x506880 STP	X25, X1, [SP, #240]

    (3569) 0x506884 LDR	X12, [SP, #232]

      (3572) 0x506888 LDR	X1, [X28, X21,LSL #3]

      (3572) 0x50688c CMP	X8, X1

      (3572) 0x506890 CCMP	X7, X1, #1, #13

      (3572) 0x506894 B.GE	506a5c

      (3572) 0x506898 LDR	X0, [X11, X13]

      (3572) 0x50689c CMP	X2, X0

      (3572) 0x5068a0 B.LE	5069f4

      (3572) 0x5068a4 SUB	X25, X2, X0

      (3572) 0x5068a8 ANDS	X25, X25, #4224

      (3572) 0x5068ac B.EQ	506958

      (3572) 0x5068b0 CMP	X25, #1

      (3572) 0x5068b4 B.EQ	506940

      (3572) 0x5068b8 CMP	X25, #2

      (3572) 0x5068bc B.EQ	506930

      (3572) 0x5068c0 CMP	X25, #3

      (3572) 0x5068c4 B.EQ	506920

      (3572) 0x5068c8 CMP	X25, #4

      (3572) 0x5068cc B.EQ	506910

      (3572) 0x5068d0 CMP	X25, #5

      (3572) 0x5068d4 B.EQ	506900

      (3572) 0x5068d8 CMP	X25, #6

      (3572) 0x5068dc B.EQ	5068f0

      (3572) 0x5068e0 LDR	X25, [X23, X0,LSL #3]

      (3572) 0x5068e4 CMP	X1, X25

      (3572) 0x5068e8 B.EQ	506ef8

      (3572) 0x5068ec ADD	X0, X0, #1

      (3572) 0x5068f0 LDR	X25, [X23, X0,LSL #3]

      (3572) 0x5068f4 CMP	X1, X25

      (3572) 0x5068f8 B.EQ	506ef8

      (3572) 0x5068fc ADD	X0, X0, #1

      (3572) 0x506900 LDR	X25, [X23, X0,LSL #3]

      (3572) 0x506904 CMP	X1, X25

      (3572) 0x506908 B.EQ	506ef8

      (3572) 0x50690c ADD	X0, X0, #1

      (3572) 0x506910 LDR	X25, [X23, X0,LSL #3]

      (3572) 0x506914 CMP	X1, X25

      (3572) 0x506918 B.EQ	506ef8

      (3572) 0x50691c ADD	X0, X0, #1

      (3572) 0x506920 LDR	X25, [X23, X0,LSL #3]

      (3572) 0x506924 CMP	X1, X25

      (3572) 0x506928 B.EQ	506ef8

      (3572) 0x50692c ADD	X0, X0, #1

      (3572) 0x506930 LDR	X25, [X23, X0,LSL #3]

      (3572) 0x506934 CMP	X1, X25

      (3572) 0x506938 B.EQ	506ef8

      (3572) 0x50693c ADD	X0, X0, #1

      (3572) 0x506940 LDR	X25, [X23, X0,LSL #3]

      (3572) 0x506944 CMP	X1, X25

      (3572) 0x506948 B.EQ	506ef8

      (3572) 0x50694c ADD	X0, X0, #1

      (3572) 0x506950 CMP	X2, X0

      (3572) 0x506954 B.EQ	5069f4

      (3572) 0x506958 ORR	X25, XZR, X9

      (3572) 0x50695c STR	X3, [SP, #112]

        (3573) 0x506960 LDR	X9, [X23, X0,LSL #3]

        (3573) 0x506964 CMP	X1, X9

        (3573) 0x506968 B.EQ	506ef0

        (3573) 0x50696c ADD	X0, X0, #1

        (3573) 0x506970 LDR	X3, [X23, X0,LSL #3]

        (3573) 0x506974 ORR	X9, XZR, X0

        (3573) 0x506978 CMP	X1, X3

        (3573) 0x50697c B.EQ	506ef0

        (3573) 0x506980 ADD	X0, X0, #1

        (3573) 0x506984 LDR	X3, [X23, X0,LSL #3]

        (3573) 0x506988 CMP	X1, X3

        (3573) 0x50698c B.EQ	506ef0

        (3573) 0x506990 ADD	X0, X9, #2

        (3573) 0x506994 LDR	X3, [X23, X0,LSL #3]

        (3573) 0x506998 CMP	X1, X3

        (3573) 0x50699c B.EQ	506ef0

        (3573) 0x5069a0 ADD	X0, X9, #3

        (3573) 0x5069a4 LDR	X3, [X23, X0,LSL #3]

        (3573) 0x5069a8 CMP	X1, X3

        (3573) 0x5069ac B.EQ	506ef0

        (3573) 0x5069b0 ADD	X0, X9, #4

        (3573) 0x5069b4 LDR	X3, [X23, X0,LSL #3]

        (3573) 0x5069b8 CMP	X1, X3

        (3573) 0x5069bc B.EQ	506ef0

        (3573) 0x5069c0 ADD	X0, X9, #5

        (3573) 0x5069c4 LDR	X3, [X23, X0,LSL #3]

        (3573) 0x5069c8 CMP	X1, X3

        (3573) 0x5069cc B.EQ	506ef0

        (3573) 0x5069d0 ADD	X0, X9, #6

        (3573) 0x5069d4 LDR	X3, [X23, X0,LSL #3]

        (3573) 0x5069d8 CMP	X1, X3

        (3573) 0x5069dc B.EQ	506ef0

        (3573) 0x5069e0 ADD	X0, X9, #7

        (3573) 0x5069e4 CMP	X2, X0

        (3573) 0x5069e8 B.NE	506960

      (3572) 0x5069ec LDR	X3, [SP, #112]

      (3572) 0x5069f0 ORR	X9, XZR, X25

      (3572) 0x5069f4 CMP	X30, X14

      (3572) 0x5069f8 B.LE	5074b8

      (3572) 0x5069fc LDR	D1, [X26, X21,LSL #3]

      (3572) 0x506a00 UBFM	X25, X14, #61, #60

      (3572) 0x506a04 ADD	X14, X14, #1

      (3572) 0x506a08 STR	X1, [X23, X25]

      (3572) 0x506a0c STR	D1, [X5, X25]

      (3572) 0x506a10 ADD	X21, X21, #1

      (3572) 0x506a14 CMP	X21, X16

      (3572) 0x506a18 B.NE	506888

    (3569) 0x506a1c LDR	X1, [SP, #248]

    (3569) 0x506a20 ORR	X0, XZR, X6

    (3569) 0x506a24 STR	X15, [X0]

    (3569) 0x506a28 ADD	X27, X27, #1

    (3569) 0x506a2c ORR	X21, XZR, X16

    (3569) 0x506a30 LDR	X12, [SP, #104]

    (3569) 0x506a34 STR	X14, [X1]

    (3569) 0x506a38 CMP	X12, X27

    (3569) 0x506a3c B.NE	506800

(3574) 0x506a40 LDP	X19, X20, [SP, #16]

(3574) 0x506a44 LDP	X21, X22, [SP, #32]

(3574) 0x506a48 LDP	X23, X24, [SP, #48]

(3574) 0x506a4c LDP	X25, X26, [SP, #64]

(3574) 0x506a50 LDP	X27, X28, [SP, #80]

(3574) 0x506a54 LDP	X29, X30, [SP], #336

(3574) 0x506a58 RET

  (3570) 0x506a5c LDR	X0, [X10, X13]

  (3570) 0x506a60 CMP	X3, X0

  (3570) 0x506a64 B.LE	506bb8

  (3570) 0x506a68 SUB	X25, X3, X0

  (3570) 0x506a6c ANDS	X25, X25, #4224

  (3570) 0x506a70 B.EQ	506b1c

  (3570) 0x506a74 CMP	X25, #1

  (3570) 0x506a78 B.EQ	506b04

  (3570) 0x506a7c CMP	X25, #2

  (3570) 0x506a80 B.EQ	506af4

  (3570) 0x506a84 CMP	X25, #3

  (3570) 0x506a88 B.EQ	506ae4

  (3570) 0x506a8c CMP	X25, #4

  (3570) 0x506a90 B.EQ	506ad4

  (3570) 0x506a94 CMP	X25, #5

  (3570) 0x506a98 B.EQ	506ac4

  (3570) 0x506a9c CMP	X25, #6

  (3570) 0x506aa0 B.EQ	506ab4

  (3570) 0x506aa4 LDR	X25, [X24, X0,LSL #3]

  (3570) 0x506aa8 CMP	X1, X25

  (3570) 0x506aac B.EQ	506f0c

  (3570) 0x506ab0 ADD	X0, X0, #1

  (3570) 0x506ab4 LDR	X25, [X24, X0,LSL #3]

  (3570) 0x506ab8 CMP	X1, X25

  (3570) 0x506abc B.EQ	506f0c

  (3570) 0x506ac0 ADD	X0, X0, #1

  (3570) 0x506ac4 LDR	X25, [X24, X0,LSL #3]

  (3570) 0x506ac8 CMP	X1, X25

  (3570) 0x506acc B.EQ	506f0c

  (3570) 0x506ad0 ADD	X0, X0, #1

  (3570) 0x506ad4 LDR	X25, [X24, X0,LSL #3]

  (3570) 0x506ad8 CMP	X1, X25

  (3570) 0x506adc B.EQ	506f0c

  (3570) 0x506ae0 ADD	X0, X0, #1

  (3570) 0x506ae4 LDR	X25, [X24, X0,LSL #3]

  (3570) 0x506ae8 CMP	X1, X25

  (3570) 0x506aec B.EQ	506f0c

  (3570) 0x506af0 ADD	X0, X0, #1

  (3570) 0x506af4 LDR	X25, [X24, X0,LSL #3]

  (3570) 0x506af8 CMP	X1, X25

  (3570) 0x506afc B.EQ	506f0c

  (3570) 0x506b00 ADD	X0, X0, #1

  (3570) 0x506b04 LDR	X25, [X24, X0,LSL #3]

  (3570) 0x506b08 CMP	X1, X25

  (3570) 0x506b0c B.EQ	506f0c

  (3570) 0x506b10 ADD	X0, X0, #1

  (3570) 0x506b14 CMP	X3, X0

  (3570) 0x506b18 B.EQ	506bb8

  (3570) 0x506b1c ORR	X25, XZR, X9

  (3570) 0x506b20 STR	X2, [SP, #112]

    (3575) 0x506b24 LDR	X9, [X24, X0,LSL #3]

    (3575) 0x506b28 CMP	X1, X9

    (3575) 0x506b2c B.EQ	506f04

    (3575) 0x506b30 ADD	X0, X0, #1

    (3575) 0x506b34 LDR	X2, [X24, X0,LSL #3]

    (3575) 0x506b38 ORR	X9, XZR, X0

    (3575) 0x506b3c CMP	X1, X2

    (3575) 0x506b40 B.EQ	506f04

    (3575) 0x506b44 ADD	X0, X0, #1

    (3575) 0x506b48 LDR	X2, [X24, X0,LSL #3]

    (3575) 0x506b4c CMP	X1, X2

    (3575) 0x506b50 B.EQ	506f04

    (3575) 0x506b54 ADD	X0, X9, #2

    (3575) 0x506b58 LDR	X2, [X24, X0,LSL #3]

    (3575) 0x506b5c CMP	X1, X2

    (3575) 0x506b60 B.EQ	506f04

    (3575) 0x506b64 ADD	X0, X9, #3

    (3575) 0x506b68 LDR	X2, [X24, X0,LSL #3]

    (3575) 0x506b6c CMP	X1, X2

    (3575) 0x506b70 B.EQ	506f04

    (3575) 0x506b74 ADD	X0, X9, #4

    (3575) 0x506b78 LDR	X2, [X24, X0,LSL #3]

    (3575) 0x506b7c CMP	X1, X2

    (3575) 0x506b80 B.EQ	506f04

    (3575) 0x506b84 ADD	X0, X9, #5

    (3575) 0x506b88 LDR	X2, [X24, X0,LSL #3]

    (3575) 0x506b8c CMP	X1, X2

    (3575) 0x506b90 B.EQ	506f04

    (3575) 0x506b94 ADD	X0, X9, #6

    (3575) 0x506b98 LDR	X2, [X24, X0,LSL #3]

    (3575) 0x506b9c CMP	X1, X2

    (3575) 0x506ba0 B.EQ	506f04

    (3575) 0x506ba4 ADD	X0, X9, #7

    (3575) 0x506ba8 CMP	X3, X0

    (3575) 0x506bac B.NE	506b24

  (3570) 0x506bb0 LDR	X2, [SP, #112]

  (3570) 0x506bb4 ORR	X9, XZR, X25

  (3570) 0x506bb8 CMP	X17, X15

  (3570) 0x506bbc B.LE	50759c

  (3570) 0x506bc0 LDR	D31, [X26, X21,LSL #3]

  (3570) 0x506bc4 UBFM	X0, X15, #61, #60

  (3570) 0x506bc8 ADD	X15, X15, #1

  (3570) 0x506bcc STR	X1, [X24, X0]

  (3570) 0x506bd0 STR	D31, [X12, X0]

  (3570) 0x506bd4 B	506a10

      (3559) 0x506bd8 LDR	X2, [SP, #144]

      (3559) 0x506bdc CBNZ	X2, 506c10

        (3560) 0x506be0 ADD	X21, X21, X12

        (3560) 0x506be4 LDR	X12, [SP, #104]

        (3560) 0x506be8 ADD	X27, X27, #1

        (3560) 0x506bec CMP	X12, X27

        (3560) 0x506bf0 B.NE	506800

        (3560) 0x506bf4 LDP	X19, X20, [SP, #16]

        (3560) 0x506bf8 LDP	X21, X22, [SP, #32]

        (3560) 0x506bfc LDP	X23, X24, [SP, #48]

        (3560) 0x506c00 LDP	X25, X26, [SP, #64]

        (3560) 0x506c04 LDP	X27, X28, [SP, #80]

        (3560) 0x506c08 LDP	X29, X30, [SP], #336

        (3560) 0x506c0c RET

        (3560) 0x506c10 LDR	X10, [SP, #152]

        (3560) 0x506c14 CMP	X10, #0

        (3560) 0x506c18 B.LE	506be0

        (3560) 0x506c1c LDP	X2, X0, [SP, #160]

        (3560) 0x506c20 ADD	X15, X28, X12,LSL #3

        (3560) 0x506c24 MOVZ	X14, #0

        (3560) 0x506c28 B	506c38

          (3561) 0x506c2c ADD	X2, X2, #16

          (3561) 0x506c30 CMP	X2, X4

          (3561) 0x506c34 B.EQ	506be0

          (3561) 0x506c38 LDP	X13, X16, [X2]

          (3561) 0x506c3c ORR	X6, XZR, X14

          (3561) 0x506c40 ADD	X14, X14, X16

          (3561) 0x506c44 CMP	X25, X13

          (3561) 0x506c48 B.NE	506c2c

          (3561) 0x506c4c CMP	X12, #0

          (3561) 0x506c50 B.LE	506c2c

          (3561) 0x506c54 CMP	X16, #0

          (3561) 0x506c58 B.LE	506c2c

          (3561) 0x506c5c ADD	X10, X0, X6,LSL #3

          (3561) 0x506c60 ORR	X3, XZR, X28

          (3561) 0x506c64 ADD	X6, X0, X14,LSL #3

            (3563) 0x506c68 SUB	X30, X6, X10

            (3563) 0x506c6c ORR	X1, XZR, X10

            (3563) 0x506c70 SUB	X13, X30, #8

            (3563) 0x506c74 UBFM	X16, X13, #3, #63

            (3563) 0x506c78 ADD	X17, X16, #1

            (3563) 0x506c7c ANDS	X30, X17, #4224

            (3563) 0x506c80 B.EQ	506d58

            (3563) 0x506c84 CMP	X30, #1

            (3563) 0x506c88 B.EQ	506d2c

            (3563) 0x506c8c CMP	X30, #2

            (3563) 0x506c90 B.EQ	506d18

            (3563) 0x506c94 CMP	X30, #3

            (3563) 0x506c98 B.EQ	506d04

            (3563) 0x506c9c CMP	X30, #4

            (3563) 0x506ca0 B.EQ	506cf0

            (3563) 0x506ca4 CMP	X30, #5

            (3563) 0x506ca8 B.EQ	506cdc

            (3563) 0x506cac CMP	X30, #6

            (3563) 0x506cb0 B.EQ	506cc8

            (3563) 0x506cb4 LDR	X13, [X3]

            (3563) 0x506cb8 LDR	X1, [X10]

            (3563) 0x506cbc CMP	X13, X1

            (3563) 0x506cc0 B.EQ	506edc

            (3563) 0x506cc4 ADD	X1, X10, #8

            (3563) 0x506cc8 LDR	X30, [X1]

            (3563) 0x506ccc LDR	X13, [X3]

            (3563) 0x506cd0 CMP	X13, X30

            (3563) 0x506cd4 B.EQ	506ec8

            (3563) 0x506cd8 ADD	X1, X1, #8

            (3563) 0x506cdc LDR	X30, [X1]

            (3563) 0x506ce0 LDR	X13, [X3]

            (3563) 0x506ce4 CMP	X13, X30

            (3563) 0x506ce8 B.EQ	506eb4

            (3563) 0x506cec ADD	X1, X1, #8

            (3563) 0x506cf0 LDR	X30, [X1]

            (3563) 0x506cf4 LDR	X13, [X3]

            (3563) 0x506cf8 CMP	X13, X30

            (3563) 0x506cfc B.EQ	506ea0

            (3563) 0x506d00 ADD	X1, X1, #8

            (3563) 0x506d04 LDR	X30, [X1]

            (3563) 0x506d08 LDR	X13, [X3]

            (3563) 0x506d0c CMP	X13, X30

            (3563) 0x506d10 B.EQ	506e8c

            (3563) 0x506d14 ADD	X1, X1, #8

            (3563) 0x506d18 LDR	X30, [X1]

            (3563) 0x506d1c LDR	X13, [X3]

            (3563) 0x506d20 CMP	X13, X30

            (3563) 0x506d24 B.EQ	506e78

            (3563) 0x506d28 ADD	X1, X1, #8

            (3563) 0x506d2c LDR	X30, [X1]

            (3563) 0x506d30 LDR	X13, [X3]

            (3563) 0x506d34 CMP	X13, X30

            (3563) 0x506d38 B.NE	506d4c

            (3563) 0x506d3c STR	X22, [X1]

            (3563) 0x506d40 LDR	X16, [X20, X19]

            (3563) 0x506d44 ADD	X17, X16, #1

            (3563) 0x506d48 STR	X17, [X20, X19]

            (3563) 0x506d4c ADD	X1, X1, #8

            (3563) 0x506d50 CMP	X1, X6

            (3563) 0x506d54 B.EQ	506e68

              (3562) 0x506d58 LDR	X30, [X1]

              (3562) 0x506d5c LDR	X13, [X3]

              (3562) 0x506d60 CMP	X13, X30

              (3562) 0x506d64 B.NE	506d78

              (3562) 0x506d68 STR	X22, [X1]

              (3562) 0x506d6c LDR	X16, [X20, X19]

              (3562) 0x506d70 ADD	X17, X16, #1

              (3562) 0x506d74 STR	X17, [X20, X19]

              (3562) 0x506d78 LDR	X16, [X3]

              (3562) 0x506d7c ADD	X30, X1, #8

              (3562) 0x506d80 LDR	X13, [X1, #8]

              (3562) 0x506d84 CMP	X16, X13

              (3562) 0x506d88 B.NE	506d9c

              (3562) 0x506d8c STR	X22, [X1, #8]

              (3562) 0x506d90 LDR	X1, [X20, X19]

              (3562) 0x506d94 ADD	X17, X1, #1

              (3562) 0x506d98 STR	X17, [X20, X19]

              (3562) 0x506d9c LDR	X13, [X3]

              (3562) 0x506da0 LDR	X16, [X30, #8]

              (3562) 0x506da4 CMP	X13, X16

              (3562) 0x506da8 B.NE	506dbc

              (3562) 0x506dac STR	X22, [X30, #8]

              (3562) 0x506db0 LDR	X1, [X20, X19]

              (3562) 0x506db4 ADD	X17, X1, #1

              (3562) 0x506db8 STR	X17, [X20, X19]

              (3562) 0x506dbc LDR	X13, [X3]

              (3562) 0x506dc0 LDR	X16, [X30, #16]

              (3562) 0x506dc4 CMP	X13, X16

              (3562) 0x506dc8 B.NE	506ddc

              (3562) 0x506dcc STR	X22, [X30, #16]

              (3562) 0x506dd0 LDR	X1, [X20, X19]

              (3562) 0x506dd4 ADD	X17, X1, #1

              (3562) 0x506dd8 STR	X17, [X20, X19]

              (3562) 0x506ddc LDR	X13, [X3]

              (3562) 0x506de0 LDR	X16, [X30, #24]

              (3562) 0x506de4 CMP	X13, X16

              (3562) 0x506de8 B.NE	506dfc

              (3562) 0x506dec STR	X22, [X30, #24]

              (3562) 0x506df0 LDR	X1, [X20, X19]

              (3562) 0x506df4 ADD	X17, X1, #1

              (3562) 0x506df8 STR	X17, [X20, X19]

              (3562) 0x506dfc LDR	X13, [X3]

              (3562) 0x506e00 LDR	X16, [X30, #32]

              (3562) 0x506e04 CMP	X13, X16

              (3562) 0x506e08 B.NE	506e1c

              (3562) 0x506e0c STR	X22, [X30, #32]

              (3562) 0x506e10 LDR	X1, [X20, X19]

              (3562) 0x506e14 ADD	X17, X1, #1

              (3562) 0x506e18 STR	X17, [X20, X19]

              (3562) 0x506e1c LDR	X13, [X3]

              (3562) 0x506e20 LDR	X16, [X30, #40]

              (3562) 0x506e24 CMP	X13, X16

              (3562) 0x506e28 B.NE	506e3c

              (3562) 0x506e2c STR	X22, [X30, #40]

              (3562) 0x506e30 LDR	X1, [X20, X19]

              (3562) 0x506e34 ADD	X17, X1, #1

              (3562) 0x506e38 STR	X17, [X20, X19]

              (3562) 0x506e3c LDR	X13, [X3]

              (3562) 0x506e40 LDR	X16, [X30, #48]

              (3562) 0x506e44 CMP	X13, X16

              (3562) 0x506e48 B.NE	506e5c

              (3562) 0x506e4c STR	X22, [X30, #48]

              (3562) 0x506e50 LDR	X1, [X20, X19]

              (3562) 0x506e54 ADD	X17, X1, #1

              (3562) 0x506e58 STR	X17, [X20, X19]

              (3562) 0x506e5c ADD	X1, X30, #56

              (3562) 0x506e60 CMP	X1, X6

              (3562) 0x506e64 B.NE	506d58

            (3563) 0x506e68 ADD	X3, X3, #8

            (3563) 0x506e6c CMP	X3, X15

            (3563) 0x506e70 B.NE	506c68

          (3561) 0x506e74 B	506c2c

            (3563) 0x506e78 STR	X22, [X1]

            (3563) 0x506e7c LDR	X16, [X20, X19]

            (3563) 0x506e80 ADD	X17, X16, #1

            (3563) 0x506e84 STR	X17, [X20, X19]

            (3563) 0x506e88 B	506d28

            (3563) 0x506e8c STR	X22, [X1]

            (3563) 0x506e90 LDR	X16, [X20, X19]

            (3563) 0x506e94 ADD	X17, X16, #1

            (3563) 0x506e98 STR	X17, [X20, X19]

            (3563) 0x506e9c B	506d14

            (3563) 0x506ea0 STR	X22, [X1]

            (3563) 0x506ea4 LDR	X16, [X20, X19]

            (3563) 0x506ea8 ADD	X17, X16, #1

            (3563) 0x506eac STR	X17, [X20, X19]

            (3563) 0x506eb0 B	506d00

            (3563) 0x506eb4 STR	X22, [X1]

            (3563) 0x506eb8 LDR	X16, [X20, X19]

            (3563) 0x506ebc ADD	X17, X16, #1

            (3563) 0x506ec0 STR	X17, [X20, X19]

            (3563) 0x506ec4 B	506cec

            (3563) 0x506ec8 STR	X22, [X1]

            (3563) 0x506ecc LDR	X16, [X20, X19]

            (3563) 0x506ed0 ADD	X17, X16, #1

            (3563) 0x506ed4 STR	X17, [X20, X19]

            (3563) 0x506ed8 B	506cd8

            (3563) 0x506edc STR	X22, [X10]

            (3563) 0x506ee0 LDR	X16, [X20, X19]

            (3563) 0x506ee4 ADD	X17, X16, #1

            (3563) 0x506ee8 STR	X17, [X20, X19]

            (3563) 0x506eec B	506cc4

      (3572) 0x506ef0 LDR	X3, [SP, #112]

      (3572) 0x506ef4 ORR	X9, XZR, X25

      (3572) 0x506ef8 LDR	D2, [X26, X21,LSL #3]

      (3572) 0x506efc STR	D2, [X5, X0,LSL #3]

      (3572) 0x506f00 B	506a10

  (3570) 0x506f04 LDR	X2, [SP, #112]

  (3570) 0x506f08 ORR	X9, XZR, X25

  (3570) 0x506f0c LDR	D0, [X26, X21,LSL #3]

  (3570) 0x506f10 STR	D0, [X12, X0,LSL #3]

  (3570) 0x506f14 B	506a10

      (3559) 0x506f18 LDR	X2, [SP, #184]

      (3559) 0x506f1c LDR	X15, [SP, #216]

      (3559) 0x506f20 LDR	X14, [SP, #200]

      (3559) 0x506f24 LDR	X2, [X2, X13]

      (3559) 0x506f28 LDR	X10, [X15, X13]

      (3559) 0x506f2c LDR	X16, [SP, #208]

      (3559) 0x506f30 LDR	X6, [X14, X13]

      (3559) 0x506f34 SUB	X3, X10, X2

      (3559) 0x506f38 LDR	X25, [X16, X13]

      (3559) 0x506f3c CMP	X12, X3

      (3559) 0x506f40 B.GT	50741c

      (3559) 0x506f44 CMP	X12, #0

      (3559) 0x506f48 B.LE	506be4

      (3559) 0x506f4c MOVZ	X3, #0

      (3559) 0x506f50 MOVZ	X14, #0

      (3559) 0x506f54 ADD	X12, X21, X12

      (3559) 0x506f58 ORR	X15, XZR, X2

      (3559) 0x506f5c HINT	#0

        (3564) 0x506f60 LDR	X1, [X28, X21,LSL #3]

        (3564) 0x506f64 CMP	X2, #0

        (3564) 0x506f68 B.LE	5070ac

          (3567) 0x506f6c ANDS	X17, X2, #4224

          (3567) 0x506f70 MOVZ	X0, #0

          (3567) 0x506f74 B.EQ	507020

          (3567) 0x506f78 CMP	X17, #1

          (3567) 0x506f7c B.EQ	507008

          (3567) 0x506f80 CMP	X17, #2

          (3567) 0x506f84 B.EQ	506ff8

          (3567) 0x506f88 CMP	X17, #3

          (3567) 0x506f8c B.EQ	506fe8

          (3567) 0x506f90 CMP	X17, #4

          (3567) 0x506f94 B.EQ	506fd8

          (3567) 0x506f98 CMP	X17, #5

          (3567) 0x506f9c B.EQ	506fc8

          (3567) 0x506fa0 CMP	X17, #6

          (3567) 0x506fa4 B.EQ	506fb8

          (3567) 0x506fa8 LDR	X30, [X25]

          (3567) 0x506fac CMP	X30, X1

          (3567) 0x506fb0 B.EQ	507128

          (3567) 0x506fb4 MOVZ	X0, #1

          (3567) 0x506fb8 LDR	X16, [X25, X0,LSL #3]

          (3567) 0x506fbc CMP	X16, X1

          (3567) 0x506fc0 B.EQ	507128

          (3567) 0x506fc4 ADD	X0, X0, #1

          (3567) 0x506fc8 LDR	X17, [X25, X0,LSL #3]

          (3567) 0x506fcc CMP	X17, X1

          (3567) 0x506fd0 B.EQ	507128

          (3567) 0x506fd4 ADD	X0, X0, #1

          (3567) 0x506fd8 LDR	X30, [X25, X0,LSL #3]

          (3567) 0x506fdc CMP	X30, X1

          (3567) 0x506fe0 B.EQ	507128

          (3567) 0x506fe4 ADD	X0, X0, #1

          (3567) 0x506fe8 LDR	X16, [X25, X0,LSL #3]

          (3567) 0x506fec CMP	X16, X1

          (3567) 0x506ff0 B.EQ	507128

          (3567) 0x506ff4 ADD	X0, X0, #1

          (3567) 0x506ff8 LDR	X17, [X25, X0,LSL #3]

          (3567) 0x506ffc CMP	X17, X1

          (3567) 0x507000 B.EQ	507128

          (3567) 0x507004 ADD	X0, X0, #1

          (3567) 0x507008 LDR	X30, [X25, X0,LSL #3]

          (3567) 0x50700c CMP	X30, X1

          (3567) 0x507010 B.EQ	507128

          (3567) 0x507014 ADD	X0, X0, #1

          (3567) 0x507018 CMP	X2, X0

          (3567) 0x50701c B.EQ	5070ac

            (3568) 0x507020 LDR	X16, [X25, X0,LSL #3]

            (3568) 0x507024 CMP	X16, X1

            (3568) 0x507028 B.EQ	507128

            (3568) 0x50702c ADD	X0, X0, #1

            (3568) 0x507030 LDR	X17, [X25, X0,LSL #3]

            (3568) 0x507034 ORR	X30, XZR, X0

            (3568) 0x507038 CMP	X17, X1

            (3568) 0x50703c B.EQ	507128

            (3568) 0x507040 ADD	X0, X0, #1

            (3568) 0x507044 LDR	X16, [X25, X0,LSL #3]

            (3568) 0x507048 CMP	X16, X1

            (3568) 0x50704c B.EQ	507128

            (3568) 0x507050 ADD	X0, X30, #2

            (3568) 0x507054 LDR	X17, [X25, X0,LSL #3]

            (3568) 0x507058 CMP	X17, X1

            (3568) 0x50705c B.EQ	507128

            (3568) 0x507060 ADD	X0, X30, #3

            (3568) 0x507064 LDR	X16, [X25, X0,LSL #3]

            (3568) 0x507068 CMP	X16, X1

            (3568) 0x50706c B.EQ	507128

            (3568) 0x507070 ADD	X0, X30, #4

            (3568) 0x507074 LDR	X17, [X25, X0,LSL #3]

            (3568) 0x507078 CMP	X17, X1

            (3568) 0x50707c B.EQ	507128

            (3568) 0x507080 ADD	X0, X30, #5

            (3568) 0x507084 LDR	X16, [X25, X0,LSL #3]

            (3568) 0x507088 CMP	X16, X1

            (3568) 0x50708c B.EQ	507128

            (3568) 0x507090 ADD	X0, X30, #6

            (3568) 0x507094 LDR	X17, [X25, X0,LSL #3]

            (3568) 0x507098 CMP	X17, X1

            (3568) 0x50709c B.EQ	507128

            (3568) 0x5070a0 ADD	X0, X30, #7

            (3568) 0x5070a4 CMP	X2, X0

            (3568) 0x5070a8 B.NE	507020

        (3564) 0x5070ac LDR	D3, [X26, X21,LSL #3]

        (3564) 0x5070b0 CMP	X10, X15

        (3564) 0x5070b4 B.LE	507144

        (3564) 0x5070b8 UBFM	X16, X15, #61, #60

        (3564) 0x5070bc ADD	X15, X15, #1

        (3564) 0x5070c0 STR	X1, [X25, X16]

        (3564) 0x5070c4 STR	D3, [X6, X16]

        (3564) 0x5070c8 ADD	X21, X21, #1

        (3564) 0x5070cc CMP	X21, X12

        (3564) 0x5070d0 B.NE	506f60

      (3559) 0x5070d4 LDR	X1, [SP, #184]

      (3559) 0x5070d8 ADD	X21, X15, X14

      (3559) 0x5070dc STR	X21, [X1, X13]

      (3559) 0x5070e0 CBNZ	X14, 5071c4

      (3559) 0x5070e4 ORR	X21, XZR, X12

      (3559) 0x5070e8 CBZ	X3, 506be4

      (3559) 0x5070ec ORR	X0, XZR, X3

      (3559) 0x5070f0 STR	X12, [SP, #112]

      (3559) 0x5070f4 STP	X9, X5, [SP, #240]

      (3559) 0x5070f8 STP	X11, X7, [SP, #256]

      (3559) 0x5070fc STR	X8, [SP, #272]

      (3559) 0x507100 STP	X18, X4, [SP, #288]

      (3559) 0x507104 BL	52b3a0

      (3559) 0x507108 LDR	X0, [SP, #240]

      (3559) 0x50710c BL	52b3a0

      (3559) 0x507110 LDR	X21, [SP, #112]

      (3559) 0x507114 MOVZ	X9, #0

      (3559) 0x507118 LDP	X5, X11, [SP, #248]

      (3559) 0x50711c LDP	X7, X8, [SP, #264]

      (3559) 0x507120 LDP	X18, X4, [SP, #288]

      (3559) 0x507124 B	506be4

          (3567) 0x507128 LDR	D4, [X26, X21,LSL #3]

          (3567) 0x50712c ADD	X21, X21, #1

          (3567) 0x507130 STR	D4, [X6, X0,LSL #3]

          (3567) 0x507134 CMP	X21, X12

          (3567) 0x507138 B.EQ	5070d4

          (3567) 0x50713c LDR	X1, [X28, X21,LSL #3]

          (3567) 0x507140 B	506f6c

        (3564) 0x507144 UBFM	X30, X14, #61, #60

        (3564) 0x507148 ADD	X14, X14, #1

        (3564) 0x50714c STR	X1, [X3, X30]

        (3564) 0x507150 STR	D3, [X9, X30]

        (3564) 0x507154 B	5070c8

0x507158 MADD	X30, X0, X1, XZR

0x50715c UBFM	X19, X25, #61, #60

0x507160 STR	XZR, [X21, X19]

0x507164 ADD	X0, X1, X30

0x507168 ADD	X27, X30, X22

0x50716c ADD	X3, X0, X22

0x507170 ADD	X22, X21, X25,LSL #3

0x507174 STR	X3, [SP, #104]

0x507178 CMP	X27, X3

0x50717c B.LT	506538

0x507180 STP	X6, X7, [SP, #240]

0x507184 STP	X8, X5, [SP, #256]

0x507188 STR	X12, [SP, #272]

0x50718c BL	410d30

0x507190 LDR	X12, [SP, #272]

0x507194 LDP	X9, X7, [SP, #240]

0x507198 LDP	X8, X5, [SP, #256]

0x50719c CBNZ	X25, 5071a8

0x5071a0 CMP	X26, #0

0x5071a4 B.GT	506678

0x5071a8 LDP	X19, X20, [SP, #16]

0x5071ac LDP	X21, X22, [SP, #32]

0x5071b0 LDP	X23, X24, [SP, #48]

0x5071b4 LDP	X25, X26, [SP, #64]

0x5071b8 LDP	X27, X28, [SP, #80]

0x5071bc LDP	X29, X30, [SP], #336

0x5071c0 B	410d30

      (3559) 0x5071c4 LDR	X6, [SP, #208]

      (3559) 0x5071c8 UBFM	X25, X21, #61, #60

      (3559) 0x5071cc ORR	X1, XZR, X25

      (3559) 0x5071d0 STR	X13, [SP, #112]

      (3559) 0x5071d4 STR	X9, [SP, #272]

      (3559) 0x5071d8 LDR	X0, [X6, X13]

      (3559) 0x5071dc STP	X12, X15, [SP, #240]

      (3559) 0x5071e0 STP	X14, X3, [SP, #256]

      (3559) 0x5071e4 STP	X5, X11, [SP, #288]

      (3559) 0x5071e8 STP	X7, X8, [SP, #304]

      (3559) 0x5071ec STP	X18, X4, [SP, #320]

      (3559) 0x5071f0 BL	52b348

      (3559) 0x5071f4 LDR	X3, [SP, #112]

      (3559) 0x5071f8 ORR	X1, XZR, X25

      (3559) 0x5071fc ORR	X9, XZR, X0

      (3559) 0x507200 LDP	X10, X25, [SP, #200]

      (3559) 0x507204 LDR	X0, [X10, X3]

      (3559) 0x507208 STR	X9, [X25, X3]

      (3559) 0x50720c BL	52b348

      (3559) 0x507210 LDR	X2, [SP, #112]

      (3559) 0x507214 ORR	X30, XZR, X0

      (3559) 0x507218 LDP	X12, X15, [SP, #240]

      (3559) 0x50721c LDP	X14, X3, [SP, #256]

      (3559) 0x507220 UBFM	X10, X15, #61, #60

      (3559) 0x507224 LDP	X5, X11, [SP, #288]

      (3559) 0x507228 CMP	X14, #1

      (3559) 0x50722c LDP	X7, X8, [SP, #304]

      (3559) 0x507230 LDP	X18, X4, [SP, #320]

      (3559) 0x507234 LDR	X13, [SP, #200]

      (3559) 0x507238 LDR	X17, [X25, X2]

      (3559) 0x50723c LDR	X9, [SP, #272]

      (3559) 0x507240 STR	X0, [X13, X2]

      (3559) 0x507244 LDR	X0, [SP, #216]

      (3559) 0x507248 STR	X21, [X0, X2]

      (3559) 0x50724c B.EQ	507624

      (3559) 0x507250 ADD	X1, X30, X15,LSL #3

      (3559) 0x507254 ADD	X21, X10, #8

      (3559) 0x507258 ADD	X16, X9, #8

      (3559) 0x50725c ADD	X6, X17, X21

      (3559) 0x507260 ADD	X2, X17, X15,LSL #3

      (3559) 0x507264 ADD	X25, X3, #8

      (3559) 0x507268 CMP	X6, X1

      (3559) 0x50726c CCMP	X16, X1, #4, #1

      (3559) 0x507270 CCMP	X25, X2, #4, #1

      (3559) 0x507274 B.EQ	507624

      (3559) 0x507278 UBFM	X21, X14, #1, #63

      (3559) 0x50727c MOVZ	X0, #0

      (3559) 0x507280 UBFM	X6, X21, #60, #59

      (3559) 0x507284 SUB	X25, X6, #16

      (3559) 0x507288 UBFM	X16, X25, #4, #63

      (3559) 0x50728c ADD	X13, X16, #1

      (3559) 0x507290 ANDS	X21, X13, #4224

      (3559) 0x507294 B.EQ	507348

      (3559) 0x507298 CMP	X21, #1

      (3559) 0x50729c B.EQ	50732c

      (3559) 0x5072a0 CMP	X21, #2

      (3559) 0x5072a4 B.EQ	507318

      (3559) 0x5072a8 CMP	X21, #3

      (3559) 0x5072ac B.EQ	507304

      (3559) 0x5072b0 CMP	X21, #4

      (3559) 0x5072b4 B.EQ	5072f0

      (3559) 0x5072b8 CMP	X21, #5

      (3559) 0x5072bc B.EQ	5072dc

      (3559) 0x5072c0 CMP	X21, #6

      (3559) 0x5072c4 B.NE	5077a8

      (3559) 0x5072c8 LDR	Q7, [X3, X0]

      (3559) 0x5072cc LDR	Q6, [X9, X0]

      (3559) 0x5072d0 STR	Q7, [X2, X0]

      (3559) 0x5072d4 STR	Q6, [X1, X0]

      (3559) 0x5072d8 ADD	X0, X0, #16

      (3559) 0x5072dc LDR	Q17, [X3, X0]

      (3559) 0x5072e0 LDR	Q16, [X9, X0]

      (3559) 0x5072e4 STR	Q17, [X2, X0]

      (3559) 0x5072e8 STR	Q16, [X1, X0]

      (3559) 0x5072ec ADD	X0, X0, #16

      (3559) 0x5072f0 LDR	Q19, [X3, X0]

      (3559) 0x5072f4 LDR	Q18, [X9, X0]

      (3559) 0x5072f8 STR	Q19, [X2, X0]

      (3559) 0x5072fc STR	Q18, [X1, X0]

      (3559) 0x507300 ADD	X0, X0, #16

      (3559) 0x507304 LDR	Q21, [X3, X0]

      (3559) 0x507308 LDR	Q20, [X9, X0]

      (3559) 0x50730c STR	Q21, [X2, X0]

      (3559) 0x507310 STR	Q20, [X1, X0]

      (3559) 0x507314 ADD	X0, X0, #16

      (3559) 0x507318 LDR	Q23, [X3, X0]

      (3559) 0x50731c LDR	Q22, [X9, X0]

      (3559) 0x507320 STR	Q23, [X2, X0]

      (3559) 0x507324 STR	Q22, [X1, X0]

      (3559) 0x507328 ADD	X0, X0, #16

      (3559) 0x50732c LDR	Q25, [X3, X0]

      (3559) 0x507330 LDR	Q24, [X9, X0]

      (3559) 0x507334 STR	Q25, [X2, X0]

      (3559) 0x507338 STR	Q24, [X1, X0]

      (3559) 0x50733c ADD	X0, X0, #16

      (3559) 0x507340 CMP	X6, X0

      (3559) 0x507344 B.EQ	5073f4

      (3559) 0x507348 ORR	X25, XZR, X6

        (3566) 0x50734c LDR	Q27, [X3, X0]

        (3566) 0x507350 ADD	X6, X0, #16

        (3566) 0x507354 ADD	X21, X0, #32

        (3566) 0x507358 ADD	X16, X0, #48

        (3566) 0x50735c ADD	X13, X0, #64

        (3566) 0x507360 LDR	Q26, [X9, X0]

        (3566) 0x507364 ADD	X10, X0, #80

        (3566) 0x507368 STR	Q27, [X2, X0]

        (3566) 0x50736c LDR	Q28, [X3, X6]

        (3566) 0x507370 STR	Q26, [X1, X0]

        (3566) 0x507374 LDR	Q29, [X9, X6]

        (3566) 0x507378 STR	Q28, [X2, X6]

        (3566) 0x50737c LDR	Q0, [X3, X21]

        (3566) 0x507380 STR	Q29, [X1, X6]

        (3566) 0x507384 ADD	X6, X0, #96

        (3566) 0x507388 LDR	Q31, [X9, X21]

        (3566) 0x50738c STR	Q0, [X2, X21]

        (3566) 0x507390 LDR	Q1, [X3, X16]

        (3566) 0x507394 STR	Q31, [X1, X21]

        (3566) 0x507398 ADD	X21, X0, #112

        (3566) 0x50739c ADD	X0, X0, #128

        (3566) 0x5073a0 LDR	Q2, [X9, X16]

        (3566) 0x5073a4 STR	Q1, [X2, X16]

        (3566) 0x5073a8 LDR	Q3, [X3, X13]

        (3566) 0x5073ac STR	Q2, [X1, X16]

        (3566) 0x5073b0 LDR	Q4, [X9, X13]

        (3566) 0x5073b4 STR	Q3, [X2, X13]

        (3566) 0x5073b8 LDR	Q30, [X3, X10]

        (3566) 0x5073bc STR	Q4, [X1, X13]

        (3566) 0x5073c0 LDR	Q5, [X9, X10]

        (3566) 0x5073c4 STR	Q30, [X2, X10]

        (3566) 0x5073c8 LDR	Q6, [X3, X6]

        (3566) 0x5073cc STR	Q5, [X1, X10]

        (3566) 0x5073d0 LDR	Q7, [X9, X6]

        (3566) 0x5073d4 STR	Q6, [X2, X6]

        (3566) 0x5073d8 LDR	Q16, [X3, X21]

        (3566) 0x5073dc STR	Q7, [X1, X6]

        (3566) 0x5073e0 LDR	Q17, [X9, X21]

        (3566) 0x5073e4 STR	Q16, [X2, X21]

        (3566) 0x5073e8 STR	Q17, [X1, X21]

        (3566) 0x5073ec CMP	X25, X0

        (3566) 0x5073f0 B.NE	50734c

      (3559) 0x5073f4 AND	X2, X14, #8127

      (3559) 0x5073f8 ADD	X15, X2, X15

      (3559) 0x5073fc TBZ	W14, #0, 5070ec

      (3559) 0x507400 UBFM	X14, X2, #61, #60

      (3559) 0x507404 UBFM	X1, X15, #61, #60

      (3559) 0x507408 LDR	X0, [X3, X14]

      (3559) 0x50740c LDR	D18, [X9, X14]

      (3559) 0x507410 STR	X0, [X17, X1]

      (3559) 0x507414 STR	D18, [X30, X1]

      (3559) 0x507418 B	5070ec

      (3559) 0x50741c SUB	X9, X12, X3

      (3559) 0x507420 MOVZ	X1, #8

      (3559) 0x507424 STP	X12, X6, [SP, #240]

      (3559) 0x507428 ORR	X0, XZR, X9

      (3559) 0x50742c STR	X9, [SP, #112]

      (3559) 0x507430 STP	X10, X2, [SP, #256]

      (3559) 0x507434 STR	X13, [SP, #272]

      (3559) 0x507438 STP	X5, X11, [SP, #288]

      (3559) 0x50743c STP	X7, X8, [SP, #304]

      (3559) 0x507440 STP	X18, X4, [SP, #320]

      (3559) 0x507444 BL	52b308

      (3559) 0x507448 ORR	X7, XZR, X0

      (3559) 0x50744c LDR	X0, [SP, #112]

      (3559) 0x507450 MOVZ	X1, #8

      (3559) 0x507454 STR	X7, [SP, #112]

      (3559) 0x507458 BL	52b308

      (3559) 0x50745c LDP	X12, X6, [SP, #240]

      (3559) 0x507460 ORR	X9, XZR, X0

      (3559) 0x507464 LDP	X10, X2, [SP, #256]

      (3559) 0x507468 LDP	X5, X11, [SP, #288]

      (3559) 0x50746c LDP	X7, X8, [SP, #304]

      (3559) 0x507470 LDP	X18, X4, [SP, #320]

      (3559) 0x507474 LDR	X3, [SP, #112]

      (3559) 0x507478 LDR	X13, [SP, #272]

      (3559) 0x50747c CMP	X12, #0

      (3559) 0x507480 B.GT	506f50

      (3559) 0x507484 ORR	X12, XZR, X21

      (3559) 0x507488 LDR	X21, [SP, #184]

      (3559) 0x50748c STR	X2, [X21, X13]

      (3559) 0x507490 B	5070e4

0x507494 STP	X9, X7, [SP, #240]

0x507498 STP	X8, X5, [SP, #256]

0x50749c STR	X12, [SP, #272]

0x5074a0 BL	410d30

0x5074a4 LDUR	X21, [X22, #504]

0x5074a8 LDP	X11, X7, [SP, #240]

0x5074ac LDP	X8, X5, [SP, #256]

0x5074b0 LDR	X12, [SP, #272]

0x5074b4 B	5067a8

    (3569) 0x5074b8 ADRP	X30,

    (3569) 0x5074bc MOVZ	X3, #0

    (3569) 0x5074c0 LDR	X25, [SP, #240]

    (3569) 0x5074c4 ADD	X0, X30, #936

    (3569) 0x5074c8 MOVZ	X2, #1

    (3569) 0x5074cc STR	X13, [SP, #112]

    (3569) 0x5074d0 MOVZ	X1, #3406

    (3569) 0x5074d4 STP	X4, X18, [SP, #240]

    (3569) 0x5074d8 STP	X8, X7, [SP, #256]

    (3569) 0x5074dc STR	X11, [SP, #272]

    (3569) 0x5074e0 STP	X5, X14, [SP, #288]

    (3569) 0x5074e4 STP	X15, X9, [SP, #304]

    (3569) 0x5074e8 BL	52ede0

    (3569) 0x5074ec LDR	X5, [SP, #224]

    (3569) 0x5074f0 MOVZ	X18, #1

    (3569) 0x5074f4 LDR	X4, [X5, #224]

    (3569) 0x5074f8 LDADD	X18, X1, [X4]

    (3569) 0x5074fc LDP	X11, X10, [SP, #272]

    (3569) 0x507500 LDP	X4, X18, [SP, #240]

    (3569) 0x507504 LDP	X8, X7, [SP, #256]

    (3569) 0x507508 LDP	X5, X14, [SP, #288]

    (3569) 0x50750c LDP	X15, X9, [SP, #304]

    (3569) 0x507510 LDR	X13, [SP, #112]

    (3569) 0x507514 CBNZ	X10, 507540

    (3571) 0x507518 ORR	X16, XZR, X21

    (3571) 0x50751c LDR	X21, [SP, #144]

    (3571) 0x507520 ADD	X17, X21, #56

    (3571) 0x507524 LDP	X2, X1, [X17]

    (3571) 0x507528 ADD	X0, X2, X13

    (3571) 0x50752c ADD	X1, X1, X13

    (3571) 0x507530 B	506a24

0x507534 LDR	X0, [X1], #8

0x507538 STR	X0, [X22]

0x50753c B	506590

    (3569) 0x507540 ADRP	X16,

    (3569) 0x507544 ORR	X1, XZR, X25

    (3569) 0x507548 STR	X15, [SP, #112]

    (3569) 0x50754c ADD	X0, X16, #1096

    (3569) 0x507550 STP	X14, X13, [SP, #240]

    (3569) 0x507554 STP	X9, X5, [SP, #256]

    (3569) 0x507558 STR	X11, [SP, #272]

    (3569) 0x50755c STP	X7, X8, [SP, #288]

    (3569) 0x507560 STP	X18, X4, [SP, #304]

    (3569) 0x507564 BL	52b540

    (3569) 0x507568 LDR	X12, [SP, #144]

    (3569) 0x50756c ORR	X16, XZR, X21

    (3569) 0x507570 LDP	X14, X13, [SP, #240]

    (3569) 0x507574 LDP	X9, X5, [SP, #256]

    (3569) 0x507578 ADD	X6, X12, #56

    (3569) 0x50757c LDP	X0, X3, [X6]

    (3569) 0x507580 LDP	X7, X8, [SP, #288]

    (3569) 0x507584 ADD	X0, X0, X13

    (3569) 0x507588 ADD	X1, X3, X13

    (3569) 0x50758c LDP	X18, X4, [SP, #304]

    (3569) 0x507590 LDR	X15, [SP, #112]

    (3569) 0x507594 LDR	X11, [SP, #272]

    (3569) 0x507598 B	506a24

  (3570) 0x50759c ADRP	X12,

  (3570) 0x5075a0 MOVZ	X3, #0

  (3570) 0x5075a4 LDR	X25, [SP, #240]

  (3570) 0x5075a8 ADD	X0, X12, #936

  (3570) 0x5075ac MOVZ	X2, #1

  (3570) 0x5075b0 STR	X13, [SP, #112]

  (3570) 0x5075b4 MOVZ	X1, #3440

  (3570) 0x5075b8 STP	X4, X18, [SP, #240]

  (3570) 0x5075bc STP	X8, X7, [SP, #256]

  (3570) 0x5075c0 STR	X11, [SP, #272]

  (3570) 0x5075c4 STP	X5, X14, [SP, #288]

  (3570) 0x5075c8 STP	X15, X9, [SP, #304]

  (3570) 0x5075cc BL	52ede0

  (3570) 0x5075d0 LDR	X8, [SP, #224]

  (3570) 0x5075d4 MOVZ	X7, #1

  (3570) 0x5075d8 LDR	X11, [X8, #224]

  (3570) 0x5075dc LDADD	X7, X1, [X11]

  (3570) 0x5075e0 LDP	X11, X6, [SP, #272]

  (3570) 0x5075e4 LDP	X4, X18, [SP, #240]

  (3570) 0x5075e8 LDP	X8, X7, [SP, #256]

  (3570) 0x5075ec LDP	X5, X14, [SP, #288]

  (3570) 0x5075f0 LDP	X15, X9, [SP, #304]

  (3570) 0x5075f4 LDR	X13, [SP, #112]

  (3570) 0x5075f8 CBZ	X6, 507518

  (3570) 0x5075fc ADRP	X3,

  (3570) 0x507600 ORR	X1, XZR, X25

  (3570) 0x507604 STR	X15, [SP, #112]

  (3570) 0x507608 ADD	X0, X3, #1136

  (3570) 0x50760c STP	X14, X13, [SP, #240]

  (3570) 0x507610 STP	X9, X5, [SP, #256]

  (3570) 0x507614 STR	X11, [SP, #272]

  (3570) 0x507618 STP	X7, X8, [SP, #288]

  (3570) 0x50761c STP	X18, X4, [SP, #304]

  (3570) 0x507620 B	507564

      (3559) 0x507624 ANDS	X16, X14, #4224

      (3559) 0x507628 ADD	X21, X17, X10

      (3559) 0x50762c MOVZ	X0, #0

      (3559) 0x507630 ADD	X25, X30, X10

      (3559) 0x507634 B.EQ	5076fc

      (3559) 0x507638 CMP	X16, #1

      (3559) 0x50763c B.EQ	5076e0

      (3559) 0x507640 CMP	X16, #2

      (3559) 0x507644 B.EQ	5076cc

      (3559) 0x507648 CMP	X16, #3

      (3559) 0x50764c B.EQ	5076b8

      (3559) 0x507650 CMP	X16, #4

      (3559) 0x507654 B.EQ	5076a4

      (3559) 0x507658 CMP	X16, #5

      (3559) 0x50765c B.EQ	507690

      (3559) 0x507660 CMP	X16, #6

      (3559) 0x507664 B.EQ	50767c

      (3559) 0x507668 LDR	D19, [X9]

      (3559) 0x50766c MOVZ	X0, #1

      (3559) 0x507670 LDR	X13, [X3]

      (3559) 0x507674 STR	X13, [X17, X10]

      (3559) 0x507678 STR	D19, [X30, X10]

      (3559) 0x50767c LDR	D20, [X9, X0,LSL #3]

      (3559) 0x507680 LDR	X30, [X3, X0,LSL #3]

      (3559) 0x507684 STR	X30, [X21, X0,LSL #3]

      (3559) 0x507688 STR	D20, [X25, X0,LSL #3]

      (3559) 0x50768c ADD	X0, X0, #1

      (3559) 0x507690 LDR	D21, [X9, X0,LSL #3]

      (3559) 0x507694 LDR	X17, [X3, X0,LSL #3]

      (3559) 0x507698 STR	X17, [X21, X0,LSL #3]

      (3559) 0x50769c STR	D21, [X25, X0,LSL #3]

      (3559) 0x5076a0 ADD	X0, X0, #1

      (3559) 0x5076a4 LDR	D22, [X9, X0,LSL #3]

      (3559) 0x5076a8 LDR	X10, [X3, X0,LSL #3]

      (3559) 0x5076ac STR	X10, [X21, X0,LSL #3]

      (3559) 0x5076b0 STR	D22, [X25, X0,LSL #3]

      (3559) 0x5076b4 ADD	X0, X0, #1

      (3559) 0x5076b8 LDR	D23, [X9, X0,LSL #3]

      (3559) 0x5076bc LDR	X6, [X3, X0,LSL #3]

      (3559) 0x5076c0 STR	X6, [X21, X0,LSL #3]

      (3559) 0x5076c4 STR	D23, [X25, X0,LSL #3]

      (3559) 0x5076c8 ADD	X0, X0, #1

      (3559) 0x5076cc LDR	D24, [X9, X0,LSL #3]

      (3559) 0x5076d0 LDR	X2, [X3, X0,LSL #3]

      (3559) 0x5076d4 STR	X2, [X21, X0,LSL #3]

      (3559) 0x5076d8 STR	D24, [X25, X0,LSL #3]

      (3559) 0x5076dc ADD	X0, X0, #1

      (3559) 0x5076e0 LDR	D25, [X9, X0,LSL #3]

      (3559) 0x5076e4 LDR	X15, [X3, X0,LSL #3]

      (3559) 0x5076e8 STR	X15, [X21, X0,LSL #3]

      (3559) 0x5076ec STR	D25, [X25, X0,LSL #3]

      (3559) 0x5076f0 ADD	X0, X0, #1

      (3559) 0x5076f4 CMP	X0, X14

      (3559) 0x5076f8 B.EQ	5070ec

        (3565) 0x5076fc LDR	X16, [X3, X0,LSL #3]

        (3565) 0x507700 ADD	X1, X0, #1

        (3565) 0x507704 ADD	X30, X0, #2

        (3565) 0x507708 ADD	X13, X0, #3

        (3565) 0x50770c ADD	X17, X0, #4

        (3565) 0x507710 LDR	D26, [X9, X0,LSL #3]

        (3565) 0x507714 ADD	X2, X0, #6

        (3565) 0x507718 STR	X16, [X21, X0,LSL #3]

        (3565) 0x50771c ADD	X16, X0, #5

        (3565) 0x507720 LDR	X10, [X3, X1,LSL #3]

        (3565) 0x507724 STR	D26, [X25, X0,LSL #3]

        (3565) 0x507728 LDR	D27, [X9, X1,LSL #3]

        (3565) 0x50772c STR	X10, [X21, X1,LSL #3]

        (3565) 0x507730 LDR	X6, [X3, X30,LSL #3]

        (3565) 0x507734 STR	D27, [X25, X1,LSL #3]

        (3565) 0x507738 ADD	X1, X0, #7

        (3565) 0x50773c ADD	X0, X0, #8

        (3565) 0x507740 LDR	D28, [X9, X30,LSL #3]

        (3565) 0x507744 STR	X6, [X21, X30,LSL #3]

        (3565) 0x507748 LDR	X15, [X3, X13,LSL #3]

        (3565) 0x50774c STR	D28, [X25, X30,LSL #3]

        (3565) 0x507750 LDR	D29, [X9, X13,LSL #3]

        (3565) 0x507754 STR	X15, [X21, X13,LSL #3]

        (3565) 0x507758 LDR	X30, [X3, X17,LSL #3]

        (3565) 0x50775c STR	D29, [X25, X13,LSL #3]

        (3565) 0x507760 LDR	D0, [X9, X17,LSL #3]

        (3565) 0x507764 STR	X30, [X21, X17,LSL #3]

        (3565) 0x507768 LDR	X13, [X3, X16,LSL #3]

        (3565) 0x50776c STR	D0, [X25, X17,LSL #3]

        (3565) 0x507770 LDR	D31, [X9, X16,LSL #3]

        (3565) 0x507774 STR	X13, [X21, X16,LSL #3]

        (3565) 0x507778 LDR	X17, [X3, X2,LSL #3]

        (3565) 0x50777c STR	D31, [X25, X16,LSL #3]

        (3565) 0x507780 LDR	D1, [X9, X2,LSL #3]

        (3565) 0x507784 STR	X17, [X21, X2,LSL #3]

        (3565) 0x507788 LDR	X10, [X3, X1,LSL #3]

        (3565) 0x50778c STR	D1, [X25, X2,LSL #3]

        (3565) 0x507790 LDR	D2, [X9, X1,LSL #3]

        (3565) 0x507794 STR	X10, [X21, X1,LSL #3]

        (3565) 0x507798 STR	D2, [X25, X1,LSL #3]

        (3565) 0x50779c CMP	X0, X14

        (3565) 0x5077a0 B.NE	5076fc

      (3559) 0x5077a4 B	5070ec

      (3559) 0x5077a8 LDR	Q30, [X3]

      (3559) 0x5077ac MOVZ	X0, #16

      (3559) 0x5077b0 LDR	Q5, [X9]

      (3559) 0x5077b4 STR	Q30, [X17, X10]

      (3559) 0x5077b8 STR	Q5, [X30, X10]

      (3559) 0x5077bc B	5072c8

    (3569) 0x5077c0 ORR	X16, XZR, X21

    (3569) 0x5077c4 B	506a24

Coverage (%)	Name	Source Location	Module
►99.05+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3322,3329-3353,3359-3368,3376-3412,3422-3446,3454-3458,3466-3484,3500.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 63% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 38.67 to 28.50 cycles (1.36x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 38.67 to 3.00 cycles (12.89x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 704 bytes. The binary function is storing 592 bytes.

General properties

nb instructions	227
loop length	908
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	16.50	16.50	16.17	16.17	16.17	16.17	16.17	16.17	0.00	0.00	0.00	0.00	38.67	38.67	38.67	29.00	29.00
cycles	16.50	16.50	16.17	16.17	16.17	16.17	16.17	16.17	0.00	0.00	0.00	0.00	38.67	38.67	38.67	29.00	29.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	28.00
Overall L1	38.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 38.67 cycles. At this rate:

18% of peak load performance is reached (18.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 506440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #688]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X22, X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X1, X28, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X2, [X12, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X8, [X12, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X7, X4, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X6, X9, [X12, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X12, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X13, X24, [X12, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X13, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X14, X15, [X12, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X14, X15, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X23, X16, [X12, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X16, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X17, X18, [X12, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X17, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X20, [X12, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X19, X20, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X25, X26, [X12, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X20, [X12, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X1, X22, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X6, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB X22, X1, X27, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X0, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 507158 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X27, X1, X0, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X2, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X19, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X21, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X21, X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X3, X2, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X27, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 507180 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X4, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X4, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X10, X9, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X13, X11, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X15, X14, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065e0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065c0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065b4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 50659c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 507534 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x10f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X17, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X1, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 506650 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X6, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CBNZ X25, 507494 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1054>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 506788 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X21, X26, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X25, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X6, X25, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X22, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X13, X22, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X26, X1, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B.EQ 506728 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 506714 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 506708 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5066fc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5066f0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5066e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5066d8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X16, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X17, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X1, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 506788 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X9, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X21, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X27, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 506a40 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVN X22, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X4, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X6, X4, #1, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X25, X10, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X15, X14, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X4, X15, X6,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X25, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
MADD X30, X0, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X19, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X21, X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X0, X1, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X30, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X0, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X22, X21, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X27, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 506538 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X6, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CBNZ X25, 5071a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 506678 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #336	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 410d30 <@plt_start@+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X9, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X21, [X22, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 5067a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 506590 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 38.67 to 3.00 cycles (12.89x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 704 bytes. The binary function is storing 592 bytes.

General properties

nb instructions	227
loop length	908
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	16.50	16.50	16.17	16.17	16.17	16.17	16.17	16.17	0.00	0.00	0.00	0.00	38.67	38.67	38.67	29.00	29.00
cycles	16.50	16.50	16.17	16.17	16.17	16.17	16.17	16.17	0.00	0.00	0.00	0.00	38.67	38.67	38.67	29.00	29.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	28.00
Overall L1	38.67

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 38.67 cycles. At this rate:

18% of peak load performance is reached (18.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 506440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #688]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X12, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X22, X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X1, X28, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X2, [X12, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X8, [X12, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X7, X4, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X7, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X6, X9, [X12, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X12, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X13, X24, [X12, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X13, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X14, X15, [X12, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X14, X15, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X23, X16, [X12, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X16, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X17, X18, [X12, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X17, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X20, [X12, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X19, X20, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X25, X26, [X12, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X20, [X12, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X1, X22, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X6, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB X22, X1, X27, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X0, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 507158 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD X27, X1, X0, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X2, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X19, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X22, X21, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X21, X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X3, X2, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X27, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 507180 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X4, X27,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X4, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X10, X9, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X13, X11, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X15, X14, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065e0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065c0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065b4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5065a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 50659c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X15, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 507534 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x10f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X17, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X1, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 506650 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X6, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CBNZ X25, 507494 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1054>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 506788 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X1, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X21, X26, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X25, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X6, X25, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X22, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X13, X22, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X26, X1, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B.EQ 506728 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 506714 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 506708 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5066fc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5066f0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5066e4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X13, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 5066d8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X15, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X16, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X17, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X0, X0, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X1, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 506788 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X9, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X21, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X27, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 506a40 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVN X22, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X4, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X6, X4, #1, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X25, X10, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X15, X14, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X18, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X4, X15, X6,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X25, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
MADD X30, X0, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X19, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X21, X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X0, X1, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X27, X30, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X0, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X22, X21, X25,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X27, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 506538 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X6, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CBNZ X25, 5071a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xd68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 506678 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #336	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 410d30 <@plt_start@+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X9, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410d30 <@plt_start@+0x570>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X21, [X22, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X8, X5, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X12, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 5067a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X1], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 506590 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1–	0.26	0.04
○Loop 3558 - IJMatrix_parcsr.c:3274-3275 - exec	0.01	0.00
▼Loop 3574 - IJMatrix_parcsr.c:3240-3500 - exec–	0.00	0.00
▼Loop 3570 - IJMatrix_parcsr.c:3240-3500 - exec–	0.17	0.02
▼Loop 3569 - IJMatrix_parcsr.c:3240-3500 - exec–	0.02	0.01
▼Loop 3572 - IJMatrix_parcsr.c:3383-3484 - exec–	0.06	0.01
○Loop 3573 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
▼Loop 3559 - IJMatrix_parcsr.c:3240-3500 - exec–	0.01	0.01
○Loop 3566 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
▼Loop 3564 - IJMatrix_parcsr.c:3316-3341 - exec–	0.00	0.00
▼Loop 3567 - IJMatrix_parcsr.c:3316-3341 - exec–	0.00	0.00
○Loop 3568 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00
▼Loop 3560 - IJMatrix_parcsr.c:3240-3500 - exec–	0.00	0.00
▼Loop 3561 - IJMatrix_parcsr.c:3470-3500 - exec–	0.00	0.00
▼Loop 3563 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 3562 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 3565 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3575 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 3571 - IJMatrix_parcsr.c:3457-3458 - exec	0.00	0.00
○Loop 3576 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code