OV - exec - Function hypre_ParMatmul._omp

	Function: hypre_ParMatmul._omp_fn.3	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 1.14% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

830: #endif

831:    {

832:     HYPRE_Int *B_marker = NULL;

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x4e78a0 STP	X29, X30, [SP, #704]!

0x4e78a4 ADD	X29, SP, #0

0x4e78a8 ORR	X2, XZR, X0

0x4e78ac STP	X19, X20, [SP, #16]

0x4e78b0 STP	X21, X22, [SP, #32]

0x4e78b4 STP	X23, X24, [SP, #48]

0x4e78b8 STP	X25, X26, [SP, #64]

0x4e78bc STP	X27, X28, [SP, #80]

0x4e78c0 STR	D15, [SP, #96]

0x4e78c4 LDP	X0, X1, [X0]

0x4e78c8 STR	X1, [SP, #120]

0x4e78cc STR	X0, [SP, #192]

0x4e78d0 LDP	X15, X3, [X2, #16]

0x4e78d4 STR	X15, [SP, #224]

0x4e78d8 STR	X3, [SP, #288]

0x4e78dc LDP	X4, X5, [X2, #32]

0x4e78e0 STR	X4, [SP, #112]

0x4e78e4 STR	X5, [SP, #280]

0x4e78e8 LDP	X25, X14, [X2, #48]

0x4e78ec STR	X14, [SP, #216]

0x4e78f0 LDP	X21, X7, [X2, #80]

0x4e78f4 LDP	X22, X27, [X2, #64]

0x4e78f8 STR	X7, [SP, #208]

0x4e78fc LDP	X8, X6, [X2, #96]

0x4e7900 STR	X6, [SP, #200]

0x4e7904 STR	X8, [SP, #184]

0x4e7908 LDP	X26, X9, [X2, #112]

0x4e790c LDR	X10, [X2, #176]

0x4e7910 STR	X9, [SP, #176]

0x4e7914 LDP	X11, X19, [X2, #128]

0x4e7918 LDR	D15, [X2, #248]

0x4e791c STR	X11, [SP, #168]

0x4e7920 LDP	X24, X23, [X2, #152]

0x4e7924 STR	X10, [SP, #160]

0x4e7928 LDP	X12, X13, [X2, #192]

0x4e792c STR	X12, [SP, #144]

0x4e7930 STR	X13, [SP, #272]

0x4e7934 LDP	X28, X18, [X2, #208]

0x4e7938 STR	X18, [SP, #136]

0x4e793c LDP	X16, X17, [X2, #224]

0x4e7940 STR	X2, [SP, #128]

0x4e7944 STP	X17, X16, [SP, #256]

0x4e7948 LDR	X20, [X2, #240]

0x4e794c STR	X20, [SP, #152]

0x4e7950 BL	52df60

0x4e7954 ORR	X20, XZR, X0

0x4e7958 BL	52df40

0x4e795c ORR	X2, XZR, X0

0x4e7960 SDIV	X0, X25, X0

0x4e7964 LDR	X3, [SP, #144]

0x4e7968 LDP	X12, X18, [SP, #128]

0x4e796c LDP	X4, X5, [SP, #160]

0x4e7970 LDP	X6, X7, [SP, #200]

0x4e7974 MSUB	X25, X0, X2, X25

0x4e7978 LDP	X14, X15, [SP, #216]

0x4e797c MADD	X1, X20, X0, XZR

0x4e7980 CMP	X20, X25

0x4e7984 ADD	X9, X0, X1

0x4e7988 B.GE	4e7dc4

0x4e798c ADD	X30, X20, X9

0x4e7990 ADD	X8, X20, X1

0x4e7994 ADD	X13, X30, #1

0x4e7998 LDR	X11, [X12, #184]

0x4e799c UBFM	X9, X8, #61, #60

0x4e79a0 LDR	X10, [X12, #144]

0x4e79a4 LDR	X16, [X12, #168]

0x4e79a8 LDR	X17, [X11]

0x4e79ac LDR	X20, [X10]

0x4e79b0 LDR	X2, [X16]

0x4e79b4 ORR	X0, X26, X17

0x4e79b8 LDR	X20, [X20, X9]

0x4e79bc LDR	X25, [X2, X9]

0x4e79c0 CBNZ	X0, 4e7d48

0x4e79c4 MOVZ	X0, #0

0x4e79c8 LDR	X1, [SP, #112]

0x4e79cc LDR	X17, [SP, #120]

0x4e79d0 ADD	X12, X1, X9

0x4e79d4 ADD	X10, X17, X9

0x4e79d8 CMP	X8, X13

0x4e79dc B.GE	4e7d28

0x4e79e0 STR	X4, [SP, #112]

0x4e79e4 ORR	X16, XZR, X15

0x4e79e8 STP	X23, X12, [SP, #136]

0x4e79ec LDR	X23, [SP, #152]

0x4e79f0 STP	X13, X14, [SP, #160]

0x4e79f4 STR	X5, [SP, #200]

0x4e79f8 STP	X18, X28, [SP, #296]

0x4e79fc STR	X3, [SP, #312]

0x4e7a00 CBNZ	X23, 4e7ad4

  (3097) 0x4e7a04 LDR	X18, [SP, #168]

  (3097) 0x4e7a08 ORR	X2, XZR, X20

  (3097) 0x4e7a0c ORR	X9, XZR, X25

  (3097) 0x4e7a10 CBNZ	X18, 4e7af4

  (3097) 0x4e7a14 LDP	X12, X4, [X10]

  (3097) 0x4e7a18 CMP	X12, X4

  (3097) 0x4e7a1c B.GE	4e7aa4

  (3097) 0x4e7a20 LDP	X17, X18, [SP, #176]

  (3097) 0x4e7a24 LDP	X13, X11, [SP, #192]

  (3097) 0x4e7a28 STR	X8, [SP, #120]

    (3102) 0x4e7a2c LDR	X23, [X16, X12,LSL #3]

    (3102) 0x4e7a30 LDR	D28, [X13, X12,LSL #3]

    (3102) 0x4e7a34 UBFM	X5, X23, #61, #60

    (3102) 0x4e7a38 ADD	X8, X5, #8

    (3102) 0x4e7a3c LDR	X1, [X27, X5]

    (3102) 0x4e7a40 ADD	X15, X27, X8

    (3102) 0x4e7a44 LDR	X14, [X27, X8]

    (3102) 0x4e7a48 CMP	X1, X14

    (3102) 0x4e7a4c B.GE	4e7a8c

      (3104) 0x4e7a50 LDR	X4, [X21, X1,LSL #3]

      (3104) 0x4e7a54 UBFM	X28, X2, #61, #60

      (3104) 0x4e7a58 LDR	D6, [X22, X1,LSL #3]

      (3104) 0x4e7a5c UBFM	X23, X4, #61, #60

      (3104) 0x4e7a60 LDR	X3, [X0, X23]

      (3104) 0x4e7a64 FMUL	D7, D28, D6

      (3104) 0x4e7a68 UBFM	X30, X3, #61, #60

      (3104) 0x4e7a6c CMP	X20, X3

      (3104) 0x4e7a70 B.GT	4e7c24

      (3104) 0x4e7a74 LDR	D16, [X19, X30]

      (3104) 0x4e7a78 ADD	X1, X1, #1

      (3104) 0x4e7a7c FADD	D17, D16, D7

      (3104) 0x4e7a80 STR	D17, [X19, X30]

      (3104) 0x4e7a84 CMP	X1, X14

      (3104) 0x4e7a88 B.LT	4e7a50

    (3102) 0x4e7a8c CBNZ	X17, 4e7c48

    (3102) 0x4e7a90 LDR	X4, [X10, #8]

    (3102) 0x4e7a94 ADD	X12, X12, #1

    (3102) 0x4e7a98 CMP	X4, X12

    (3102) 0x4e7a9c B.GT	4e7a2c

  (3097) 0x4e7aa0 LDR	X8, [SP, #120]

  (3097) 0x4e7aa4 ADD	X8, X8, #1

  (3097) 0x4e7aa8 ADD	X10, X10, #8

  (3097) 0x4e7aac LDR	X20, [SP, #144]

  (3097) 0x4e7ab0 LDR	X17, [SP, #160]

  (3097) 0x4e7ab4 ADD	X25, X20, #8

  (3097) 0x4e7ab8 STR	X25, [SP, #144]

  (3097) 0x4e7abc CMP	X17, X8

  (3097) 0x4e7ac0 B.EQ	4e7d28

  (3097) 0x4e7ac4 LDR	X23, [SP, #152]

  (3097) 0x4e7ac8 ORR	X25, XZR, X9

  (3097) 0x4e7acc ORR	X20, XZR, X2

  (3097) 0x4e7ad0 CBZ	X23, 4e7a04

(3101) 0x4e7ad4 UBFM	X28, X20, #61, #60

(3101) 0x4e7ad8 STR	X20, [X0, X8,LSL #3]

(3101) 0x4e7adc ADD	X2, X20, #1

(3101) 0x4e7ae0 LDR	X18, [SP, #168]

(3101) 0x4e7ae4 ORR	X9, XZR, X25

(3101) 0x4e7ae8 STR	D15, [X19, X28]

(3101) 0x4e7aec STR	X8, [X24, X28]

(3101) 0x4e7af0 CBZ	X18, 4e7a14

  (3097) 0x4e7af4 LDR	X5, [SP, #144]

  (3097) 0x4e7af8 LDP	X13, X3, [X5]

  (3097) 0x4e7afc CMP	X13, X3

  (3097) 0x4e7b00 B.GE	4e7a14

  (3097) 0x4e7b04 LDR	X4, [SP, #112]

  (3097) 0x4e7b08 LDP	X14, X15, [SP, #272]

  (3097) 0x4e7b0c LDP	X18, X28, [SP, #296]

  (3097) 0x4e7b10 STP	X22, X16, [SP, #240]

  (3097) 0x4e7b14 ORR	X22, XZR, X10

  (3097) 0x4e7b18 LDR	X23, [SP, #136]

  (3097) 0x4e7b1c STP	X21, X27, [SP, #224]

  (3097) 0x4e7b20 ORR	X21, XZR, X5

  (3097) 0x4e7b24 ORR	X27, XZR, X8

  (3097) 0x4e7b28 LDR	X17, [SP, #256]

  (3097) 0x4e7b2c STP	X6, X7, [SP, #208]

  (3097) 0x4e7b30 LDR	X10, [SP, #264]

  (3097) 0x4e7b34 LDR	X16, [SP, #288]

  (3097) 0x4e7b38 LDR	X3, [SP, #312]

  (3097) 0x4e7b3c HINT	#0

    (3098) 0x4e7b40 LDR	X6, [X15, X13,LSL #3]

    (3098) 0x4e7b44 LDR	D31, [X16, X13,LSL #3]

    (3098) 0x4e7b48 UBFM	X7, X6, #61, #60

    (3098) 0x4e7b4c ADD	X8, X7, #8

    (3098) 0x4e7b50 LDR	X1, [X10, X7]

    (3098) 0x4e7b54 ADD	X12, X10, X8

    (3098) 0x4e7b58 LDR	X11, [X10, X8]

    (3098) 0x4e7b5c CMP	X1, X11

    (3098) 0x4e7b60 B.GE	4e7bac

    (3098) 0x4e7b64 STP	X10, X28, [SP, #120]

      (3100) 0x4e7b68 UBFM	X28, X9, #61, #60

      (3100) 0x4e7b6c LDR	X10, [X17, X1,LSL #3]

      (3100) 0x4e7b70 LDR	D1, [X18, X1,LSL #3]

      (3100) 0x4e7b74 ADD	X30, X26, X10

      (3100) 0x4e7b78 UBFM	X5, X30, #61, #60

      (3100) 0x4e7b7c LDR	X6, [X0, X5]

      (3100) 0x4e7b80 FMUL	D2, D31, D1

      (3100) 0x4e7b84 UBFM	X30, X6, #61, #60

      (3100) 0x4e7b88 CMP	X25, X6

      (3100) 0x4e7b8c B.GT	4e7d04

      (3100) 0x4e7b90 LDR	D0, [X23, X30]

      (3100) 0x4e7b94 ADD	X1, X1, #1

      (3100) 0x4e7b98 FADD	D3, D0, D2

      (3100) 0x4e7b9c STR	D3, [X23, X30]

      (3100) 0x4e7ba0 CMP	X1, X11

      (3100) 0x4e7ba4 B.LT	4e7b68

    (3098) 0x4e7ba8 LDP	X10, X28, [SP, #120]

    (3098) 0x4e7bac ADD	X12, X14, X8

    (3098) 0x4e7bb0 LDR	X1, [X14, X7]

    (3098) 0x4e7bb4 LDR	X30, [X14, X8]

    (3098) 0x4e7bb8 CMP	X1, X30

    (3098) 0x4e7bbc B.GE	4e7bfc

      (3099) 0x4e7bc0 LDR	X6, [X28, X1,LSL #3]

      (3099) 0x4e7bc4 UBFM	X8, X2, #61, #60

      (3099) 0x4e7bc8 LDR	D30, [X3, X1,LSL #3]

      (3099) 0x4e7bcc UBFM	X7, X6, #61, #60

      (3099) 0x4e7bd0 LDR	X5, [X0, X7]

      (3099) 0x4e7bd4 FMUL	D4, D31, D30

      (3099) 0x4e7bd8 UBFM	X11, X5, #61, #60

      (3099) 0x4e7bdc CMP	X20, X5

      (3099) 0x4e7be0 B.GT	4e7cd0

      (3099) 0x4e7be4 LDR	D29, [X19, X11]

      (3099) 0x4e7be8 ADD	X1, X1, #1

      (3099) 0x4e7bec FADD	D5, D29, D4

      (3099) 0x4e7bf0 STR	D5, [X19, X11]

      (3099) 0x4e7bf4 CMP	X1, X30

      (3099) 0x4e7bf8 B.LT	4e7bc0

    (3098) 0x4e7bfc LDR	X12, [X21, #8]

    (3098) 0x4e7c00 ADD	X13, X13, #1

    (3098) 0x4e7c04 CMP	X12, X13

    (3098) 0x4e7c08 B.GT	4e7b40

  (3097) 0x4e7c0c ORR	X8, XZR, X27

  (3097) 0x4e7c10 ORR	X10, XZR, X22

  (3097) 0x4e7c14 LDP	X6, X7, [SP, #208]

  (3097) 0x4e7c18 LDP	X21, X27, [SP, #224]

  (3097) 0x4e7c1c LDP	X22, X16, [SP, #240]

  (3097) 0x4e7c20 B	4e7a14

      (3104) 0x4e7c24 STR	X2, [X0, X23]

      (3104) 0x4e7c28 ADD	X1, X1, #1

      (3104) 0x4e7c2c ADD	X2, X2, #1

      (3104) 0x4e7c30 STR	D7, [X19, X28]

      (3104) 0x4e7c34 STR	X4, [X24, X28]

      (3104) 0x4e7c38 LDR	X14, [X15]

      (3104) 0x4e7c3c CMP	X14, X1

      (3104) 0x4e7c40 B.GT	4e7a50

    (3102) 0x4e7c44 CBZ	X17, 4e7a90

    (3102) 0x4e7c48 LDR	X1, [X18, X5]

    (3102) 0x4e7c4c ADD	X4, X18, X8

    (3102) 0x4e7c50 LDR	X30, [X18, X8]

    (3102) 0x4e7c54 CMP	X1, X30

    (3102) 0x4e7c58 B.GE	4e7a90

    (3102) 0x4e7c5c LDR	X28, [SP, #136]

      (3103) 0x4e7c60 UBFM	X23, X9, #61, #60

      (3103) 0x4e7c64 LDR	X5, [X6, X1,LSL #3]

      (3103) 0x4e7c68 LDR	D27, [X7, X1,LSL #3]

      (3103) 0x4e7c6c LDR	X8, [X11, X5,LSL #3]

      (3103) 0x4e7c70 FMUL	D18, D28, D27

      (3103) 0x4e7c74 ADD	X15, X26, X8

      (3103) 0x4e7c78 UBFM	X3, X15, #61, #60

      (3103) 0x4e7c7c LDR	X14, [X0, X3]

      (3103) 0x4e7c80 UBFM	X5, X14, #61, #60

      (3103) 0x4e7c84 CMP	X25, X14

      (3103) 0x4e7c88 B.GT	4e7ca8

      (3103) 0x4e7c8c LDR	D26, [X28, X5]

      (3103) 0x4e7c90 ADD	X1, X1, #1

      (3103) 0x4e7c94 FADD	D19, D26, D18

      (3103) 0x4e7c98 STR	D19, [X28, X5]

      (3103) 0x4e7c9c CMP	X1, X30

      (3103) 0x4e7ca0 B.LT	4e7c60

    (3102) 0x4e7ca4 B	4e7a90

      (3103) 0x4e7ca8 LDR	X30, [SP, #112]

      (3103) 0x4e7cac ADD	X1, X1, #1

      (3103) 0x4e7cb0 STR	X9, [X0, X3]

      (3103) 0x4e7cb4 ADD	X9, X9, #1

      (3103) 0x4e7cb8 STR	D18, [X28, X23]

      (3103) 0x4e7cbc STR	X8, [X30, X23]

      (3103) 0x4e7cc0 LDR	X30, [X4]

      (3103) 0x4e7cc4 CMP	X30, X1

      (3103) 0x4e7cc8 B.GT	4e7c60

    (3102) 0x4e7ccc B	4e7a90

      (3099) 0x4e7cd0 STR	X2, [X0, X7]

      (3099) 0x4e7cd4 ADD	X1, X1, #1

      (3099) 0x4e7cd8 ADD	X2, X2, #1

      (3099) 0x4e7cdc STR	D4, [X19, X8]

      (3099) 0x4e7ce0 STR	X6, [X24, X8]

      (3099) 0x4e7ce4 LDR	X30, [X12]

      (3099) 0x4e7ce8 CMP	X30, X1

      (3099) 0x4e7cec B.GT	4e7bc0

    (3098) 0x4e7cf0 LDR	X12, [X21, #8]

    (3098) 0x4e7cf4 ADD	X13, X13, #1

    (3098) 0x4e7cf8 CMP	X12, X13

    (3098) 0x4e7cfc B.GT	4e7b40

  (3097) 0x4e7d00 B	4e7c0c

      (3100) 0x4e7d04 STR	X9, [X0, X5]

      (3100) 0x4e7d08 ADD	X1, X1, #1

      (3100) 0x4e7d0c ADD	X9, X9, #1

      (3100) 0x4e7d10 STR	D2, [X23, X28]

      (3100) 0x4e7d14 STR	X10, [X4, X28]

      (3100) 0x4e7d18 LDR	X11, [X12]

      (3100) 0x4e7d1c CMP	X11, X1

      (3100) 0x4e7d20 B.GT	4e7b68

    (3098) 0x4e7d24 B	4e7ba8

0x4e7d28 LDR	D15, [SP, #96]

0x4e7d2c LDP	X19, X20, [SP, #16]

0x4e7d30 LDP	X21, X22, [SP, #32]

0x4e7d34 LDP	X23, X24, [SP, #48]

0x4e7d38 LDP	X25, X26, [SP, #64]

0x4e7d3c LDP	X27, X28, [SP, #80]

0x4e7d40 LDP	X29, X30, [SP], #320

0x4e7d44 B	52b3a0

0x4e7d48 MOVZ	X1, #8

0x4e7d4c ADD	X0, X26, X17

0x4e7d50 STP	X13, X18, [SP, #128]

0x4e7d54 STR	X3, [SP, #144]

0x4e7d58 STP	X4, X5, [SP, #160]

0x4e7d5c STP	X6, X7, [SP, #200]

0x4e7d60 STP	X14, X15, [SP, #216]

0x4e7d64 STP	X9, X8, [SP, #232]

0x4e7d68 STR	X12, [SP, #248]

0x4e7d6c BL	52b308

0x4e7d70 LDR	X10, [SP, #248]

0x4e7d74 MOVZ	X1, #0

0x4e7d78 MOVN	X12, #0

0x4e7d7c LDP	X13, X18, [SP, #128]

0x4e7d80 LDP	X4, X5, [SP, #160]

0x4e7d84 LDP	X6, X7, [SP, #200]

0x4e7d88 LDP	X14, X15, [SP, #216]

0x4e7d8c LDP	X9, X8, [SP, #232]

0x4e7d90 LDR	X11, [X10, #184]

0x4e7d94 LDR	X3, [SP, #144]

0x4e7d98 LDR	X2, [X11]

0x4e7d9c ADD	X10, X26, X2

0x4e7da0 CMP	X10, #0

0x4e7da4 B.LE	4e79c8

(3105) 0x4e7da8 STR	X12, [X0, X1,LSL #3]

(3105) 0x4e7dac ADD	X1, X1, #1

(3105) 0x4e7db0 LDR	X30, [X11]

(3105) 0x4e7db4 ADD	X16, X26, X30

(3105) 0x4e7db8 CMP	X16, X1

(3105) 0x4e7dbc B.GT	4e7da8

0x4e7dc0 B	4e79c8

0x4e7dc4 ADD	X8, X25, X1

0x4e7dc8 ADD	X13, X25, X9

0x4e7dcc B	4e7998

Coverage (%)	Name	Source Location	Module
►99.26+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829-832,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.17 to 3.50 cycles (8.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 71% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 29.17 to 23.67 cycles (1.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.17 to 1.50 cycles (19.44x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 608 bytes. The binary function is storing 432 bytes.

General properties

nb instructions	125
loop length	500
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	5.17	5.17	5.17	5.17	5.17	5.17	0.50	0.50	0.00	0.00	29.17	28.83	29.00	19.00	19.00
cycles	5.50	5.50	5.17	5.17	5.17	5.17	5.17	5.17	0.50	0.50	0.00	0.00	29.17	28.83	29.00	19.00	19.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	15.63
Overall L1	29.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.17 cycles. At this rate:

21% of peak load performance is reached (20.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4e78a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #704]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDP X0, X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X3, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X4, X5, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X25, X14, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X7, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X27, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X6, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X9, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X19, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR D15, [X2, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X23, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X13, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X18, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X16, X17, [X2, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X17, X16, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X20, [X2, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X0, X25, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X12, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB X25, X0, X2, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X1, X20, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X20, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X9, X0, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.GE 4e7dc4 <hypre_ParMatmul._omp_fn.3+0x524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X20, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X20, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X12, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X12, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, X26, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X20, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X2, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 4e7d48 <hypre_ParMatmul._omp_fn.3+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X1, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X17, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4e7d28 <hypre_ParMatmul._omp_fn.3+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X16, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X13, X14, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X23, 4e7ad4 <hypre_ParMatmul._omp_fn.3+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 52b3a0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X26, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVN X12, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X10, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X26, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4e79c8 <hypre_ParMatmul._omp_fn.3+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e79c8 <hypre_ParMatmul._omp_fn.3+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X25, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X25, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 4e7998 <hypre_ParMatmul._omp_fn.3+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 29.17 to 3.50 cycles (8.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.17 to 1.50 cycles (19.44x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 608 bytes. The binary function is storing 432 bytes.

General properties

nb instructions	125
loop length	500
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.50	5.50	5.17	5.17	5.17	5.17	5.17	5.17	0.50	0.50	0.00	0.00	29.17	28.83	29.00	19.00	19.00
cycles	5.50	5.50	5.17	5.17	5.17	5.17	5.17	5.17	0.50	0.50	0.00	0.00	29.17	28.83	29.00	19.00	19.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	15.63
Overall L1	29.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.17 cycles. At this rate:

21% of peak load performance is reached (20.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4e78a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #704]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDP X0, X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X15, X3, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X4, X5, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X25, X14, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X7, [X2, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X27, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X6, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X9, [X2, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X19, [X2, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR D15, [X2, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X23, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X13, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X13, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X18, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X16, X17, [X2, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X17, X16, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X20, [X2, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X0, X25, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X12, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MSUB X25, X0, X2, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X1, X20, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X20, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X9, X0, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.GE 4e7dc4 <hypre_ParMatmul._omp_fn.3+0x524>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X30, X20, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X20, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X30, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X12, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X12, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, X26, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X20, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X2, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 4e7d48 <hypre_ParMatmul._omp_fn.3+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X1, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X17, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4e7d28 <hypre_ParMatmul._omp_fn.3+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X16, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X13, X14, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X5, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X28, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X23, 4e7ad4 <hypre_ParMatmul._omp_fn.3+0x234>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #320	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 52b3a0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X26, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVN X12, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP X13, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X14, X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X9, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X10, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X26, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4e79c8 <hypre_ParMatmul._omp_fn.3+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4e79c8 <hypre_ParMatmul._omp_fn.3+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X25, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X25, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B 4e7998 <hypre_ParMatmul._omp_fn.3+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul._omp_fn.3–	1.14	0.18
○Loop 3105 - par_csr_matop.c:858-859 - exec	0.00	0.00
▼Loop 3101 - par_csr_matop.c:865-989 - exec–	0.00	0.00
▼Loop 3097 - par_csr_matop.c:865-989 - exec–	0.01	0.01
▼Loop 3102 - par_csr_matop.c:937-989 - exec–	0.25	0.03
○Loop 3104 - par_csr_matop.c:946-965 - exec	0.87	0.11
○Loop 3103 - par_csr_matop.c:970-989 - exec	0.00	0.00
▼Loop 3098 - par_csr_matop.c:888-928 - exec–	0.00	0.00
○Loop 3100 - par_csr_matop.c:897-915 - exec	0.00	0.00
○Loop 3099 - par_csr_matop.c:917-928 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code