OV - exec - Function hypre_ParMatmul_RowSizes._omp

	Function: hypre_ParMatmul_RowSizes._omp_fn.0	Module: exec	Source: par_csr_matop.c:102-276 [...]	Coverage (incl. loops): 1.06% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 102 - 276

--------------------------------------------------------------------------------

102: #pragma omp parallel private(ii, i1, jj_row_begin_diag, jj_row_begin_offd, jj_count_diag, jj_count_offd, jj2, i2, jj3, i3)

103: #endif

104:    /*for (ii=0; ii < num_threads; ii++)*/

105:    {

106:     HYPRE_Int *B_marker = NULL;

107:     HYPRE_Int ns, ne;

108:     ii = hypre_GetThreadNum();

109:     if (ii < rest)

110:     {

111:        ns = ii*size+ii;

112:        ne = (ii+1)*size+ii+1;

113:     }

114:     else

115:     {

116:        ns = ii*size+rest;

117:        ne = (ii+1)*size+rest;

118:     }

119:     jj_count_diag = start_indexing;

120:     jj_count_offd = start_indexing;

121:

122:     if (num_cols_diag_B || num_cols_offd_C)

123:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

124:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

125:       B_marker[i1] = -1;

126:

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

243:

244:     }

245:     jj_count_diag_array[ii] = jj_count_diag;

246:     jj_count_offd_array[ii] = jj_count_offd;

247:

248:     hypre_TFree(B_marker);

249: #ifdef HYPRE_USING_OPENMP

250: #pragma omp barrier

251: #endif

252:

253:     if (ii)

254:     {

255:        jj_count_diag = jj_count_diag_array[0];

256:        jj_count_offd = jj_count_offd_array[0];

257:        for (i1 = 1; i1 < ii; i1++)

258:        {

259:           jj_count_diag += jj_count_diag_array[i1];

260:           jj_count_offd += jj_count_offd_array[i1];

261:        }

262:

263:        for (i1 = ns; i1 < ne; i1++)

264:        {

265:           (*C_diag_i)[i1] += jj_count_diag;

266:           (*C_offd_i)[i1] += jj_count_offd;

267:        }

268:     }

269:     else

270:     {

271:        (*C_diag_i)[num_rows_diag_A] = 0;

272:        (*C_offd_i)[num_rows_diag_A] = 0;

273:        for (i1 = 0; i1 < num_threads; i1++)

274:        {

275:           (*C_diag_i)[num_rows_diag_A] += jj_count_diag_array[i1];

276:           (*C_offd_i)[num_rows_diag_A] += jj_count_offd_array[i1];

0x4e67c0 STP	X29, X30, [SP, #768]!

0x4e67c4 ADD	X29, SP, #0

0x4e67c8 STP	X19, X20, [SP, #16]

0x4e67cc STP	X21, X22, [SP, #32]

0x4e67d0 STP	X23, X24, [SP, #48]

0x4e67d4 STP	X25, X26, [SP, #64]

0x4e67d8 STP	X27, X28, [SP, #80]

0x4e67dc LDP	X1, X2, [X0]

0x4e67e0 STP	X2, X1, [SP, #168]

0x4e67e4 LDP	X28, X6, [X0, #16]

0x4e67e8 STR	X6, [SP, #232]

0x4e67ec LDP	X10, X3, [X0, #32]

0x4e67f0 STR	X3, [SP, #104]

0x4e67f4 STR	X10, [SP, #224]

0x4e67f8 LDP	X9, X27, [X0, #64]

0x4e67fc LDP	X23, X21, [X0, #48]

0x4e6800 STR	X9, [SP, #216]

0x4e6804 LDP	X8, X26, [X0, #80]

0x4e6808 STR	X8, [SP, #208]

0x4e680c LDP	X7, X25, [X0, #96]

0x4e6810 STR	X7, [SP, #200]

0x4e6814 LDP	X24, X4, [X0, #112]

0x4e6818 LDR	X12, [X0, #208]

0x4e681c STR	X4, [SP, #192]

0x4e6820 LDP	X5, X11, [X0, #128]

0x4e6824 STR	X5, [SP, #112]

0x4e6828 STR	X11, [SP, #128]

0x4e682c LDP	X22, X13, [X0, #144]

0x4e6830 STR	X13, [SP, #184]

0x4e6834 LDP	X14, X18, [X0, #176]

0x4e6838 LDP	X19, X20, [X0, #160]

0x4e683c STP	X18, X14, [SP, #152]

0x4e6840 LDP	X0, X15, [X0, #192]

0x4e6844 STR	X12, [SP, #120]

0x4e6848 STP	X0, X15, [SP, #136]

0x4e684c BL	52df60

0x4e6850 LDP	X2, X18, [SP, #144]

0x4e6854 ORR	X13, XZR, X0

0x4e6858 LDP	X3, X8, [SP, #200]

0x4e685c MADD	X7, X2, X0, XZR

0x4e6860 LDP	X9, X10, [SP, #216]

0x4e6864 ADD	X12, X2, X7

0x4e6868 LDR	X1, [SP, #120]

0x4e686c LDR	X5, [SP, #184]

0x4e6870 LDR	X6, [SP, #232]

0x4e6874 CMP	X1, X0

0x4e6878 B.LE	4e6ce0

0x4e687c ADD	X16, X0, X12

0x4e6880 ORR	X17, X19, X22

0x4e6884 ADD	X4, X0, X7

0x4e6888 ADD	X7, X16, #1

0x4e688c CBNZ	X17, 4e6cf0

(3078) 0x4e6890 MOVZ	X19, #0

(3078) 0x4e6894 CMP	X4, X7

(3078) 0x4e6898 B.GE	4e6d88

(3078) 0x4e689c LDP	X1, X0, [SP, #168]

(3078) 0x4e68a0 ADD	X14, X4, #1

(3078) 0x4e68a4 ORR	X2, XZR, X4

(3078) 0x4e68a8 UBFM	X15, X14, #61, #60

(3078) 0x4e68ac ORR	X14, XZR, X20

(3078) 0x4e68b0 STR	X7, [SP, #120]

(3078) 0x4e68b4 STR	X3, [SP, #184]

(3078) 0x4e68b8 LDR	X0, [X0]

(3078) 0x4e68bc STR	X13, [SP, #216]

(3078) 0x4e68c0 LDR	X1, [X1]

(3078) 0x4e68c4 STP	X4, X18, [SP, #200]

(3078) 0x4e68c8 LDR	X13, [SP, #128]

(3078) 0x4e68cc LDR	X4, [SP, #104]

(3078) 0x4e68d0 CBNZ	X13, 4e69a0

  (3087) 0x4e68d4 ORR	X3, XZR, X20

  (3087) 0x4e68d8 LDR	X18, [SP, #112]

  (3087) 0x4e68dc CBNZ	X18, 4e69b0

    (3085) 0x4e68e0 ORR	X11, XZR, X14

  (3087) 0x4e68e4 LDR	X17, [X28, X2,LSL #3]

  (3087) 0x4e68e8 ORR	X7, XZR, X25

  (3087) 0x4e68ec LDR	X12, [X28, X15]

  (3087) 0x4e68f0 CMP	X17, X12

  (3087) 0x4e68f4 B.GE	4e6974

  (3087) 0x4e68f8 HINT	#0

  (3087) 0x4e68fc HINT	#0

    (3091) 0x4e6900 LDR	X25, [X6, X17,LSL #3]

    (3091) 0x4e6904 UBFM	X18, X25, #61, #60

    (3091) 0x4e6908 ADD	X30, X18, #8

    (3091) 0x4e690c LDR	X12, [X23, X18]

    (3091) 0x4e6910 ADD	X25, X23, X30

    (3091) 0x4e6914 LDR	X16, [X23, X30]

    (3091) 0x4e6918 CMP	X12, X16

    (3091) 0x4e691c B.GE	4e695c

    (3091) 0x4e6920 ORR	X13, XZR, X11

    (3091) 0x4e6924 STR	X0, [SP, #104]

      (3094) 0x4e6928 LDR	X11, [X21, X12,LSL #3]

      (3094) 0x4e692c UBFM	X11, X11, #61, #60

      (3094) 0x4e6930 LDR	X0, [X19, X11]

      (3094) 0x4e6934 CMP	X20, X0

      (3094) 0x4e6938 B.LE	4e6a84

      (3094) 0x4e693c STR	X3, [X19, X11]

      (3094) 0x4e6940 ADD	X12, X12, #1

      (3094) 0x4e6944 ADD	X3, X3, #1

      (3094) 0x4e6948 LDR	X16, [X25]

      (3094) 0x4e694c CMP	X16, X12

      (3094) 0x4e6950 B.GT	4e6928

    (3091) 0x4e6954 LDR	X0, [SP, #104]

    (3091) 0x4e6958 ORR	X11, XZR, X13

    (3091) 0x4e695c CBNZ	X5, 4e6acc

    (3091) 0x4e6960 LDR	X18, [X28, X15]

    (3091) 0x4e6964 ADD	X17, X17, #1

    (3091) 0x4e6968 CMP	X18, X17

    (3091) 0x4e696c B.GT	4e6900

  (3087) 0x4e6970 ORR	X25, XZR, X7

  (3087) 0x4e6974 STR	X20, [X0, X2,LSL #3]

  (3087) 0x4e6978 ADD	X15, X15, #8

  (3087) 0x4e697c LDR	X20, [SP, #120]

  (3087) 0x4e6980 STR	X14, [X1, X2,LSL #3]

  (3087) 0x4e6984 ADD	X2, X2, #1

  (3087) 0x4e6988 CMP	X20, X2

  (3087) 0x4e698c B.EQ	4e6b40

  (3087) 0x4e6990 LDR	X13, [SP, #128]

  (3087) 0x4e6994 ORR	X14, XZR, X11

  (3087) 0x4e6998 ORR	X20, XZR, X3

  (3087) 0x4e699c CBZ	X13, 4e68d4

  (3090) 0x4e69a0 LDR	X18, [SP, #112]

  (3090) 0x4e69a4 ADD	X3, X20, #1

  (3090) 0x4e69a8 STR	X20, [X19, X2,LSL #3]

  (3090) 0x4e69ac CBZ	X18, 4e68e0

  (3087) 0x4e69b0 LDR	X30, [X10, X2,LSL #3]

  (3087) 0x4e69b4 LDR	X12, [X10, X15]

  (3087) 0x4e69b8 CMP	X30, X12

  (3087) 0x4e69bc B.GE	4e68e0

  (3087) 0x4e69c0 LDR	X7, [SP, #184]

  (3087) 0x4e69c4 ORR	X11, XZR, X14

  (3087) 0x4e69c8 STP	X5, X24, [SP, #144]

    (3086) 0x4e69cc LDR	X24, [X4, X30,LSL #3]

    (3086) 0x4e69d0 UBFM	X5, X24, #61, #60

    (3086) 0x4e69d4 ADD	X24, X5, #8

    (3086) 0x4e69d8 LDR	X12, [X7, X5]

    (3086) 0x4e69dc ADD	X17, X7, X24

    (3086) 0x4e69e0 LDR	X16, [X7, X24]

    (3086) 0x4e69e4 CMP	X12, X16

    (3086) 0x4e69e8 B.GE	4e6a24

    (3086) 0x4e69ec STR	X0, [SP, #104]

      (3089) 0x4e69f0 LDR	X0, [X25, X12,LSL #3]

      (3089) 0x4e69f4 ADD	X13, X22, X0

      (3089) 0x4e69f8 UBFM	X18, X13, #61, #60

      (3089) 0x4e69fc LDR	X0, [X19, X18]

      (3089) 0x4e6a00 CMP	X14, X0

      (3089) 0x4e6a04 B.LE	4e6a9c

      (3089) 0x4e6a08 STR	X11, [X19, X18]

      (3089) 0x4e6a0c ADD	X12, X12, #1

      (3089) 0x4e6a10 ADD	X11, X11, #1

      (3089) 0x4e6a14 LDR	X16, [X17]

      (3089) 0x4e6a18 CMP	X12, X16

      (3089) 0x4e6a1c B.LT	4e69f0

    (3086) 0x4e6a20 LDR	X0, [SP, #104]

    (3086) 0x4e6a24 LDR	X13, [X8, X5]

    (3086) 0x4e6a28 ADD	X5, X8, X24

    (3086) 0x4e6a2c LDR	X18, [X8, X24]

    (3086) 0x4e6a30 CMP	X13, X18

    (3086) 0x4e6a34 B.GE	4e6a6c

    (3086) 0x4e6a38 HINT	#0

    (3086) 0x4e6a3c HINT	#0

      (3088) 0x4e6a40 LDR	X24, [X26, X13,LSL #3]

      (3088) 0x4e6a44 UBFM	X17, X24, #61, #60

      (3088) 0x4e6a48 LDR	X12, [X19, X17]

      (3088) 0x4e6a4c CMP	X20, X12

      (3088) 0x4e6a50 B.LE	4e6aac

      (3088) 0x4e6a54 STR	X3, [X19, X17]

      (3088) 0x4e6a58 ADD	X13, X13, #1

      (3088) 0x4e6a5c ADD	X3, X3, #1

      (3088) 0x4e6a60 LDR	X18, [X5]

      (3088) 0x4e6a64 CMP	X18, X13

      (3088) 0x4e6a68 B.GT	4e6a40

    (3086) 0x4e6a6c LDR	X16, [X10, X15]

    (3086) 0x4e6a70 ADD	X30, X30, #1

    (3086) 0x4e6a74 CMP	X16, X30

    (3086) 0x4e6a78 B.GT	4e69cc

  (3087) 0x4e6a7c LDP	X5, X24, [SP, #144]

  (3087) 0x4e6a80 B	4e68e4

      (3094) 0x4e6a84 ADD	X12, X12, #1

      (3094) 0x4e6a88 CMP	X12, X16

      (3094) 0x4e6a8c B.LT	4e6928

    (3091) 0x4e6a90 LDR	X0, [SP, #104]

    (3091) 0x4e6a94 ORR	X11, XZR, X13

    (3091) 0x4e6a98 B	4e695c

      (3089) 0x4e6a9c ADD	X12, X12, #1

      (3089) 0x4e6aa0 CMP	X12, X16

      (3089) 0x4e6aa4 B.LT	4e69f0

    (3086) 0x4e6aa8 B	4e6a20

      (3088) 0x4e6aac ADD	X13, X13, #1

      (3088) 0x4e6ab0 CMP	X13, X18

      (3088) 0x4e6ab4 B.LT	4e6a40

    (3086) 0x4e6ab8 LDR	X16, [X10, X15]

    (3086) 0x4e6abc ADD	X30, X30, #1

    (3086) 0x4e6ac0 CMP	X16, X30

    (3086) 0x4e6ac4 B.GT	4e69cc

  (3087) 0x4e6ac8 B	4e6a7c

    (3091) 0x4e6acc LDR	X13, [X9, X18]

    (3091) 0x4e6ad0 ADD	X18, X9, X30

    (3091) 0x4e6ad4 LDR	X25, [X9, X30]

    (3091) 0x4e6ad8 CMP	X13, X25

    (3091) 0x4e6adc B.GE	4e6960

      (3092) 0x4e6ae0 LDR	X30, [X27, X13,LSL #3]

      (3092) 0x4e6ae4 LDR	X12, [X24, X30,LSL #3]

      (3092) 0x4e6ae8 ADD	X16, X22, X12

      (3092) 0x4e6aec UBFM	X30, X16, #61, #60

      (3092) 0x4e6af0 LDR	X12, [X19, X30]

      (3092) 0x4e6af4 CMP	X14, X12

      (3092) 0x4e6af8 B.LE	4e6b30

      (3093) 0x4e6afc STR	X11, [X19, X30]

      (3093) 0x4e6b00 ADD	X13, X13, #1

      (3093) 0x4e6b04 ADD	X11, X11, #1

      (3093) 0x4e6b08 LDR	X25, [X18]

      (3093) 0x4e6b0c CMP	X25, X13

      (3093) 0x4e6b10 B.LE	4e6960

      (3093) 0x4e6b14 LDR	X30, [X27, X13,LSL #3]

      (3093) 0x4e6b18 LDR	X12, [X24, X30,LSL #3]

      (3093) 0x4e6b1c ADD	X16, X22, X12

      (3093) 0x4e6b20 UBFM	X30, X16, #61, #60

      (3093) 0x4e6b24 LDR	X12, [X19, X30]

      (3093) 0x4e6b28 CMP	X14, X12

      (3093) 0x4e6b2c B.GT	4e6afc

      (3092) 0x4e6b30 ADD	X13, X13, #1

      (3092) 0x4e6b34 CMP	X25, X13

      (3092) 0x4e6b38 B.GT	4e6ae0

    (3091) 0x4e6b3c B	4e6960

(3078) 0x4e6b40 LDR	X13, [SP, #216]

(3078) 0x4e6b44 ORR	X7, XZR, X20

(3078) 0x4e6b48 LDP	X4, X18, [SP, #200]

(3078) 0x4e6b4c UBFM	X28, X13, #61, #60

(3078) 0x4e6b50 ORR	X0, XZR, X19

(3078) 0x4e6b54 STR	X3, [X18, X28]

(3078) 0x4e6b58 LDR	X23, [SP, #136]

(3078) 0x4e6b5c STR	X11, [X23, X28]

(3078) 0x4e6b60 STP	X18, X13, [SP, #104]

(3078) 0x4e6b64 STP	X4, X7, [SP, #120]

(3078) 0x4e6b68 BL	52b3a0

(3078) 0x4e6b6c BL	410d30

(3078) 0x4e6b70 LDP	X21, X13, [SP, #104]

(3078) 0x4e6b74 LDP	X4, X12, [SP, #120]

(3078) 0x4e6b78 CBNZ	X13, 4e6d94

(3078) 0x4e6b7c LDR	X27, [SP, #176]

(3078) 0x4e6b80 LDR	X9, [SP, #168]

(3078) 0x4e6b84 LDR	X26, [SP, #192]

(3078) 0x4e6b88 LDR	X8, [X27]

(3078) 0x4e6b8c LDR	X10, [X9]

(3078) 0x4e6b90 UBFM	X22, X26, #61, #60

(3078) 0x4e6b94 LDR	X6, [SP, #160]

(3078) 0x4e6b98 STR	XZR, [X8, X22]

(3078) 0x4e6b9c ADD	X19, X8, X26,LSL #3

(3078) 0x4e6ba0 STR	XZR, [X10, X22]

(3078) 0x4e6ba4 ADD	X14, X10, X22

(3078) 0x4e6ba8 CMP	X6, #0

(3078) 0x4e6bac B.LE	4e6cc4

(3078) 0x4e6bb0 ANDS	X4, X6, #4160

(3078) 0x4e6bb4 B.EQ	4e6c24

(3078) 0x4e6bb8 CMP	X4, #1

(3078) 0x4e6bbc B.EQ	4e6bf0

(3078) 0x4e6bc0 CMP	X4, #2

(3078) 0x4e6bc4 B.NE	4e72e0

(3078) 0x4e6bc8 LDR	X16, [X21, X13,LSL #3]

(3078) 0x4e6bcc LDR	X30, [X19]

(3078) 0x4e6bd0 LDR	X25, [SP, #136]

(3078) 0x4e6bd4 ADD	X12, X30, X16

(3078) 0x4e6bd8 STR	X12, [X19]

(3078) 0x4e6bdc LDR	X18, [X25, X13,LSL #3]

(3078) 0x4e6be0 ADD	X13, X13, #1

(3078) 0x4e6be4 LDR	X17, [X14]

(3078) 0x4e6be8 ADD	X15, X17, X18

(3078) 0x4e6bec STR	X15, [X14]

(3078) 0x4e6bf0 LDR	X20, [X21, X13,LSL #3]

(3078) 0x4e6bf4 LDR	X2, [X19]

(3078) 0x4e6bf8 LDR	X23, [SP, #136]

(3078) 0x4e6bfc LDR	X8, [SP, #160]

(3078) 0x4e6c00 ADD	X28, X2, X20

(3078) 0x4e6c04 STR	X28, [X19]

(3078) 0x4e6c08 LDR	X27, [X23, X13,LSL #3]

(3078) 0x4e6c0c ADD	X13, X13, #1

(3078) 0x4e6c10 LDR	X26, [X14]

(3078) 0x4e6c14 ADD	X22, X26, X27

(3078) 0x4e6c18 STR	X22, [X14]

(3078) 0x4e6c1c CMP	X8, X13

(3078) 0x4e6c20 B.EQ	4e6cc4

(3078) 0x4e6c24 LDR	X9, [SP, #136]

  (3084) 0x4e6c28 ADD	X10, X13, #1

  (3084) 0x4e6c2c ADD	X6, X13, #2

  (3084) 0x4e6c30 LDR	X4, [X21, X13,LSL #3]

  (3084) 0x4e6c34 ADD	X1, X13, #3

  (3084) 0x4e6c38 LDR	X3, [X19]

  (3084) 0x4e6c3c ADD	X5, X3, X4

  (3084) 0x4e6c40 STR	X5, [X19]

  (3084) 0x4e6c44 LDR	X24, [X9, X13,LSL #3]

  (3084) 0x4e6c48 ADD	X13, X13, #4

  (3084) 0x4e6c4c LDR	X7, [X14]

  (3084) 0x4e6c50 ADD	X11, X7, X24

  (3084) 0x4e6c54 STR	X11, [X14]

  (3084) 0x4e6c58 LDR	X0, [X21, X10,LSL #3]

  (3084) 0x4e6c5c LDR	X16, [X19]

  (3084) 0x4e6c60 ADD	X30, X16, X0

  (3084) 0x4e6c64 STR	X30, [X19]

  (3084) 0x4e6c68 LDR	X12, [X9, X10,LSL #3]

  (3084) 0x4e6c6c LDR	X25, [X14]

  (3084) 0x4e6c70 ADD	X18, X25, X12

  (3084) 0x4e6c74 STR	X18, [X14]

  (3084) 0x4e6c78 LDR	X17, [X21, X6,LSL #3]

  (3084) 0x4e6c7c LDR	X15, [X19]

  (3084) 0x4e6c80 ADD	X20, X15, X17

  (3084) 0x4e6c84 STR	X20, [X19]

  (3084) 0x4e6c88 LDR	X2, [X9, X6,LSL #3]

  (3084) 0x4e6c8c LDR	X28, [X14]

  (3084) 0x4e6c90 LDR	X6, [SP, #160]

  (3084) 0x4e6c94 ADD	X23, X28, X2

  (3084) 0x4e6c98 STR	X23, [X14]

  (3084) 0x4e6c9c LDR	X27, [X21, X1,LSL #3]

  (3084) 0x4e6ca0 LDR	X26, [X19]

  (3084) 0x4e6ca4 ADD	X22, X26, X27

  (3084) 0x4e6ca8 STR	X22, [X19]

  (3084) 0x4e6cac LDR	X8, [X9, X1,LSL #3]

  (3084) 0x4e6cb0 LDR	X10, [X14]

  (3084) 0x4e6cb4 ADD	X1, X10, X8

  (3084) 0x4e6cb8 STR	X1, [X14]

  (3084) 0x4e6cbc CMP	X6, X13

  (3084) 0x4e6cc0 B.NE	4e6c28

(3078) 0x4e6cc4 LDP	X19, X20, [SP, #16]

(3078) 0x4e6cc8 LDP	X21, X22, [SP, #32]

(3078) 0x4e6ccc LDP	X23, X24, [SP, #48]

(3078) 0x4e6cd0 LDP	X25, X26, [SP, #64]

(3078) 0x4e6cd4 LDP	X27, X28, [SP, #80]

(3078) 0x4e6cd8 LDP	X29, X30, [SP], #256

(3078) 0x4e6cdc RET

(3078) 0x4e6ce0 ORR	X17, X19, X22

(3078) 0x4e6ce4 ADD	X4, X1, X7

(3078) 0x4e6ce8 ADD	X7, X1, X12

(3078) 0x4e6cec CBZ	X17, 4e6890

(3078) 0x4e6cf0 ADD	X30, X19, X22

(3078) 0x4e6cf4 MOVZ	X1, #8

(3078) 0x4e6cf8 STP	X4, X7, [SP, #144]

(3078) 0x4e6cfc ORR	X0, XZR, X30

(3078) 0x4e6d00 STR	X30, [SP, #120]

(3078) 0x4e6d04 STR	X18, [SP, #184]

(3078) 0x4e6d08 STP	X5, X3, [SP, #200]

(3078) 0x4e6d0c STP	X8, X9, [SP, #216]

(3078) 0x4e6d10 STP	X10, X6, [SP, #232]

(3078) 0x4e6d14 STR	X13, [SP, #248]

(3078) 0x4e6d18 BL	52b308

(3078) 0x4e6d1c LDR	X11, [SP, #120]

(3078) 0x4e6d20 ORR	X19, XZR, X0

(3078) 0x4e6d24 LDP	X4, X7, [SP, #144]

(3078) 0x4e6d28 LDP	X5, X3, [SP, #200]

(3078) 0x4e6d2c LDP	X8, X9, [SP, #216]

(3078) 0x4e6d30 LDP	X10, X6, [SP, #232]

(3078) 0x4e6d34 LDR	X18, [SP, #184]

(3078) 0x4e6d38 LDR	X13, [SP, #248]

(3078) 0x4e6d3c CMP	X11, #0

(3078) 0x4e6d40 B.LE	4e6894

(3078) 0x4e6d44 UBFM	X2, X11, #61, #60

(3078) 0x4e6d48 MOVZ	W1, #255

(3078) 0x4e6d4c STR	X4, [SP, #120]

(3078) 0x4e6d50 STP	X7, X18, [SP, #144]

(3078) 0x4e6d54 STR	X5, [SP, #184]

(3078) 0x4e6d58 STP	X3, X8, [SP, #200]

(3078) 0x4e6d5c STP	X9, X10, [SP, #216]

(3078) 0x4e6d60 STP	X6, X13, [SP, #232]

(3078) 0x4e6d64 BL	410950

(3078) 0x4e6d68 LDR	X4, [SP, #120]

(3078) 0x4e6d6c LDP	X7, X18, [SP, #144]

(3078) 0x4e6d70 LDP	X3, X8, [SP, #200]

(3078) 0x4e6d74 LDP	X9, X10, [SP, #216]

(3078) 0x4e6d78 LDP	X6, X13, [SP, #232]

(3078) 0x4e6d7c LDR	X5, [SP, #184]

(3078) 0x4e6d80 CMP	X4, X7

(3078) 0x4e6d84 B.LT	4e689c

(3078) 0x4e6d88 ORR	X11, XZR, X20

(3078) 0x4e6d8c ORR	X3, XZR, X20

(3078) 0x4e6d90 B	4e6b4c

(3078) 0x4e6d94 LDR	X19, [SP, #136]

(3078) 0x4e6d98 LDR	X6, [X21]

(3078) 0x4e6d9c LDR	X7, [X19]

(3078) 0x4e6da0 CMP	X13, #1

(3078) 0x4e6da4 B.LE	4e703c

(3078) 0x4e6da8 SUB	X14, X13, #2

(3078) 0x4e6dac SUB	X5, X13, #1

(3078) 0x4e6db0 CMP	X14, #6

(3078) 0x4e6db4 B.LS	4e7520

(3078) 0x4e6db8 UBFM	X9, X5, #3, #63

(3078) 0x4e6dbc LDR	X25, [SP, #136]

(3078) 0x4e6dc0 MOVI	V20.4S, #0

(3078) 0x4e6dc4 ORR	X20, XZR, X21

(3078) 0x4e6dc8 UBFM	X24, X9, #58, #57

(3078) 0x4e6dcc ADD	X3, X21, X9,LSL #6

(3078) 0x4e6dd0 SUB	X11, X24, #64

(3078) 0x4e6dd4 UBFM	X0, X11, #6, #63

(3078) 0x4e6dd8 ADD	X16, X0, #1

(3078) 0x4e6ddc ORR	V25.16B, V20.16B, V20.16B

(3078) 0x4e6de0 ORR	V19.16B, V20.16B, V20.16B

(3078) 0x4e6de4 ANDS	X30, X16, #4160

(3078) 0x4e6de8 ORR	V30.16B, V20.16B, V20.16B

(3078) 0x4e6dec ORR	V18.16B, V20.16B, V20.16B

(3078) 0x4e6df0 ADD	X15, X25, #8

(3078) 0x4e6df4 ORR	V17.16B, V20.16B, V20.16B

(3078) 0x4e6df8 ORR	V16.16B, V20.16B, V20.16B

(3078) 0x4e6dfc ORR	V31.16B, V20.16B, V20.16B

(3078) 0x4e6e00 B.EQ	4e6e9c

(3078) 0x4e6e04 CMP	X30, #1

(3078) 0x4e6e08 B.EQ	4e6e54

(3078) 0x4e6e0c CMP	X30, #2

(3078) 0x4e6e10 B.NE	4e72bc

  (3081) 0x4e6e14 LDP	Q26, Q28, [X15]

  (3081) 0x4e6e18 ADD	X20, X20, #64

  (3081) 0x4e6e1c LDP	Q0, Q1, [X15, #32]

  (3081) 0x4e6e20 ADD	X15, X15, #64

  (3081) 0x4e6e24 LDUR	Q27, [X20, #456]

  (3081) 0x4e6e28 LDUR	Q29, [X20, #472]

  (3081) 0x4e6e2c LDUR	Q2, [X20, #488]

  (3081) 0x4e6e30 ADD	V30.2D, V30.2D, V26.2D

  (3081) 0x4e6e34 ADD	V19.2D, V19.2D, V28.2D

  (3081) 0x4e6e38 LDUR	Q3, [X20, #504]

  (3081) 0x4e6e3c ADD	V31.2D, V31.2D, V27.2D

  (3081) 0x4e6e40 ADD	V25.2D, V25.2D, V0.2D

  (3081) 0x4e6e44 ADD	V20.2D, V20.2D, V1.2D

  (3081) 0x4e6e48 ADD	V16.2D, V16.2D, V29.2D

  (3081) 0x4e6e4c ADD	V17.2D, V17.2D, V2.2D

  (3081) 0x4e6e50 ADD	V18.2D, V18.2D, V3.2D

  (3081) 0x4e6e54 LDP	Q4, Q5, [X15]

  (3081) 0x4e6e58 ADD	X20, X20, #64

  (3081) 0x4e6e5c LDP	Q6, Q7, [X15, #32]

  (3081) 0x4e6e60 ADD	X15, X15, #64

  (3081) 0x4e6e64 LDUR	Q21, [X20, #456]

  (3081) 0x4e6e68 LDUR	Q22, [X20, #472]

  (3081) 0x4e6e6c LDUR	Q23, [X20, #488]

  (3081) 0x4e6e70 ADD	V30.2D, V30.2D, V4.2D

  (3081) 0x4e6e74 ADD	V19.2D, V19.2D, V5.2D

  (3081) 0x4e6e78 LDUR	Q24, [X20, #504]

  (3081) 0x4e6e7c ADD	V31.2D, V31.2D, V21.2D

  (3081) 0x4e6e80 ADD	V25.2D, V25.2D, V6.2D

  (3081) 0x4e6e84 ADD	V20.2D, V20.2D, V7.2D

  (3081) 0x4e6e88 ADD	V16.2D, V16.2D, V22.2D

  (3081) 0x4e6e8c ADD	V17.2D, V17.2D, V23.2D

  (3081) 0x4e6e90 ADD	V18.2D, V18.2D, V24.2D

  (3081) 0x4e6e94 CMP	X3, X20

  (3081) 0x4e6e98 B.EQ	4e6fa0

    (3083) 0x4e6e9c LDP	Q26, Q28, [X15]

    (3083) 0x4e6ea0 ADD	X22, X20, #8

    (3083) 0x4e6ea4 ADD	X28, X20, #64

    (3083) 0x4e6ea8 ADD	X8, X28, #8

    (3083) 0x4e6eac ADD	X2, X15, #64

    (3083) 0x4e6eb0 LDP	Q29, Q27, [X15, #32]

    (3083) 0x4e6eb4 ADD	X23, X15, #128

    (3083) 0x4e6eb8 ADD	X26, X15, #192

    (3083) 0x4e6ebc ORR	X27, XZR, X20

    (3083) 0x4e6ec0 ADD	X20, X20, #256

    (3083) 0x4e6ec4 LDP	Q4, Q5, [X22]

    (3083) 0x4e6ec8 ADD	X15, X15, #256

    (3083) 0x4e6ecc ADD	V1.2D, V19.2D, V28.2D

    (3083) 0x4e6ed0 ADD	V0.2D, V30.2D, V26.2D

    (3083) 0x4e6ed4 LDP	Q30, Q19, [X22, #32]

    (3083) 0x4e6ed8 ADD	V2.2D, V25.2D, V29.2D

    (3083) 0x4e6edc ADD	V3.2D, V20.2D, V27.2D

    (3083) 0x4e6ee0 LDP	Q25, Q20, [X2, #16]

    (3083) 0x4e6ee4 ADD	V6.2D, V31.2D, V4.2D

    (3083) 0x4e6ee8 ADD	V7.2D, V16.2D, V5.2D

    (3083) 0x4e6eec LDP	Q31, Q24, [X8]

    (3083) 0x4e6ef0 LDP	Q28, Q27, [X2, #48]

    (3083) 0x4e6ef4 LDUR	Q4, [X15, #320]

    (3083) 0x4e6ef8 ADD	V23.2D, V18.2D, V19.2D

    (3083) 0x4e6efc ADD	V16.2D, V17.2D, V30.2D

    (3083) 0x4e6f00 LDP	Q18, Q21, [X8, #32]

    (3083) 0x4e6f04 ADD	V22.2D, V1.2D, V25.2D

    (3083) 0x4e6f08 ADD	V17.2D, V2.2D, V20.2D

    (3083) 0x4e6f0c LDP	Q5, Q30, [X23, #16]

    (3083) 0x4e6f10 ADD	V1.2D, V6.2D, V31.2D

    (3083) 0x4e6f14 ADD	V2.2D, V7.2D, V24.2D

    (3083) 0x4e6f18 LDUR	Q19, [X28, #72]

    (3083) 0x4e6f1c ADD	V0.2D, V0.2D, V4.2D

    (3083) 0x4e6f20 ADD	V3.2D, V3.2D, V28.2D

    (3083) 0x4e6f24 LDUR	Q25, [X28, #104]

    (3083) 0x4e6f28 LDUR	Q31, [X15, #448]

    (3083) 0x4e6f2c ADD	V29.2D, V23.2D, V21.2D

    (3083) 0x4e6f30 ADD	V26.2D, V16.2D, V18.2D

    (3083) 0x4e6f34 LDUR	Q21, [X28, #120]

    (3083) 0x4e6f38 ADD	V16.2D, V0.2D, V27.2D

    (3083) 0x4e6f3c ADD	V7.2D, V17.2D, V30.2D

    (3083) 0x4e6f40 ADD	V17.2D, V1.2D, V19.2D

    (3083) 0x4e6f44 LDUR	Q23, [X28, #88]

    (3083) 0x4e6f48 ADD	V6.2D, V22.2D, V5.2D

    (3083) 0x4e6f4c ADD	V18.2D, V26.2D, V25.2D

    (3083) 0x4e6f50 LDP	Q20, Q22, [X26, #16]

    (3083) 0x4e6f54 ADD	V30.2D, V16.2D, V31.2D

    (3083) 0x4e6f58 ADD	V1.2D, V29.2D, V21.2D

    (3083) 0x4e6f5c LDR	Q29, [X23, #48]

    (3083) 0x4e6f60 LDR	Q4, [X26, #48]

    (3083) 0x4e6f64 ADD	V24.2D, V2.2D, V23.2D

    (3083) 0x4e6f68 LDUR	Q2, [X27, #200]

    (3083) 0x4e6f6c LDUR	Q26, [X27, #216]

    (3083) 0x4e6f70 ADD	V3.2D, V3.2D, V29.2D

    (3083) 0x4e6f74 ADD	V19.2D, V6.2D, V20.2D

    (3083) 0x4e6f78 ADD	V25.2D, V7.2D, V22.2D

    (3083) 0x4e6f7c LDUR	Q28, [X27, #232]

    (3083) 0x4e6f80 LDUR	Q27, [X27, #248]

    (3083) 0x4e6f84 ADD	V31.2D, V17.2D, V2.2D

    (3083) 0x4e6f88 ADD	V20.2D, V3.2D, V4.2D

    (3083) 0x4e6f8c ADD	V16.2D, V24.2D, V26.2D

    (3083) 0x4e6f90 ADD	V17.2D, V18.2D, V28.2D

    (3083) 0x4e6f94 ADD	V18.2D, V1.2D, V27.2D

    (3083) 0x4e6f98 CMP	X3, X20

    (3083) 0x4e6f9c B.NE	4e6e9c

  (3081) 0x4e6fa0 ADD	V0.2D, V19.2D, V30.2D

  (3081) 0x4e6fa4 ADD	V5.2D, V16.2D, V31.2D

  (3081) 0x4e6fa8 AND	X13, X5, #7997

  (3081) 0x4e6fac ADD	V6.2D, V0.2D, V25.2D

  (3081) 0x4e6fb0 ADD	V30.2D, V5.2D, V17.2D

  (3081) 0x4e6fb4 ADD	V7.2D, V6.2D, V20.2D

  (3081) 0x4e6fb8 ADD	V16.2D, V30.2D, V18.2D

  (3081) 0x4e6fbc ADDP	D19, V7.2D

  (3081) 0x4e6fc0 ADDP	D23, V16.2D

  (3081) 0x4e6fc4 FMOV	X10, D19

  (3081) 0x4e6fc8 FMOV	X1, D23

  (3081) 0x4e6fcc ADD	X7, X7, X10

  (3081) 0x4e6fd0 ADD	X6, X6, X1

  (3081) 0x4e6fd4 ANDS	XZR, X5, #4224

  (3081) 0x4e6fd8 B.EQ	4e703c

  (3081) 0x4e6fdc ADD	X19, X13, #1

  (3081) 0x4e6fe0 SUB	X13, X5, X13

  (3081) 0x4e6fe4 LDR	X5, [SP, #136]

  (3081) 0x4e6fe8 DUP	Z25.B, #0

  (3081) 0x4e6fec WHILELO	P7.D, XZR, X13

  (3081) 0x4e6ff0 ADD	X21, X21, X19,LSL #3

  (3081) 0x4e6ff4 MOVZ	X24, #0

  (3081) 0x4e6ff8 CNTD	X14, ALL

  (3081) 0x4e6ffc ORR	Z17.D, Z25.D, Z25.D

  (3081) 0x4e7000 ADD	X9, X5, X19,LSL #3

    (3082) 0x4e7004 LD1D	{Z24.D}, P7/Z, [X21, X24,LSL #3]

    (3082) 0x4e7008 LD1D	{Z18.D}, P7/Z, [X9, X24,LSL #3]

    (3082) 0x4e700c ADD	Z17.D, P7/M, Z17.D, Z24.D

    (3082) 0x4e7010 ADD	X24, X24, X14

    (3082) 0x4e7014 ADD	Z25.D, P7/M, Z25.D, Z18.D

    (3082) 0x4e7018 WHILELO	P7.D, X24, X13

    (3082) 0x4e701c B.NE	4e7004

  (3081) 0x4e7020 PTRUE	P0.B, ALL

  (3081) 0x4e7024 UADDV	D20, P0, Z25.D

  (3081) 0x4e7028 UADDV	D22, P0, Z17.D

  (3081) 0x4e702c FMOV	X3, D20

  (3081) 0x4e7030 FMOV	X11, D22

  (3081) 0x4e7034 ADD	X7, X7, X3

  (3081) 0x4e7038 ADD	X6, X6, X11

  (3081) 0x4e703c CMP	X4, X12

  (3081) 0x4e7040 B.GE	4e6cc4

  (3081) 0x4e7044 LDP	X16, X0, [SP, #168]

  (3081) 0x4e7048 SUB	X30, X12, X4

  (3081) 0x4e704c SUB	X18, X30, #1

  (3081) 0x4e7050 LDR	X25, [X0]

  (3081) 0x4e7054 LDR	X17, [X16]

  (3081) 0x4e7058 CMP	X18, #2

  (3081) 0x4e705c B.LS	4e730c

  (3081) 0x4e7060 ADD	X15, X4, #2

  (3081) 0x4e7064 UBFM	X20, X15, #61, #60

  (3081) 0x4e7068 SUB	X28, X20, #16

  (3081) 0x4e706c ADD	X2, X17, X20

  (3081) 0x4e7070 ADD	X23, X25, X28

  (3081) 0x4e7074 ADD	X27, X17, X28

  (3081) 0x4e7078 CMP	X23, X2

  (3081) 0x4e707c ADD	X26, X25, X20

  (3081) 0x4e7080 CCMP	X27, X26, #2, #3

  (3081) 0x4e7084 B.CC	4e730c

  (3081) 0x4e7088 UBFM	X22, X30, #1, #63

  (3081) 0x4e708c DUP	V31.2D, X6

  (3081) 0x4e7090 MOVZ	X21, #0

  (3081) 0x4e7094 UBFM	X8, X22, #60, #59

  (3081) 0x4e7098 SUB	X10, X8, #16

  (3081) 0x4e709c DUP	V30.2D, X7

  (3081) 0x4e70a0 UBFM	X1, X10, #4, #63

  (3081) 0x4e70a4 ADD	X19, X1, #1

  (3081) 0x4e70a8 ANDS	X14, X19, #4224

  (3081) 0x4e70ac B.EQ	4e7190

  (3081) 0x4e70b0 CMP	X14, #1

  (3081) 0x4e70b4 B.EQ	4e716c

  (3081) 0x4e70b8 CMP	X14, #2

  (3081) 0x4e70bc B.EQ	4e7150

  (3081) 0x4e70c0 CMP	X14, #3

  (3081) 0x4e70c4 B.EQ	4e7134

  (3081) 0x4e70c8 CMP	X14, #4

  (3081) 0x4e70cc B.EQ	4e7118

  (3081) 0x4e70d0 CMP	X14, #5

  (3081) 0x4e70d4 B.EQ	4e70fc

  (3081) 0x4e70d8 CMP	X14, #6

  (3081) 0x4e70dc B.NE	4e7500

  (3081) 0x4e70e0 LDR	Q28, [X23, X21]

  (3081) 0x4e70e4 ADD	V27.2D, V28.2D, V31.2D

  (3081) 0x4e70e8 STR	Q27, [X23, X21]

  (3081) 0x4e70ec LDR	Q29, [X27, X21]

  (3081) 0x4e70f0 ADD	V3.2D, V29.2D, V30.2D

  (3081) 0x4e70f4 STR	Q3, [X27, X21]

  (3081) 0x4e70f8 ADD	X21, X21, #16

  (3081) 0x4e70fc LDR	Q4, [X23, X21]

  (3081) 0x4e7100 ADD	V0.2D, V4.2D, V31.2D

  (3081) 0x4e7104 STR	Q0, [X23, X21]

  (3081) 0x4e7108 LDR	Q5, [X27, X21]

  (3081) 0x4e710c ADD	V6.2D, V5.2D, V30.2D

  (3081) 0x4e7110 STR	Q6, [X27, X21]

  (3081) 0x4e7114 ADD	X21, X21, #16

  (3081) 0x4e7118 LDR	Q7, [X23, X21]

  (3081) 0x4e711c ADD	V16.2D, V7.2D, V31.2D

  (3081) 0x4e7120 STR	Q16, [X23, X21]

  (3081) 0x4e7124 LDR	Q19, [X27, X21]

  (3081) 0x4e7128 ADD	V23.2D, V19.2D, V30.2D

  (3081) 0x4e712c STR	Q23, [X27, X21]

  (3081) 0x4e7130 ADD	X21, X21, #16

  (3081) 0x4e7134 LDR	Q25, [X23, X21]

  (3081) 0x4e7138 ADD	V17.2D, V25.2D, V31.2D

  (3081) 0x4e713c STR	Q17, [X23, X21]

  (3081) 0x4e7140 LDR	Q24, [X27, X21]

  (3081) 0x4e7144 ADD	V18.2D, V24.2D, V30.2D

  (3081) 0x4e7148 STR	Q18, [X27, X21]

  (3081) 0x4e714c ADD	X21, X21, #16

  (3081) 0x4e7150 LDR	Q20, [X23, X21]

  (3081) 0x4e7154 ADD	V22.2D, V20.2D, V31.2D

  (3081) 0x4e7158 STR	Q22, [X23, X21]

  (3081) 0x4e715c LDR	Q21, [X27, X21]

  (3081) 0x4e7160 ADD	V1.2D, V21.2D, V30.2D

  (3081) 0x4e7164 STR	Q1, [X27, X21]

  (3081) 0x4e7168 ADD	X21, X21, #16

  (3081) 0x4e716c LDR	Q2, [X23, X21]

  (3081) 0x4e7170 ADD	V26.2D, V2.2D, V31.2D

  (3081) 0x4e7174 STR	Q26, [X23, X21]

  (3081) 0x4e7178 LDR	Q28, [X27, X21]

  (3081) 0x4e717c ADD	V27.2D, V28.2D, V30.2D

  (3081) 0x4e7180 STR	Q27, [X27, X21]

  (3081) 0x4e7184 ADD	X21, X21, #16

  (3081) 0x4e7188 CMP	X8, X21

  (3081) 0x4e718c B.EQ	4e7278

    (3080) 0x4e7190 LDR	Q29, [X23, X21]

    (3080) 0x4e7194 ADD	X5, X21, #16

    (3080) 0x4e7198 ADD	X24, X21, #32

    (3080) 0x4e719c ADD	X9, X21, #48

    (3080) 0x4e71a0 ADD	X3, X21, #64

    (3080) 0x4e71a4 ADD	X13, X21, #80

    (3080) 0x4e71a8 ADD	X12, X21, #96

    (3080) 0x4e71ac ADD	X11, X21, #112

    (3080) 0x4e71b0 ADD	V3.2D, V29.2D, V31.2D

    (3080) 0x4e71b4 STR	Q3, [X23, X21]

    (3080) 0x4e71b8 LDR	Q4, [X27, X21]

    (3080) 0x4e71bc ADD	V0.2D, V4.2D, V30.2D

    (3080) 0x4e71c0 STR	Q0, [X27, X21]

    (3080) 0x4e71c4 ADD	X21, X21, #128

    (3080) 0x4e71c8 LDR	Q5, [X23, X5]

    (3080) 0x4e71cc ADD	V6.2D, V5.2D, V31.2D

    (3080) 0x4e71d0 STR	Q6, [X23, X5]

    (3080) 0x4e71d4 LDR	Q7, [X27, X5]

    (3080) 0x4e71d8 ADD	V16.2D, V7.2D, V30.2D

    (3080) 0x4e71dc STR	Q16, [X27, X5]

    (3080) 0x4e71e0 LDR	Q19, [X23, X24]

    (3080) 0x4e71e4 ADD	V23.2D, V19.2D, V31.2D

    (3080) 0x4e71e8 STR	Q23, [X23, X24]

    (3080) 0x4e71ec LDR	Q25, [X27, X24]

    (3080) 0x4e71f0 ADD	V17.2D, V25.2D, V30.2D

    (3080) 0x4e71f4 STR	Q17, [X27, X24]

    (3080) 0x4e71f8 LDR	Q24, [X23, X9]

    (3080) 0x4e71fc ADD	V18.2D, V24.2D, V31.2D

    (3080) 0x4e7200 STR	Q18, [X23, X9]

    (3080) 0x4e7204 LDR	Q20, [X27, X9]

    (3080) 0x4e7208 ADD	V22.2D, V20.2D, V30.2D

    (3080) 0x4e720c STR	Q22, [X27, X9]

    (3080) 0x4e7210 LDR	Q21, [X23, X3]

    (3080) 0x4e7214 ADD	V1.2D, V21.2D, V31.2D

    (3080) 0x4e7218 STR	Q1, [X23, X3]

    (3080) 0x4e721c LDR	Q2, [X27, X3]

    (3080) 0x4e7220 ADD	V26.2D, V2.2D, V30.2D

    (3080) 0x4e7224 STR	Q26, [X27, X3]

    (3080) 0x4e7228 LDR	Q28, [X23, X13]

    (3080) 0x4e722c ADD	V27.2D, V28.2D, V31.2D

    (3080) 0x4e7230 STR	Q27, [X23, X13]

    (3080) 0x4e7234 LDR	Q29, [X27, X13]

    (3080) 0x4e7238 ADD	V3.2D, V29.2D, V30.2D

    (3080) 0x4e723c STR	Q3, [X27, X13]

    (3080) 0x4e7240 LDR	Q4, [X23, X12]

    (3080) 0x4e7244 ADD	V0.2D, V4.2D, V31.2D

    (3080) 0x4e7248 STR	Q0, [X23, X12]

    (3080) 0x4e724c LDR	Q5, [X27, X12]

    (3080) 0x4e7250 ADD	V6.2D, V5.2D, V30.2D

    (3080) 0x4e7254 STR	Q6, [X27, X12]

    (3080) 0x4e7258 LDR	Q7, [X23, X11]

    (3080) 0x4e725c ADD	V16.2D, V7.2D, V31.2D

    (3080) 0x4e7260 STR	Q16, [X23, X11]

    (3080) 0x4e7264 LDR	Q19, [X27, X11]

    (3080) 0x4e7268 ADD	V23.2D, V19.2D, V30.2D

    (3080) 0x4e726c STR	Q23, [X27, X11]

    (3080) 0x4e7270 CMP	X8, X21

    (3080) 0x4e7274 B.NE	4e7190

  (3081) 0x4e7278 TBZ	W30, #0, 4e6cc4

  (3081) 0x4e727c AND	X30, X30, #8127

  (3081) 0x4e7280 ADD	X4, X30, X4

  (3081) 0x4e7284 UBFM	X16, X4, #61, #60

  (3081) 0x4e7288 LDR	X0, [X25, X16]

  (3081) 0x4e728c ADD	X6, X0, X6

  (3081) 0x4e7290 STR	X6, [X25, X16]

  (3081) 0x4e7294 LDR	X25, [X17, X16]

  (3081) 0x4e7298 ADD	X7, X25, X7

  (3081) 0x4e729c STR	X7, [X17, X16]

  (3081) 0x4e72a0 LDP	X19, X20, [SP, #16]

  (3081) 0x4e72a4 LDP	X21, X22, [SP, #32]

  (3081) 0x4e72a8 LDP	X23, X24, [SP, #48]

  (3081) 0x4e72ac LDP	X25, X26, [SP, #64]

  (3081) 0x4e72b0 LDP	X27, X28, [SP, #80]

  (3081) 0x4e72b4 LDP	X29, X30, [SP], #256

  (3081) 0x4e72b8 RET

  (3081) 0x4e72bc LDR	X17, [SP, #136]

  (3081) 0x4e72c0 ADD	X18, X21, #8

  (3081) 0x4e72c4 ADD	X20, X21, #64

  (3081) 0x4e72c8 LDP	Q30, Q19, [X15]

  (3081) 0x4e72cc LDP	Q25, Q20, [X15, #32]

  (3081) 0x4e72d0 ADD	X15, X17, #72

  (3081) 0x4e72d4 LDP	Q31, Q16, [X18]

  (3081) 0x4e72d8 LDP	Q17, Q18, [X18, #32]

  (3081) 0x4e72dc B	4e6e14

(3078) 0x4e72e0 LDR	X1, [X19]

(3078) 0x4e72e4 MOVZ	X13, #1

(3078) 0x4e72e8 LDR	X3, [X21]

(3078) 0x4e72ec LDR	X24, [SP, #136]

(3078) 0x4e72f0 ADD	X5, X1, X3

(3078) 0x4e72f4 STR	X5, [X19]

(3078) 0x4e72f8 LDR	X7, [X14]

(3078) 0x4e72fc LDR	X11, [X24]

(3078) 0x4e7300 ADD	X0, X7, X11

(3078) 0x4e7304 STR	X0, [X14]

(3078) 0x4e7308 B	4e6bc8

(3078) 0x4e730c SUB	X18, X12, X4

(3078) 0x4e7310 ANDS	X15, X18, #4224

(3078) 0x4e7314 B.EQ	4e7414

(3078) 0x4e7318 CMP	X15, #1

(3078) 0x4e731c B.EQ	4e73f0

(3078) 0x4e7320 CMP	X15, #2

(3078) 0x4e7324 B.EQ	4e73d4

(3078) 0x4e7328 CMP	X15, #3

(3078) 0x4e732c B.EQ	4e73b8

(3078) 0x4e7330 CMP	X15, #4

(3078) 0x4e7334 B.EQ	4e739c

(3078) 0x4e7338 CMP	X15, #5

(3078) 0x4e733c B.EQ	4e7380

(3078) 0x4e7340 CMP	X15, #6

(3078) 0x4e7344 B.EQ	4e7364

(3078) 0x4e7348 LDR	X20, [X25, X4,LSL #3]

(3078) 0x4e734c ADD	X28, X20, X6

(3078) 0x4e7350 STR	X28, [X25, X4,LSL #3]

(3078) 0x4e7354 LDR	X2, [X17, X4,LSL #3]

(3078) 0x4e7358 ADD	X23, X2, X7

(3078) 0x4e735c STR	X23, [X17, X4,LSL #3]

(3078) 0x4e7360 ADD	X4, X4, #1

(3078) 0x4e7364 LDR	X27, [X25, X4,LSL #3]

(3078) 0x4e7368 ADD	X26, X27, X6

(3078) 0x4e736c STR	X26, [X25, X4,LSL #3]

(3078) 0x4e7370 LDR	X22, [X17, X4,LSL #3]

(3078) 0x4e7374 ADD	X8, X22, X7

(3078) 0x4e7378 STR	X8, [X17, X4,LSL #3]

(3078) 0x4e737c ADD	X4, X4, #1

(3078) 0x4e7380 LDR	X10, [X25, X4,LSL #3]

(3078) 0x4e7384 ADD	X1, X10, X6

(3078) 0x4e7388 STR	X1, [X25, X4,LSL #3]

(3078) 0x4e738c LDR	X19, [X17, X4,LSL #3]

(3078) 0x4e7390 ADD	X14, X19, X7

(3078) 0x4e7394 STR	X14, [X17, X4,LSL #3]

(3078) 0x4e7398 ADD	X4, X4, #1

(3078) 0x4e739c LDR	X21, [X25, X4,LSL #3]

(3078) 0x4e73a0 ADD	X5, X21, X6

(3078) 0x4e73a4 STR	X5, [X25, X4,LSL #3]

(3078) 0x4e73a8 LDR	X9, [X17, X4,LSL #3]

(3078) 0x4e73ac ADD	X24, X9, X7

(3078) 0x4e73b0 STR	X24, [X17, X4,LSL #3]

(3078) 0x4e73b4 ADD	X4, X4, #1

(3078) 0x4e73b8 LDR	X3, [X25, X4,LSL #3]

(3078) 0x4e73bc ADD	X13, X3, X6

(3078) 0x4e73c0 STR	X13, [X25, X4,LSL #3]

(3078) 0x4e73c4 LDR	X11, [X17, X4,LSL #3]

(3078) 0x4e73c8 ADD	X30, X11, X7

(3078) 0x4e73cc STR	X30, [X17, X4,LSL #3]

(3078) 0x4e73d0 ADD	X4, X4, #1

(3078) 0x4e73d4 LDR	X16, [X25, X4,LSL #3]

(3078) 0x4e73d8 ADD	X0, X16, X6

(3078) 0x4e73dc STR	X0, [X25, X4,LSL #3]

(3078) 0x4e73e0 LDR	X18, [X17, X4,LSL #3]

(3078) 0x4e73e4 ADD	X15, X18, X7

(3078) 0x4e73e8 STR	X15, [X17, X4,LSL #3]

(3078) 0x4e73ec ADD	X4, X4, #1

(3078) 0x4e73f0 LDR	X20, [X25, X4,LSL #3]

(3078) 0x4e73f4 ADD	X28, X20, X6

(3078) 0x4e73f8 STR	X28, [X25, X4,LSL #3]

(3078) 0x4e73fc LDR	X2, [X17, X4,LSL #3]

(3078) 0x4e7400 ADD	X23, X2, X7

(3078) 0x4e7404 STR	X23, [X17, X4,LSL #3]

(3078) 0x4e7408 ADD	X4, X4, #1

(3078) 0x4e740c CMP	X12, X4

(3078) 0x4e7410 B.EQ	4e6cc4

  (3079) 0x4e7414 LDR	X27, [X25, X4,LSL #3]

  (3079) 0x4e7418 ADD	X26, X4, #1

  (3079) 0x4e741c ADD	X10, X4, #2

  (3079) 0x4e7420 ADD	X22, X4, #3

  (3079) 0x4e7424 ADD	X1, X4, #4

  (3079) 0x4e7428 ADD	X8, X4, #5

  (3079) 0x4e742c ADD	X19, X4, #6

  (3079) 0x4e7430 ADD	X14, X4, #7

  (3079) 0x4e7434 ADD	X21, X27, X6

  (3079) 0x4e7438 STR	X21, [X25, X4,LSL #3]

  (3079) 0x4e743c LDR	X5, [X17, X4,LSL #3]

  (3079) 0x4e7440 ADD	X9, X5, X7

  (3079) 0x4e7444 STR	X9, [X17, X4,LSL #3]

  (3079) 0x4e7448 ADD	X4, X4, #8

  (3079) 0x4e744c LDR	X24, [X25, X26,LSL #3]

  (3079) 0x4e7450 ADD	X3, X24, X6

  (3079) 0x4e7454 STR	X3, [X25, X26,LSL #3]

  (3079) 0x4e7458 LDR	X13, [X17, X26,LSL #3]

  (3079) 0x4e745c ADD	X11, X13, X7

  (3079) 0x4e7460 STR	X11, [X17, X26,LSL #3]

  (3079) 0x4e7464 LDR	X30, [X25, X10,LSL #3]

  (3079) 0x4e7468 ADD	X16, X30, X6

  (3079) 0x4e746c STR	X16, [X25, X10,LSL #3]

  (3079) 0x4e7470 LDR	X0, [X17, X10,LSL #3]

  (3079) 0x4e7474 ADD	X18, X0, X7

  (3079) 0x4e7478 STR	X18, [X17, X10,LSL #3]

  (3079) 0x4e747c LDR	X15, [X25, X22,LSL #3]

  (3079) 0x4e7480 ADD	X20, X15, X6

  (3079) 0x4e7484 STR	X20, [X25, X22,LSL #3]

  (3079) 0x4e7488 LDR	X28, [X17, X22,LSL #3]

  (3079) 0x4e748c ADD	X2, X28, X7

  (3079) 0x4e7490 STR	X2, [X17, X22,LSL #3]

  (3079) 0x4e7494 LDR	X23, [X25, X1,LSL #3]

  (3079) 0x4e7498 ADD	X27, X23, X6

  (3079) 0x4e749c STR	X27, [X25, X1,LSL #3]

  (3079) 0x4e74a0 LDR	X26, [X17, X1,LSL #3]

  (3079) 0x4e74a4 ADD	X22, X26, X7

  (3079) 0x4e74a8 STR	X22, [X17, X1,LSL #3]

  (3079) 0x4e74ac LDR	X10, [X25, X8,LSL #3]

  (3079) 0x4e74b0 ADD	X1, X10, X6

  (3079) 0x4e74b4 STR	X1, [X25, X8,LSL #3]

  (3079) 0x4e74b8 LDR	X21, [X17, X8,LSL #3]

  (3079) 0x4e74bc ADD	X5, X21, X7

  (3079) 0x4e74c0 STR	X5, [X17, X8,LSL #3]

  (3079) 0x4e74c4 LDR	X8, [X25, X19,LSL #3]

  (3079) 0x4e74c8 ADD	X9, X8, X6

  (3079) 0x4e74cc STR	X9, [X25, X19,LSL #3]

  (3079) 0x4e74d0 LDR	X24, [X17, X19,LSL #3]

  (3079) 0x4e74d4 ADD	X3, X24, X7

  (3079) 0x4e74d8 STR	X3, [X17, X19,LSL #3]

  (3079) 0x4e74dc LDR	X19, [X25, X14,LSL #3]

  (3079) 0x4e74e0 ADD	X13, X19, X6

  (3079) 0x4e74e4 STR	X13, [X25, X14,LSL #3]

  (3079) 0x4e74e8 LDR	X11, [X17, X14,LSL #3]

  (3079) 0x4e74ec ADD	X30, X11, X7

  (3079) 0x4e74f0 STR	X30, [X17, X14,LSL #3]

  (3079) 0x4e74f4 CMP	X12, X4

  (3079) 0x4e74f8 B.NE	4e7414

(3078) 0x4e74fc B	4e6cc4

  (3081) 0x4e7500 LDR	Q21, [X23]

  (3081) 0x4e7504 MOVZ	X21, #16

  (3081) 0x4e7508 ADD	V1.2D, V21.2D, V31.2D

  (3081) 0x4e750c STR	Q1, [X23]

  (3081) 0x4e7510 LDR	Q2, [X27]

  (3081) 0x4e7514 ADD	V26.2D, V2.2D, V30.2D

  (3081) 0x4e7518 STR	Q26, [X27]

  (3081) 0x4e751c B	4e70e0

(3078) 0x4e7520 MOVZ	X13, #0

(3078) 0x4e7524 B	4e6fdc

Coverage (%)	Name	Source Location	Module
►99.13+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_csr_matop.c:102-276
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:102-127,135-137,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-276.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 76% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 13.33 to 10.92 cycles (1.22x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.33 to 0.50 cycles (26.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 232 bytes.

General properties

nb instructions	52
loop length	208
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.92	1.75	1.83	1.83	1.83	1.83	0.00	0.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00
cycles	1.50	1.50	1.92	1.75	1.83	1.83	1.83	1.83	0.00	0.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Overall L1	13.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

22% of peak load performance is reached (21.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
36% of peak store performance is reached (17.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4e67c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #768]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X1, X2, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X2, X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X28, X6, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X3, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X27, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X21, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [X0, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X7, X25, [X0, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X4, [X0, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X12, [X0, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X11, [X0, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X22, X13, [X0, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X14, X18, [X0, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [X0, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X18, X14, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X0, X15, [X0, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X0, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X18, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X13, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X7, X2, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDP X9, X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X12, X2, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [SP, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4e6ce0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X0, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X17, X19, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X4, X0, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CBNZ X17, 4e6cf0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_csr_matop.c:102-276
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 13.33 to 0.50 cycles (26.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 232 bytes.

General properties

nb instructions	52
loop length	208
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.92	1.75	1.83	1.83	1.83	1.83	0.00	0.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00
cycles	1.50	1.50	1.92	1.75	1.83	1.83	1.83	1.83	0.00	0.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.50
Overall L1	13.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.33 cycles. At this rate:

22% of peak load performance is reached (21.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
36% of peak store performance is reached (17.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4e67c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #768]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X1, X2, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X2, X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X28, X6, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X3, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X27, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X21, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [X0, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X7, X25, [X0, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X7, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X4, [X0, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X12, [X0, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X11, [X0, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X22, X13, [X0, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X13, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X14, X18, [X0, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [X0, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X18, X14, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X0, X15, [X0, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X0, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X2, X18, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X13, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X7, X2, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDP X9, X10, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X12, X2, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [SP, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4e6ce0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X0, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X17, X19, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X4, X0, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X7, X16, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CBNZ X17, 4e6cf0 <hypre_ParMatmul_RowSizes._omp_fn.0+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul_RowSizes._omp_fn.0–	1.06	0.17
▼Loop 3078 - par_csr_matop.c:102-276 - exec–	0.00	0.00
▼Loop 3087 - par_csr_matop.c:127-242 - exec–	0.01	0.01
▼Loop 3091 - par_csr_matop.c:187-231 - exec–	0.38	0.05
○Loop 3094 - par_csr_matop.c:195-208 - exec	0.63	0.08
○Loop 3093 - par_csr_matop.c:218-231 - exec	0.00	0.00
○Loop 3092 - par_csr_matop.c:218-228 - exec	0.00	0.00
▼Loop 3086 - par_csr_matop.c:146-177 - exec–	0.00	0.00
○Loop 3088 - par_csr_matop.c:170-177 - exec	0.00	0.00
○Loop 3089 - par_csr_matop.c:154-167 - exec	0.00	0.00
▼Loop 3081 - par_csr_matop.c:102-266 - exec–	0.00	0.00
○Loop 3080 - par_csr_matop.c:263-266 - exec	0.03	0.00
○Loop 3083 - par_csr_matop.c:257-260 - exec	0.00	0.00
○Loop 3082 - par_csr_matop.c:257-260 - exec	0.00	0.00
▼Loop 3090 - par_csr_matop.c:136-146 - exec–	0.00	0.00
○Loop 3085 - par_csr_matop.c:146-146 - exec	0.00	0.00
○Loop 3084 - par_csr_matop.c:273-276 - exec	0.00	0.00
○Loop 3079 - par_csr_matop.c:263-266 - exec	0.00	0.00

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Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code