OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.1	Module: exec	Source: ams.c:3662-3682 [...]	Coverage (incl. loops): 51.87% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x4c8360 STP	X29, X30, [SP, #976]!

0x4c8364 ADD	X29, SP, #0

0x4c8368 STP	X19, X20, [SP, #16]

0x4c836c ORR	X19, XZR, X0

0x4c8370 STR	X21, [SP, #32]

0x4c8374 LDR	X21, [X0, #64]

0x4c8378 BL	410d60

0x4c837c SBFM	X20, X0, #0, #31

0x4c8380 BL	410c90

0x4c8384 SBFM	X1, X0, #0, #31

0x4c8388 SDIV	X7, X21, X20

0x4c838c MSUB	X0, X7, X20, X21

0x4c8390 CMP	X1, X0

0x4c8394 B.LT	4c84c0

(2651) 0x4c8398 MADD	X1, X7, X1, X0

(2651) 0x4c839c ADD	X30, X7, X1

(2651) 0x4c83a0 CMP	X1, X30

(2651) 0x4c83a4 B.GE	4c84b0

(2651) 0x4c83a8 LDP	X10, X11, [X19, #16]

(2651) 0x4c83ac CNTD	X4, ALL

(2651) 0x4c83b0 PTRUE	P6.B, ALL

(2651) 0x4c83b4 LDP	X21, X13, [X19, #32]

(2651) 0x4c83b8 ADD	X17, X11, #8

(2651) 0x4c83bc LDP	X18, X20, [X19, #48]

(2651) 0x4c83c0 ADD	X16, X13, #8

(2651) 0x4c83c4 LDP	X12, X14, [X19, #72]

(2651) 0x4c83c8 LDP	X8, X9, [X19, #88]

(2651) 0x4c83cc LDR	X15, [X19]

(2651) 0x4c83d0 LDR	D30, [X19, #8]

(2651) 0x4c83d4 LDR	D31, [X19, #104]

(2651) 0x4c83d8 B	4c83e8

  (2652) 0x4c83dc ADD	X1, X1, #1

  (2652) 0x4c83e0 CMP	X30, X1

  (2652) 0x4c83e4 B.EQ	4c84b0

  (2652) 0x4c83e8 LDR	X5, [X11, X1,LSL #3]

  (2652) 0x4c83ec UBFM	X3, X5, #61, #60

  (2652) 0x4c83f0 ADD	X6, X10, X5,LSL #3

  (2652) 0x4c83f4 LDR	D5, [X10, X3]

  (2652) 0x4c83f8 FCMP	D31, D5

  (2652) 0x4c83fc B.EQ	4c83dc

  (2652) 0x4c8400 LDR	X2, [X17, X1,LSL #3]

  (2652) 0x4c8404 LDR	D0, [X14, X1,LSL #3]

  (2652) 0x4c8408 CMP	X5, X2

  (2652) 0x4c840c B.GE	4c8444

  (2652) 0x4c8410 MOVZ	X0, #0

  (2652) 0x4c8414 ADD	X19, X21, X3

  (2652) 0x4c8418 SUB	X7, X2, X5

  (2652) 0x4c841c WHILELO	P7.D, XZR, X7

    (2654) 0x4c8420 LD1D	{Z4.D}, P7/Z, [X19, X0,LSL #3]

    (2654) 0x4c8424 LD1D	{Z2.D}, P7/Z, [X6, X0,LSL #3]

    (2654) 0x4c8428 LD1D	{Z3.D}, P7/Z, [X8, Z4.D,LSL #3]

    (2654) 0x4c842c ADD	X0, X0, X4

    (2654) 0x4c8430 FMUL	Z2.D, P7/M, Z2.D, Z3.D

    (2654) 0x4c8434 FNEG	Z2.D, P6/M, Z2.D

    (2654) 0x4c8438 FADDA	D0, P7, D0, Z2.D

    (2654) 0x4c843c WHILELO	P7.D, X0, X7

    (2654) 0x4c8440 B.NE	4c8420

  (2652) 0x4c8444 LDR	X3, [X13, X1,LSL #3]

  (2652) 0x4c8448 LDR	X6, [X16, X1,LSL #3]

  (2652) 0x4c844c CMP	X3, X6

  (2652) 0x4c8450 B.GE	4c848c

  (2652) 0x4c8454 ADD	X5, X20, X3,LSL #3

  (2652) 0x4c8458 MOVZ	X7, #0

  (2652) 0x4c845c SUB	X2, X6, X3

  (2652) 0x4c8460 WHILELO	P0.D, XZR, X2

  (2652) 0x4c8464 ADD	X19, X18, X3,LSL #3

    (2653) 0x4c8468 LD1D	{Z27.D}, P0/Z, [X5, X7,LSL #3]

    (2653) 0x4c846c LD1D	{Z1.D}, P0/Z, [X19, X7,LSL #3]

    (2653) 0x4c8470 LD1D	{Z26.D}, P0/Z, [X9, Z27.D,LSL #3]

    (2653) 0x4c8474 ADD	X7, X7, X4

    (2653) 0x4c8478 FMUL	Z1.D, P0/M, Z1.D, Z26.D

    (2653) 0x4c847c FNEG	Z1.D, P6/M, Z1.D

    (2653) 0x4c8480 FADDA	D0, P0, D0, Z1.D

    (2653) 0x4c8484 WHILELO	P0.D, X7, X2

    (2653) 0x4c8488 B.NE	4c8468

  (2652) 0x4c848c LDR	D29, [X15, X1,LSL #3]

  (2652) 0x4c8490 FMUL	D6, D30, D0

  (2652) 0x4c8494 LDR	D28, [X12, X1,LSL #3]

  (2652) 0x4c8498 FDIV	D7, D6, D29

  (2652) 0x4c849c FADD	D16, D28, D7

  (2652) 0x4c84a0 STR	D16, [X12, X1,LSL #3]

  (2652) 0x4c84a4 ADD	X1, X1, #1

  (2652) 0x4c84a8 CMP	X30, X1

  (2652) 0x4c84ac B.NE	4c83e8

(2651) 0x4c84b0 LDR	X21, [SP, #32]

(2651) 0x4c84b4 LDP	X19, X20, [SP, #16]

(2651) 0x4c84b8 LDP	X29, X30, [SP], #48

(2651) 0x4c84bc RET

(2651) 0x4c84c0 ADD	X7, X7, #1

(2651) 0x4c84c4 MOVZ	X0, #0

(2651) 0x4c84c8 B	4c8398

Coverage (%)	Name	Source Location	Module
►99.02+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c8360

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X7, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X0, X7, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4c84c0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c8360

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X20, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
SDIV X7, X21, X20	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X0, X7, X20, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.LT 4c84c0 <hypre_ParCSRRelaxThreads._omp_fn.1+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.1–	51.87	8.31
▼Loop 2651 - ams.c:3662-3682 - exec–	0.00	0.00
▼Loop 2652 - ams.c:3662-3682 - exec–	1.73	0.21
○Loop 2654 - ams.c:3672-3675 - exec	50.14	6.23
○Loop 2653 - ams.c:3677-3680 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code