OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.0	Module: exec	Source: ams.c:3655-3659	Coverage (incl. loops): 1.71% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3655 - 3659

--------------------------------------------------------------------------------

3655: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

3656: #endif

3657:       for (i = 0; i < n; i++)

3658:       {

3659:          Vtemp_data[i] = u_data[i];

0x4c7fc8 STP	X29, X30, [SP, #976]!

0x4c7fcc ADD	X29, SP, #0

0x4c7fd0 STP	X19, X20, [SP, #16]

0x4c7fd4 ORR	X20, XZR, X0

0x4c7fd8 STR	X21, [SP, #32]

0x4c7fdc LDR	X21, [X0]

0x4c7fe0 BL	410d60

0x4c7fe4 SBFM	X19, X0, #0, #31

0x4c7fe8 BL	410c90

0x4c7fec SBFM	X1, X0, #0, #31

0x4c7ff0 SDIV	X4, X21, X19

0x4c7ff4 MSUB	X2, X4, X19, X21

0x4c7ff8 CMP	X1, X2

0x4c7ffc B.LT	4c820c

(2648) 0x4c8000 MADD	X1, X4, X1, X2

(2648) 0x4c8004 ADD	X5, X4, X1

(2648) 0x4c8008 CMP	X1, X5

(2648) 0x4c800c B.GE	4c81fc

(2648) 0x4c8010 LDP	X9, X8, [X20, #8]

(2648) 0x4c8014 CMP	X4, #1

(2648) 0x4c8018 B.EQ	4c8230

(2648) 0x4c801c UBFM	X6, X1, #61, #60

(2648) 0x4c8020 ADD	X3, X8, X1,LSL #3

(2648) 0x4c8024 ADD	X0, X6, #8

(2648) 0x4c8028 ADD	X7, X9, X0

(2648) 0x4c802c SUB	X10, X3, X7

(2648) 0x4c8030 CMP	X10, #16

(2648) 0x4c8034 B.LS	4c8230

(2648) 0x4c8038 SUB	X11, X4, #1

(2648) 0x4c803c CMP	X11, #2

(2648) 0x4c8040 B.LS	4c834c

(2648) 0x4c8044 UBFM	X13, X4, #2, #63

(2648) 0x4c8048 ADD	X17, X9, X6

(2648) 0x4c804c UBFM	X18, X13, #59, #58

(2648) 0x4c8050 MOVZ	X19, #0

(2648) 0x4c8054 SUB	X14, X18, #32

(2648) 0x4c8058 ADD	X30, X17, #16

(2648) 0x4c805c UBFM	X15, X14, #5, #63

(2648) 0x4c8060 ADD	X20, X3, #16

(2648) 0x4c8064 ADD	X16, X15, #1

(2648) 0x4c8068 ANDS	X21, X16, #4224

(2648) 0x4c806c B.EQ	4c8120

(2648) 0x4c8070 CMP	X21, #1

(2648) 0x4c8074 B.EQ	4c8104

(2648) 0x4c8078 CMP	X21, #2

(2648) 0x4c807c B.EQ	4c80f0

(2648) 0x4c8080 CMP	X21, #3

(2648) 0x4c8084 B.EQ	4c80dc

(2648) 0x4c8088 CMP	X21, #4

(2648) 0x4c808c B.EQ	4c80c8

(2648) 0x4c8090 CMP	X21, #5

(2648) 0x4c8094 B.EQ	4c80b4

(2648) 0x4c8098 CMP	X21, #6

(2648) 0x4c809c B.NE	4c8334

(2648) 0x4c80a0 LDR	Q1, [X17, X19]

(2648) 0x4c80a4 LDR	Q0, [X30, X19]

(2648) 0x4c80a8 STR	Q1, [X3, X19]

(2648) 0x4c80ac STR	Q0, [X20, X19]

(2648) 0x4c80b0 ADD	X19, X19, #32

(2648) 0x4c80b4 LDR	Q3, [X17, X19]

(2648) 0x4c80b8 LDR	Q2, [X30, X19]

(2648) 0x4c80bc STR	Q3, [X3, X19]

(2648) 0x4c80c0 STR	Q2, [X20, X19]

(2648) 0x4c80c4 ADD	X19, X19, #32

(2648) 0x4c80c8 LDR	Q5, [X17, X19]

(2648) 0x4c80cc LDR	Q4, [X30, X19]

(2648) 0x4c80d0 STR	Q5, [X3, X19]

(2648) 0x4c80d4 STR	Q4, [X20, X19]

(2648) 0x4c80d8 ADD	X19, X19, #32

(2648) 0x4c80dc LDR	Q7, [X17, X19]

(2648) 0x4c80e0 LDR	Q6, [X30, X19]

(2648) 0x4c80e4 STR	Q7, [X3, X19]

(2648) 0x4c80e8 STR	Q6, [X20, X19]

(2648) 0x4c80ec ADD	X19, X19, #32

(2648) 0x4c80f0 LDR	Q17, [X17, X19]

(2648) 0x4c80f4 LDR	Q16, [X30, X19]

(2648) 0x4c80f8 STR	Q17, [X3, X19]

(2648) 0x4c80fc STR	Q16, [X20, X19]

(2648) 0x4c8100 ADD	X19, X19, #32

(2648) 0x4c8104 LDR	Q19, [X17, X19]

(2648) 0x4c8108 LDR	Q18, [X30, X19]

(2648) 0x4c810c STR	Q19, [X3, X19]

(2648) 0x4c8110 STR	Q18, [X20, X19]

(2648) 0x4c8114 ADD	X19, X19, #32

(2648) 0x4c8118 CMP	X19, X18

(2648) 0x4c811c B.EQ	4c81c8

  (2650) 0x4c8120 LDR	Q21, [X17, X19]

  (2650) 0x4c8124 ADD	X2, X19, #32

  (2650) 0x4c8128 ADD	X6, X19, #64

  (2650) 0x4c812c ADD	X5, X19, #96

  (2650) 0x4c8130 ADD	X0, X19, #128

  (2650) 0x4c8134 LDR	Q20, [X30, X19]

  (2650) 0x4c8138 ADD	X7, X19, #160

  (2650) 0x4c813c ADD	X10, X19, #192

  (2650) 0x4c8140 ADD	X11, X19, #224

  (2650) 0x4c8144 STR	Q21, [X3, X19]

  (2650) 0x4c8148 STR	Q20, [X20, X19]

  (2650) 0x4c814c ADD	X19, X19, #256

  (2650) 0x4c8150 LDR	Q23, [X17, X2]

  (2650) 0x4c8154 LDR	Q22, [X30, X2]

  (2650) 0x4c8158 STR	Q23, [X3, X2]

  (2650) 0x4c815c STR	Q22, [X20, X2]

  (2650) 0x4c8160 LDR	Q25, [X17, X6]

  (2650) 0x4c8164 LDR	Q24, [X30, X6]

  (2650) 0x4c8168 STR	Q25, [X3, X6]

  (2650) 0x4c816c STR	Q24, [X20, X6]

  (2650) 0x4c8170 LDR	Q27, [X17, X5]

  (2650) 0x4c8174 LDR	Q26, [X30, X5]

  (2650) 0x4c8178 STR	Q27, [X3, X5]

  (2650) 0x4c817c STR	Q26, [X20, X5]

  (2650) 0x4c8180 LDR	Q29, [X17, X0]

  (2650) 0x4c8184 LDR	Q28, [X30, X0]

  (2650) 0x4c8188 STR	Q29, [X3, X0]

  (2650) 0x4c818c STR	Q28, [X20, X0]

  (2650) 0x4c8190 LDR	Q30, [X17, X7]

  (2650) 0x4c8194 LDR	Q31, [X30, X7]

  (2650) 0x4c8198 STR	Q30, [X3, X7]

  (2650) 0x4c819c STR	Q31, [X20, X7]

  (2650) 0x4c81a0 LDR	Q1, [X17, X10]

  (2650) 0x4c81a4 LDR	Q0, [X30, X10]

  (2650) 0x4c81a8 STR	Q1, [X3, X10]

  (2650) 0x4c81ac STR	Q0, [X20, X10]

  (2650) 0x4c81b0 LDR	Q3, [X17, X11]

  (2650) 0x4c81b4 LDR	Q2, [X30, X11]

  (2650) 0x4c81b8 STR	Q3, [X3, X11]

  (2650) 0x4c81bc STR	Q2, [X20, X11]

  (2650) 0x4c81c0 CMP	X19, X18

  (2650) 0x4c81c4 B.NE	4c8120

(2648) 0x4c81c8 AND	X12, X4, #8062

(2648) 0x4c81cc CMP	X4, X12

(2648) 0x4c81d0 B.EQ	4c81fc

(2648) 0x4c81d4 ADD	X1, X1, X12

(2648) 0x4c81d8 SUB	X4, X4, X12

(2648) 0x4c81dc WHILELO	P7.D, XZR, X4

(2648) 0x4c81e0 LD1D	{Z4.D}, P7/Z, [X9, X1,LSL #3]

(2648) 0x4c81e4 ADD	X8, X8, X1,LSL #3

(2648) 0x4c81e8 ST1D	{Z4.D}, P7, [X8, MUL VL]

(2648) 0x4c81ec CNTD	X3, ALL

(2648) 0x4c81f0 WHILELO	P0.D, X3, X4

(2648) 0x4c81f4 ADD	X9, X9, X1,LSL #3

(2648) 0x4c81f8 B.NE	4c8218

(2648) 0x4c81fc LDR	X21, [SP, #32]

(2648) 0x4c8200 LDP	X19, X20, [SP, #16]

(2648) 0x4c8204 LDP	X29, X30, [SP], #48

(2648) 0x4c8208 RET

(2648) 0x4c820c ADD	X4, X4, #1

(2648) 0x4c8210 MOVZ	X2, #0

(2648) 0x4c8214 B	4c8000

(2648) 0x4c8218 LDR	X21, [SP, #32]

(2648) 0x4c821c LD1D	{Z5.D}, P0/Z, [X9, #1, MUL VL]

(2648) 0x4c8220 ST1D	{Z5.D}, P0, [X8, #1, MUL VL]

(2648) 0x4c8224 LDP	X19, X20, [SP, #16]

(2648) 0x4c8228 LDP	X29, X30, [SP], #48

(2648) 0x4c822c RET

(2648) 0x4c8230 SUB	X12, X5, X1

(2648) 0x4c8234 ANDS	X13, X12, #4224

(2648) 0x4c8238 B.EQ	4c82c8

(2648) 0x4c823c CMP	X13, #1

(2648) 0x4c8240 B.EQ	4c82b4

(2648) 0x4c8244 CMP	X13, #2

(2648) 0x4c8248 B.EQ	4c82a8

(2648) 0x4c824c CMP	X13, #3

(2648) 0x4c8250 B.EQ	4c829c

(2648) 0x4c8254 CMP	X13, #4

(2648) 0x4c8258 B.EQ	4c8290

(2648) 0x4c825c CMP	X13, #5

(2648) 0x4c8260 B.EQ	4c8284

(2648) 0x4c8264 CMP	X13, #6

(2648) 0x4c8268 B.EQ	4c8278

(2648) 0x4c826c LDR	D6, [X9, X1,LSL #3]

(2648) 0x4c8270 STR	D6, [X8, X1,LSL #3]

(2648) 0x4c8274 ADD	X1, X1, #1

(2648) 0x4c8278 LDR	D7, [X9, X1,LSL #3]

(2648) 0x4c827c STR	D7, [X8, X1,LSL #3]

(2648) 0x4c8280 ADD	X1, X1, #1

(2648) 0x4c8284 LDR	D16, [X9, X1,LSL #3]

(2648) 0x4c8288 STR	D16, [X8, X1,LSL #3]

(2648) 0x4c828c ADD	X1, X1, #1

(2648) 0x4c8290 LDR	D17, [X9, X1,LSL #3]

(2648) 0x4c8294 STR	D17, [X8, X1,LSL #3]

(2648) 0x4c8298 ADD	X1, X1, #1

(2648) 0x4c829c LDR	D18, [X9, X1,LSL #3]

(2648) 0x4c82a0 STR	D18, [X8, X1,LSL #3]

(2648) 0x4c82a4 ADD	X1, X1, #1

(2648) 0x4c82a8 LDR	D19, [X9, X1,LSL #3]

(2648) 0x4c82ac STR	D19, [X8, X1,LSL #3]

(2648) 0x4c82b0 ADD	X1, X1, #1

(2648) 0x4c82b4 LDR	D20, [X9, X1,LSL #3]

(2648) 0x4c82b8 STR	D20, [X8, X1,LSL #3]

(2648) 0x4c82bc ADD	X1, X1, #1

(2648) 0x4c82c0 CMP	X5, X1

(2648) 0x4c82c4 B.EQ	4c81fc

  (2649) 0x4c82c8 LDR	D21, [X9, X1,LSL #3]

  (2649) 0x4c82cc ADD	X17, X1, #1

  (2649) 0x4c82d0 ADD	X30, X1, #2

  (2649) 0x4c82d4 ADD	X18, X1, #3

  (2649) 0x4c82d8 ADD	X14, X1, #4

  (2649) 0x4c82dc ADD	X20, X1, #5

  (2649) 0x4c82e0 ADD	X15, X1, #6

  (2649) 0x4c82e4 ADD	X16, X1, #7

  (2649) 0x4c82e8 STR	D21, [X8, X1,LSL #3]

  (2649) 0x4c82ec ADD	X1, X1, #8

  (2649) 0x4c82f0 LDR	D22, [X9, X17,LSL #3]

  (2649) 0x4c82f4 STR	D22, [X8, X17,LSL #3]

  (2649) 0x4c82f8 LDR	D23, [X9, X30,LSL #3]

  (2649) 0x4c82fc STR	D23, [X8, X30,LSL #3]

  (2649) 0x4c8300 LDR	D24, [X9, X18,LSL #3]

  (2649) 0x4c8304 STR	D24, [X8, X18,LSL #3]

  (2649) 0x4c8308 LDR	D25, [X9, X14,LSL #3]

  (2649) 0x4c830c STR	D25, [X8, X14,LSL #3]

  (2649) 0x4c8310 LDR	D26, [X9, X20,LSL #3]

  (2649) 0x4c8314 STR	D26, [X8, X20,LSL #3]

  (2649) 0x4c8318 LDR	D27, [X9, X15,LSL #3]

  (2649) 0x4c831c STR	D27, [X8, X15,LSL #3]

  (2649) 0x4c8320 LDR	D28, [X9, X16,LSL #3]

  (2649) 0x4c8324 STR	D28, [X8, X16,LSL #3]

  (2649) 0x4c8328 CMP	X5, X1

  (2649) 0x4c832c B.NE	4c82c8

(2648) 0x4c8330 B	4c81fc

(2648) 0x4c8334 LDR	Q30, [X17]

(2648) 0x4c8338 MOVZ	X19, #32

(2648) 0x4c833c LDR	Q31, [X30]

(2648) 0x4c8340 STR	Q30, [X3]

(2648) 0x4c8344 STR	Q31, [X20]

(2648) 0x4c8348 B	4c80a0

(2648) 0x4c834c MOVZ	X12, #0

(2648) 0x4c8350 B	4c81d4

0x4c8354 HINT	#0

0x4c8358 HINT	#0

0x4c835c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.92+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.03+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	hypre_ParCSRRelaxThreads	ams.c:3662	exec
○	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ams.c:3655-3659
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3655-3659.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 68% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c7fc8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X4, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X4, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4c820c <hypre_ParCSRRelaxThreads._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	ams.c:3655-3659
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3655-3659.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4c7fc8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X1, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X4, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X4, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X1, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4c820c <hypre_ParCSRRelaxThreads._omp_fn.0+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.0–	1.71	0.27
▼Loop 2648 - ams.c:3655-3659 - exec–	0.00	0.00
○Loop 2650 - ams.c:3659-3659 - exec	1.70	0.21
○Loop 2649 - ams.c:3659-3659 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code