OV - exec - Function hypre_BoomerAMGCreate2ndS._omp

	Function: hypre_BoomerAMGCreate2ndS._omp_fn.0	Module: exec	Source: par_strength.c:1253-1278	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

--------------------------------------------------------------------------------

1253: #pragma omp parallel private(i)

1254: #endif

1255:    {

1256:       HYPRE_Int num_coarse_private = 0;

1257:

1258:       HYPRE_Int i_begin, i_end;

1259:       hypre_GetSimpleThreadPartition(&i_begin, &i_end, num_cols_diag_S);

1260:

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

0x4b5ce0 STP	X29, X30, [SP, #928]!

0x4b5ce4 ADD	X29, SP, #0

0x4b5ce8 ADD	X1, SP, #88

0x4b5cec STP	X21, X22, [SP, #32]

0x4b5cf0 ORR	X22, XZR, X0

0x4b5cf4 ADD	X0, SP, #80

0x4b5cf8 STP	X19, X20, [SP, #16]

0x4b5cfc LDR	X21, [X22, #16]

0x4b5d00 STR	X23, [SP, #48]

0x4b5d04 STR	XZR, [SP, #72]

0x4b5d08 LDP	X19, X2, [X22]

0x4b5d0c LDP	X20, X23, [X22, #32]

0x4b5d10 BL	52df80

0x4b5d14 LDP	X1, X4, [SP, #80]

0x4b5d18 CMP	X1, X4

0x4b5d1c B.GE	4b5ee0

0x4b5d20 ADD	X18, X19, X1,LSL #3

0x4b5d24 MOVZ	W0, #0

0x4b5d28 ADD	X5, X19, X4,LSL #3

0x4b5d2c SUB	X3, X5, X18

0x4b5d30 SUB	X2, X3, #8

0x4b5d34 UBFM	X6, X2, #3, #63

0x4b5d38 LDR	X2, [SP, #72]

0x4b5d3c ADD	X7, X6, #1

0x4b5d40 ANDS	X8, X7, #4224

0x4b5d44 B.EQ	4b5e28

0x4b5d48 CMP	X8, #1

0x4b5d4c B.EQ	4b5e08

0x4b5d50 CMP	X8, #2

0x4b5d54 B.EQ	4b5df0

0x4b5d58 CMP	X8, #3

0x4b5d5c B.EQ	4b5dd8

0x4b5d60 CMP	X8, #4

0x4b5d64 B.EQ	4b5dc0

0x4b5d68 CMP	X8, #5

0x4b5d6c B.EQ	4b5da8

0x4b5d70 CMP	X8, #6

0x4b5d74 B.EQ	4b5d90

0x4b5d78 LDR	X9, [X18]

0x4b5d7c CMP	X9, #0

0x4b5d80 B.LE	4b5d8c

0x4b5d84 ADD	X2, X2, #1

0x4b5d88 MOVZ	W0, #1

0x4b5d8c ADD	X18, X18, #8

0x4b5d90 LDR	X10, [X18]

0x4b5d94 CMP	X10, #0

0x4b5d98 B.LE	4b5da4

0x4b5d9c ADD	X2, X2, #1

0x4b5da0 MOVZ	W0, #1

0x4b5da4 ADD	X18, X18, #8

0x4b5da8 LDR	X11, [X18]

0x4b5dac CMP	X11, #0

0x4b5db0 B.LE	4b5dbc

0x4b5db4 ADD	X2, X2, #1

0x4b5db8 MOVZ	W0, #1

0x4b5dbc ADD	X18, X18, #8

0x4b5dc0 LDR	X12, [X18]

0x4b5dc4 CMP	X12, #0

0x4b5dc8 B.LE	4b5dd4

0x4b5dcc ADD	X2, X2, #1

0x4b5dd0 MOVZ	W0, #1

0x4b5dd4 ADD	X18, X18, #8

0x4b5dd8 LDR	X13, [X18]

0x4b5ddc CMP	X13, #0

0x4b5de0 B.LE	4b5dec

0x4b5de4 ADD	X2, X2, #1

0x4b5de8 MOVZ	W0, #1

0x4b5dec ADD	X18, X18, #8

0x4b5df0 LDR	X14, [X18]

0x4b5df4 CMP	X14, #0

0x4b5df8 B.LE	4b5e04

0x4b5dfc ADD	X2, X2, #1

0x4b5e00 MOVZ	W0, #1

0x4b5e04 ADD	X18, X18, #8

0x4b5e08 LDR	X15, [X18]

0x4b5e0c CMP	X15, #0

0x4b5e10 B.LE	4b5e1c

0x4b5e14 ADD	X2, X2, #1

0x4b5e18 MOVZ	W0, #1

0x4b5e1c ADD	X18, X18, #8

0x4b5e20 CMP	X18, X5

0x4b5e24 B.EQ	4b5ed8

(2406) 0x4b5e28 LDR	X16, [X18]

(2406) 0x4b5e2c CMP	X16, #0

(2406) 0x4b5e30 B.LE	4b5e3c

(2406) 0x4b5e34 ADD	X2, X2, #1

(2406) 0x4b5e38 MOVZ	W0, #1

(2406) 0x4b5e3c LDR	X17, [X18, #8]

(2406) 0x4b5e40 ADD	X18, X18, #8

(2406) 0x4b5e44 CMP	X17, #0

(2406) 0x4b5e48 B.LE	4b5e54

(2406) 0x4b5e4c ADD	X2, X2, #1

(2406) 0x4b5e50 MOVZ	W0, #1

(2406) 0x4b5e54 LDR	X30, [X18, #8]

(2406) 0x4b5e58 CMP	X30, #0

(2406) 0x4b5e5c B.LE	4b5e68

(2406) 0x4b5e60 ADD	X2, X2, #1

(2406) 0x4b5e64 MOVZ	W0, #1

(2406) 0x4b5e68 LDR	X1, [X18, #16]

(2406) 0x4b5e6c CMP	X1, #0

(2406) 0x4b5e70 B.LE	4b5e7c

(2406) 0x4b5e74 ADD	X2, X2, #1

(2406) 0x4b5e78 MOVZ	W0, #1

(2406) 0x4b5e7c LDR	X4, [X18, #24]

(2406) 0x4b5e80 CMP	X4, #0

(2406) 0x4b5e84 B.LE	4b5e90

(2406) 0x4b5e88 ADD	X2, X2, #1

(2406) 0x4b5e8c MOVZ	W0, #1

(2406) 0x4b5e90 LDR	X3, [X18, #32]

(2406) 0x4b5e94 CMP	X3, #0

(2406) 0x4b5e98 B.LE	4b5ea4

(2406) 0x4b5e9c ADD	X2, X2, #1

(2406) 0x4b5ea0 MOVZ	W0, #1

(2406) 0x4b5ea4 LDR	X6, [X18, #40]

(2406) 0x4b5ea8 CMP	X6, #0

(2406) 0x4b5eac B.LE	4b5eb8

(2406) 0x4b5eb0 ADD	X2, X2, #1

(2406) 0x4b5eb4 MOVZ	W0, #1

(2406) 0x4b5eb8 LDR	X7, [X18, #48]

(2406) 0x4b5ebc CMP	X7, #0

(2406) 0x4b5ec0 B.LE	4b5ecc

(2406) 0x4b5ec4 ADD	X2, X2, #1

(2406) 0x4b5ec8 MOVZ	W0, #1

(2406) 0x4b5ecc ADD	X18, X18, #56

(2406) 0x4b5ed0 CMP	X18, X5

(2406) 0x4b5ed4 B.NE	4b5e28

0x4b5ed8 CBZ	W0, 4b5ee0

0x4b5edc STR	X2, [SP, #72]

0x4b5ee0 LDR	X1, [X22, #24]

0x4b5ee4 ORR	X2, XZR, X20

0x4b5ee8 ADD	X0, SP, #72

0x4b5eec BL	52ef20

0x4b5ef0 LDP	X4, X8, [SP, #80]

0x4b5ef4 CMP	X4, X8

0x4b5ef8 B.GE	4b600c

0x4b5efc SUB	X5, X8, X4

0x4b5f00 LDR	X1, [SP, #72]

0x4b5f04 MOVN	X9, #0

0x4b5f08 ANDS	X10, X5, #4224

0x4b5f0c B.EQ	4b60fc

0x4b5f10 CMP	X10, #1

0x4b5f14 B.EQ	4b5fe8

0x4b5f18 CMP	X10, #2

0x4b5f1c B.EQ	4b5fcc

0x4b5f20 CMP	X10, #3

0x4b5f24 B.EQ	4b5fb0

0x4b5f28 CMP	X10, #4

0x4b5f2c B.EQ	4b5f94

0x4b5f30 CMP	X10, #5

0x4b5f34 B.EQ	4b5f78

0x4b5f38 CMP	X10, #6

0x4b5f3c B.EQ	4b5f5c

0x4b5f40 LDR	X11, [X19, X4,LSL #3]

0x4b5f44 CMP	X11, #0

0x4b5f48 B.LE	4b61e0

0x4b5f4c STR	X1, [X21, X4,LSL #3]

0x4b5f50 STR	X4, [X23, X1,LSL #3]

0x4b5f54 ADD	X1, X1, #1

0x4b5f58 ADD	X4, X4, #1

0x4b5f5c LDR	X12, [X19, X4,LSL #3]

0x4b5f60 CMP	X12, #0

0x4b5f64 B.LE	4b61c8

0x4b5f68 STR	X1, [X21, X4,LSL #3]

0x4b5f6c STR	X4, [X23, X1,LSL #3]

0x4b5f70 ADD	X1, X1, #1

0x4b5f74 ADD	X4, X4, #1

0x4b5f78 LDR	X13, [X19, X4,LSL #3]

0x4b5f7c CMP	X13, #0

0x4b5f80 B.LE	4b61bc

0x4b5f84 STR	X1, [X21, X4,LSL #3]

0x4b5f88 STR	X4, [X23, X1,LSL #3]

0x4b5f8c ADD	X1, X1, #1

0x4b5f90 ADD	X4, X4, #1

0x4b5f94 LDR	X14, [X19, X4,LSL #3]

0x4b5f98 CMP	X14, #0

0x4b5f9c B.LE	4b61d4

0x4b5fa0 STR	X1, [X21, X4,LSL #3]

0x4b5fa4 STR	X4, [X23, X1,LSL #3]

0x4b5fa8 ADD	X1, X1, #1

0x4b5fac ADD	X4, X4, #1

0x4b5fb0 LDR	X15, [X19, X4,LSL #3]

0x4b5fb4 CMP	X15, #0

0x4b5fb8 B.LE	4b61b0

0x4b5fbc STR	X1, [X21, X4,LSL #3]

0x4b5fc0 STR	X4, [X23, X1,LSL #3]

0x4b5fc4 ADD	X1, X1, #1

0x4b5fc8 ADD	X4, X4, #1

0x4b5fcc LDR	X16, [X19, X4,LSL #3]

0x4b5fd0 CMP	X16, #0

0x4b5fd4 B.LE	4b61a4

0x4b5fd8 STR	X1, [X21, X4,LSL #3]

0x4b5fdc STR	X4, [X23, X1,LSL #3]

0x4b5fe0 ADD	X1, X1, #1

0x4b5fe4 ADD	X4, X4, #1

0x4b5fe8 LDR	X17, [X19, X4,LSL #3]

0x4b5fec CMP	X17, #0

0x4b5ff0 B.LE	4b619c

0x4b5ff4 STR	X1, [X21, X4,LSL #3]

0x4b5ff8 STR	X4, [X23, X1,LSL #3]

0x4b5ffc ADD	X1, X1, #1

0x4b6000 ADD	X4, X4, #1

0x4b6004 CMP	X8, X4

0x4b6008 B.NE	4b60fc

(2396) 0x4b600c LDR	X23, [SP, #48]

(2396) 0x4b6010 LDP	X19, X20, [SP, #16]

(2396) 0x4b6014 LDP	X21, X22, [SP, #32]

(2396) 0x4b6018 LDP	X29, X30, [SP], #96

(2396) 0x4b601c RET

  (2397) 0x4b6020 STR	X1, [X21, X4,LSL #3]

  (2397) 0x4b6024 STR	X4, [X23, X1,LSL #3]

  (2397) 0x4b6028 ADD	X4, X4, #1

  (2397) 0x4b602c ADD	X1, X1, #1

  (2397) 0x4b6030 LDR	X3, [X19, X4,LSL #3]

  (2397) 0x4b6034 CMP	X3, #0

  (2397) 0x4b6038 B.LE	4b611c

    (2398) 0x4b603c ADD	X6, X4, #1

    (2398) 0x4b6040 STR	X1, [X21, X4,LSL #3]

    (2398) 0x4b6044 STR	X4, [X23, X1,LSL #3]

    (2398) 0x4b6048 ADD	X1, X1, #1

    (2398) 0x4b604c LDR	X7, [X19, X6,LSL #3]

    (2398) 0x4b6050 CMP	X7, #0

    (2398) 0x4b6054 B.LE	4b6130

  (2404) 0x4b6058 ADD	X2, X4, #2

  (2404) 0x4b605c STR	X1, [X21, X6,LSL #3]

  (2404) 0x4b6060 STR	X6, [X23, X1,LSL #3]

  (2404) 0x4b6064 ADD	X1, X1, #1

  (2404) 0x4b6068 LDR	X0, [X19, X2,LSL #3]

  (2404) 0x4b606c CMP	X0, #0

  (2404) 0x4b6070 B.LE	4b6144

    (2398) 0x4b6074 ADD	X18, X4, #3

    (2398) 0x4b6078 STR	X1, [X21, X2,LSL #3]

    (2398) 0x4b607c STR	X2, [X23, X1,LSL #3]

    (2398) 0x4b6080 ADD	X1, X1, #1

    (2398) 0x4b6084 LDR	X20, [X19, X18,LSL #3]

    (2398) 0x4b6088 CMP	X20, #0

    (2398) 0x4b608c B.LE	4b6158

  (2402) 0x4b6090 ADD	X22, X4, #4

  (2402) 0x4b6094 STR	X1, [X21, X18,LSL #3]

  (2402) 0x4b6098 STR	X18, [X23, X1,LSL #3]

  (2402) 0x4b609c ADD	X1, X1, #1

  (2402) 0x4b60a0 LDR	X5, [X19, X22,LSL #3]

  (2402) 0x4b60a4 CMP	X5, #0

  (2402) 0x4b60a8 B.LE	4b616c

    (2398) 0x4b60ac ADD	X10, X4, #5

    (2398) 0x4b60b0 STR	X1, [X21, X22,LSL #3]

    (2398) 0x4b60b4 STR	X22, [X23, X1,LSL #3]

    (2398) 0x4b60b8 ADD	X1, X1, #1

    (2398) 0x4b60bc LDR	X11, [X19, X10,LSL #3]

    (2398) 0x4b60c0 CMP	X11, #0

    (2398) 0x4b60c4 B.LE	4b6180

  (2400) 0x4b60c8 ADD	X12, X4, #6

  (2400) 0x4b60cc STR	X1, [X21, X10,LSL #3]

  (2400) 0x4b60d0 STR	X10, [X23, X1,LSL #3]

  (2400) 0x4b60d4 ADD	X1, X1, #1

  (2400) 0x4b60d8 LDR	X13, [X19, X12,LSL #3]

  (2400) 0x4b60dc CMP	X13, #0

  (2400) 0x4b60e0 B.LE	4b6194

    (2398) 0x4b60e4 STR	X1, [X21, X12,LSL #3]

    (2398) 0x4b60e8 STR	X12, [X23, X1,LSL #3]

    (2398) 0x4b60ec ADD	X1, X1, #1

    (2398) 0x4b60f0 ADD	X4, X4, #7

    (2398) 0x4b60f4 CMP	X8, X4

    (2398) 0x4b60f8 B.EQ	4b600c

    (2398) 0x4b60fc LDR	X30, [X19, X4,LSL #3]

    (2398) 0x4b6100 CMP	X30, #0

    (2398) 0x4b6104 B.GT	4b6020

    (2398) 0x4b6108 STR	X9, [X21, X4,LSL #3]

    (2398) 0x4b610c ADD	X4, X4, #1

    (2398) 0x4b6110 LDR	X3, [X19, X4,LSL #3]

    (2398) 0x4b6114 CMP	X3, #0

    (2398) 0x4b6118 B.GT	4b603c

  (2405) 0x4b611c ADD	X6, X4, #1

  (2405) 0x4b6120 STR	X9, [X21, X4,LSL #3]

  (2405) 0x4b6124 LDR	X7, [X19, X6,LSL #3]

  (2405) 0x4b6128 CMP	X7, #0

  (2405) 0x4b612c B.GT	4b6058

    (2398) 0x4b6130 ADD	X2, X4, #2

    (2398) 0x4b6134 STR	X9, [X21, X6,LSL #3]

    (2398) 0x4b6138 LDR	X0, [X19, X2,LSL #3]

    (2398) 0x4b613c CMP	X0, #0

    (2398) 0x4b6140 B.GT	4b6074

  (2403) 0x4b6144 ADD	X18, X4, #3

  (2403) 0x4b6148 STR	X9, [X21, X2,LSL #3]

  (2403) 0x4b614c LDR	X20, [X19, X18,LSL #3]

  (2403) 0x4b6150 CMP	X20, #0

  (2403) 0x4b6154 B.GT	4b6090

    (2398) 0x4b6158 ADD	X22, X4, #4

    (2398) 0x4b615c STR	X9, [X21, X18,LSL #3]

    (2398) 0x4b6160 LDR	X5, [X19, X22,LSL #3]

    (2398) 0x4b6164 CMP	X5, #0

    (2398) 0x4b6168 B.GT	4b60ac

  (2401) 0x4b616c ADD	X10, X4, #5

  (2401) 0x4b6170 STR	X9, [X21, X22,LSL #3]

  (2401) 0x4b6174 LDR	X11, [X19, X10,LSL #3]

  (2401) 0x4b6178 CMP	X11, #0

  (2401) 0x4b617c B.GT	4b60c8

    (2398) 0x4b6180 ADD	X12, X4, #6

    (2398) 0x4b6184 STR	X9, [X21, X10,LSL #3]

    (2398) 0x4b6188 LDR	X13, [X19, X12,LSL #3]

    (2398) 0x4b618c CMP	X13, #0

    (2398) 0x4b6190 B.GT	4b60e4

  (2399) 0x4b6194 STR	X9, [X21, X12,LSL #3]

  (2399) 0x4b6198 B	4b60f0

0x4b619c STR	X9, [X21, X4,LSL #3]

0x4b61a0 B	4b6000

0x4b61a4 STR	X9, [X21, X4,LSL #3]

0x4b61a8 ADD	X4, X4, #1

0x4b61ac B	4b5fe8

0x4b61b0 STR	X9, [X21, X4,LSL #3]

0x4b61b4 ADD	X4, X4, #1

0x4b61b8 B	4b5fcc

0x4b61bc STR	X9, [X21, X4,LSL #3]

0x4b61c0 ADD	X4, X4, #1

0x4b61c4 B	4b5f94

0x4b61c8 STR	X9, [X21, X4,LSL #3]

0x4b61cc ADD	X4, X4, #1

0x4b61d0 B	4b5f78

0x4b61d4 STR	X9, [X21, X4,LSL #3]

0x4b61d8 ADD	X4, X4, #1

0x4b61dc B	4b5fb0

0x4b61e0 STR	X9, [X21, X4,LSL #3]

0x4b61e4 ADD	X4, X4, #1

0x4b61e8 B	4b5f5c

Coverage (%)	Name	Source Location	Module
►100.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 49% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 22.38 to 21.00 cycles (1.07x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.38 to 1.00 cycles (22.37x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	179
loop length	716
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

22.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	21.00	21.00	15.17	15.17	15.17	15.17	15.17	15.17	0.00	0.00	0.00	0.00	16.50	16.17	16.33	13.50	13.50
cycles	21.00	21.00	15.17	15.17	15.17	15.17	15.17	15.17	0.00	0.00	0.00	0.00	16.50	16.17	16.33	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.38
Overall L1	22.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.38 cycles. At this rate:

9% of peak load performance is reached (9.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4b5ce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, SP, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X0, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X21, [X22, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X2, [X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X20, X23, [X22, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
BL 52df80 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X1, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4b5ee0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X19, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X19, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X5, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X6, X2, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X7, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X8, X7, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5e28 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5e08 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5df0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5dd8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5dc0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5da8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5d90 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5d8c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X10, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5da4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X11, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5dbc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5dd4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X13, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5dec <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X14, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5e04 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X15, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5e1c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X18, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5ed8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 4b5ee0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 52ef20 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X4, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4b600c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X8, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X10, X5, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b60fc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5fe8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5fcc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5fb0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5f94 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5f78 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5f5c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61e0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61c8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X13, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61bc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61d4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X15, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61b0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61a4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X17, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b619c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X8, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4b60fc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 4b6000 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5fe8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5fcc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5f94 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5f78 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5fb0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5f5c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 22.38 to 1.00 cycles (22.37x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	179
loop length	716
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

22.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	21.00	21.00	15.17	15.17	15.17	15.17	15.17	15.17	0.00	0.00	0.00	0.00	16.50	16.17	16.33	13.50	13.50
cycles	21.00	21.00	15.17	15.17	15.17	15.17	15.17	15.17	0.00	0.00	0.00	0.00	16.50	16.17	16.33	13.50	13.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.38
Overall L1	22.38

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.38 cycles. At this rate:

9% of peak load performance is reached (9.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4b5ce0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, SP, #88	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X0, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X21, [X22, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X2, [X22]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X20, X23, [X22, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
BL 52df80 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X4, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X1, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4b5ee0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X18, X19, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
MOVZ W0, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X5, X19, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X3, X5, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X6, X2, #3, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X7, X6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X8, X7, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5e28 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5e08 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5df0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5dd8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5dc0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5da8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5d90 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xb0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5d8c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X10, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5da4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X11, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5dbc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5dd4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X13, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5dec <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X14, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5e04 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X18]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X15, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b5e1c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X18, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5ed8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 4b5ee0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X2, [SP, #72]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
BL 52ef20 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X4, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4b600c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X5, X8, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X1, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X10, X5, #4224	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b60fc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5fe8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5fcc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5fb0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5f94 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5f78 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4b5f5c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X11, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61e0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x500>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X12, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X12, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61c8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X13, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61bc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X14, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61d4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X15, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61b0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b61a4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X17, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4b619c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X1, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X4, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X1, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
CMP X8, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4b60fc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x41c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 4b6000 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5fe8 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5fcc <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5f94 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5f78 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5fb0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X21, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X4, X4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B 4b5f5c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS._omp_fn.0–	0.01	0.00
○Loop 2406 - par_strength.c:1261-1263 - exec	0.01	0.00
▼Loop 2396 - par_strength.c:1253-1278 - exec–	0.00	0.00
○Loop 2403 - par_strength.c:1268-1278 - exec	0.00	0.00
○Loop 2402 - par_strength.c:1268-1274 - exec	0.00	0.00
○Loop 2405 - par_strength.c:1268-1278 - exec	0.00	0.00
○Loop 2401 - par_strength.c:1268-1278 - exec	0.00	0.00
▼Loop 2397 - par_strength.c:1268-1278 - exec–	0.00	0.00
○Loop 2398 - par_strength.c:1268-1278 - exec	0.01	0.01
○Loop 2404 - par_strength.c:1268-1274 - exec	0.00	0.00
○Loop 2400 - par_strength.c:1268-1274 - exec	0.00	0.00
○Loop 2399 - par_strength.c:1278-1278 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code