OV - exec - Function hypre_BoomerAMGCreateS._omp

	Function: hypre_BoomerAMGCreateS._omp_fn.1	Module: exec	Source: par_strength.c:246-513 [...]	Coverage (incl. loops): 0.45% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

[...]

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

[...]

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

[...]

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

[...]

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x4b17ac STP	X29, X30, [SP, #816]!

0x4b17b0 ORR	X3, XZR, X0

0x4b17b4 ADD	X29, SP, #0

0x4b17b8 ADD	X1, SP, #184

0x4b17bc ADD	X0, SP, #176

0x4b17c0 STP	X19, X20, [SP, #16]

0x4b17c4 STP	X21, X22, [SP, #32]

0x4b17c8 STP	X23, X24, [SP, #48]

0x4b17cc STP	X25, X26, [SP, #64]

0x4b17d0 STP	X27, X28, [SP, #80]

0x4b17d4 STP	D14, D15, [SP, #96]

0x4b17d8 LDP	X5, X2, [X3, #80]

0x4b17dc LDP	D14, D15, [X3]

0x4b17e0 STP	X5, X2, [SP, #152]

0x4b17e4 ORR	X2, XZR, X5

0x4b17e8 LDP	X4, X21, [X3, #16]

0x4b17ec STR	X4, [SP, #168]

0x4b17f0 LDP	X10, X22, [X3, #32]

0x4b17f4 STR	X10, [SP, #144]

0x4b17f8 LDP	X9, X23, [X3, #48]

0x4b17fc STR	X9, [SP, #136]

0x4b1800 LDP	X7, X28, [X3, #96]

0x4b1804 LDP	X25, X24, [X3, #64]

0x4b1808 STR	X7, [SP, #128]

0x4b180c LDP	X8, X27, [X3, #112]

0x4b1810 STR	X8, [SP, #120]

0x4b1814 LDP	X26, X6, [X3, #128]

0x4b1818 STR	X6, [SP, #112]

0x4b181c LDP	X19, X20, [X3, #144]

0x4b1820 BL	52df80

0x4b1824 LDP	X4, X30, [SP, #176]

0x4b1828 STP	XZR, XZR, [SP, #192]

0x4b182c CMP	X4, X30

0x4b1830 LDR	X18, [SP, #152]

0x4b1834 LDP	X8, X7, [SP, #120]

0x4b1838 LDP	X15, X10, [SP, #136]

0x4b183c B.GE	4b1dd0

0x4b1840 UBFM	X0, X4, #61, #60

0x4b1844 FMOV	D31, #1.0000000

0x4b1848 ADD	X12, X15, X4,LSL #3

0x4b184c MOVZ	X2, #0

0x4b1850 ADD	X11, X0, #8

0x4b1854 MOVZ	X1, #0

0x4b1858 LDP	X16, X17, [SP, #160]

0x4b185c MOVN	X13, #0

0x4b1860 ADD	X3, X15, X11

0x4b1864 ADD	X0, X10, X11

0x4b1868 STP	X27, X28, [SP, #120]

0x4b186c STP	X18, X15, [SP, #136]

    (2299) 0x4b1870 STR	X1, [X7, X4,LSL #3]

    (2299) 0x4b1874 CBZ	X16, 4b187c

    (2299) 0x4b1878 STR	X2, [X8, X4,LSL #3]

    (2299) 0x4b187c LDP	X6, X9, [X0, #1016]

    (2299) 0x4b1880 UBFM	X14, X6, #61, #60

    (2299) 0x4b1884 ADD	X5, X6, #1

    (2299) 0x4b1888 LDR	D4, [X22, X14]

    (2299) 0x4b188c CMP	X17, #1

    (2299) 0x4b1890 B.LE	4b1f1c

    (2299) 0x4b1894 FCMPE	D4, #0

    (2299) 0x4b1898 B.MI	4b2310

  (2313) 0x4b189c CMP	X5, X9

  (2313) 0x4b18a0 B.GE	4b2db4

  (2313) 0x4b18a4 SUB	X18, X9, X5

  (2313) 0x4b18a8 LDR	X11, [X21, X4,LSL #3]

  (2313) 0x4b18ac FMOV	D3, D4

  (2313) 0x4b18b0 MOVI	D22, #0

  (2313) 0x4b18b4 ANDS	X15, X18, #4224

  (2313) 0x4b18b8 B.EQ	4b1990

      (2315) 0x4b18bc CMP	X15, #1

      (2315) 0x4b18c0 B.EQ	4b1964

    (2317) 0x4b18c4 CMP	X15, #2

    (2317) 0x4b18c8 B.EQ	4b1950

    (2317) 0x4b18cc CMP	X15, #3

    (2317) 0x4b18d0 B.EQ	4b193c

    (2317) 0x4b18d4 CMP	X15, #4

    (2317) 0x4b18d8 B.EQ	4b1928

    (2317) 0x4b18dc CMP	X15, #5

    (2317) 0x4b18e0 B.EQ	4b1914

    (2317) 0x4b18e4 CMP	X15, #6

    (2317) 0x4b18e8 B.EQ	4b1900

    (2317) 0x4b18ec LDR	X27, [X25, X5,LSL #3]

    (2317) 0x4b18f0 LDR	X28, [X21, X27,LSL #3]

    (2317) 0x4b18f4 CMP	X11, X28

    (2317) 0x4b18f8 B.EQ	4b2e38

    (2317) 0x4b18fc ADD	X5, X5, #1

    (2317) 0x4b1900 LDR	X18, [X25, X5,LSL #3]

    (2317) 0x4b1904 LDR	X15, [X21, X18,LSL #3]

    (2317) 0x4b1908 CMP	X11, X15

    (2317) 0x4b190c B.EQ	4b2da0

    (2317) 0x4b1910 ADD	X5, X5, #1

    (2317) 0x4b1914 LDR	X27, [X25, X5,LSL #3]

    (2317) 0x4b1918 LDR	X28, [X21, X27,LSL #3]

    (2317) 0x4b191c CMP	X11, X28

    (2317) 0x4b1920 B.EQ	4b2d28

    (2317) 0x4b1924 ADD	X5, X5, #1

    (2317) 0x4b1928 LDR	X18, [X25, X5,LSL #3]

    (2317) 0x4b192c LDR	X15, [X21, X18,LSL #3]

    (2317) 0x4b1930 CMP	X11, X15

    (2317) 0x4b1934 B.EQ	4b2cc4

    (2317) 0x4b1938 ADD	X5, X5, #1

    (2317) 0x4b193c LDR	X27, [X25, X5,LSL #3]

    (2317) 0x4b1940 LDR	X28, [X21, X27,LSL #3]

    (2317) 0x4b1944 CMP	X11, X28

    (2317) 0x4b1948 B.EQ	4b1ed4

    (2317) 0x4b194c ADD	X5, X5, #1

    (2317) 0x4b1950 LDR	X18, [X25, X5,LSL #3]

    (2317) 0x4b1954 LDR	X15, [X21, X18,LSL #3]

    (2317) 0x4b1958 CMP	X11, X15

    (2317) 0x4b195c B.EQ	4b1ec0

    (2317) 0x4b1960 ADD	X5, X5, #1

      (2315) 0x4b1964 LDR	X27, [X25, X5,LSL #3]

      (2315) 0x4b1968 LDR	X28, [X21, X27,LSL #3]

      (2315) 0x4b196c CMP	X11, X28

      (2315) 0x4b1970 B.NE	4b1984

(2300) 0x4b1974 LDR	D21, [X22, X5,LSL #3]

(2300) 0x4b1978 FCMPE	D21, D22

(2300) 0x4b197c FADD	D3, D3, D21

(2300) 0x4b1980 FCSEL	D22, D22, D21, #12

(2300) 0x4b1984 ADD	X5, X5, #1

(2300) 0x4b1988 CMP	X5, X9

(2300) 0x4b198c B.EQ	4b1ab8

    (2314) 0x4b1990 LDR	X18, [X25, X5,LSL #3]

    (2314) 0x4b1994 LDR	X15, [X21, X18,LSL #3]

    (2314) 0x4b1998 CMP	X11, X15

    (2314) 0x4b199c B.NE	4b19b0

    (2314) 0x4b19a0 LDR	D1, [X22, X5,LSL #3]

    (2314) 0x4b19a4 FCMPE	D1, D22

    (2314) 0x4b19a8 FADD	D3, D3, D1

    (2314) 0x4b19ac FCSEL	D22, D22, D1, #12

    (2314) 0x4b19b0 ADD	X5, X5, #1

    (2314) 0x4b19b4 LDR	X27, [X25, X5,LSL #3]

    (2314) 0x4b19b8 LDR	X28, [X21, X27,LSL #3]

    (2314) 0x4b19bc CMP	X11, X28

    (2314) 0x4b19c0 B.NE	4b19d4

    (2314) 0x4b19c4 LDR	D20, [X22, X5,LSL #3]

    (2314) 0x4b19c8 FCMPE	D20, D22

    (2314) 0x4b19cc FADD	D3, D3, D20

    (2314) 0x4b19d0 FCSEL	D22, D22, D20, #12

    (2314) 0x4b19d4 ADD	X15, X5, #1

    (2314) 0x4b19d8 LDR	X18, [X25, X15,LSL #3]

    (2314) 0x4b19dc LDR	X27, [X21, X18,LSL #3]

    (2314) 0x4b19e0 CMP	X11, X27

    (2314) 0x4b19e4 B.NE	4b19f8

    (2314) 0x4b19e8 LDR	D0, [X22, X15,LSL #3]

    (2314) 0x4b19ec FCMPE	D0, D22

    (2314) 0x4b19f0 FADD	D3, D3, D0

    (2314) 0x4b19f4 FCSEL	D22, D22, D0, #12

    (2314) 0x4b19f8 ADD	X28, X5, #2

    (2314) 0x4b19fc LDR	X15, [X25, X28,LSL #3]

    (2314) 0x4b1a00 LDR	X18, [X21, X15,LSL #3]

    (2314) 0x4b1a04 CMP	X11, X18

    (2314) 0x4b1a08 B.NE	4b1a1c

    (2314) 0x4b1a0c LDR	D24, [X22, X28,LSL #3]

    (2314) 0x4b1a10 FCMPE	D24, D22

    (2314) 0x4b1a14 FADD	D3, D3, D24

    (2314) 0x4b1a18 FCSEL	D22, D22, D24, #12

    (2314) 0x4b1a1c ADD	X27, X5, #3

    (2314) 0x4b1a20 LDR	X28, [X25, X27,LSL #3]

    (2314) 0x4b1a24 LDR	X15, [X21, X28,LSL #3]

    (2314) 0x4b1a28 CMP	X11, X15

    (2314) 0x4b1a2c B.NE	4b1a40

    (2314) 0x4b1a30 LDR	D25, [X22, X27,LSL #3]

    (2314) 0x4b1a34 FCMPE	D25, D22

    (2314) 0x4b1a38 FADD	D3, D3, D25

    (2314) 0x4b1a3c FCSEL	D22, D22, D25, #12

    (2314) 0x4b1a40 ADD	X27, X5, #4

    (2314) 0x4b1a44 LDR	X18, [X25, X27,LSL #3]

    (2314) 0x4b1a48 LDR	X28, [X21, X18,LSL #3]

    (2314) 0x4b1a4c CMP	X11, X28

    (2314) 0x4b1a50 B.NE	4b1a64

    (2314) 0x4b1a54 LDR	D26, [X22, X27,LSL #3]

    (2314) 0x4b1a58 FCMPE	D26, D22

    (2314) 0x4b1a5c FADD	D3, D3, D26

    (2314) 0x4b1a60 FCSEL	D22, D22, D26, #12

    (2314) 0x4b1a64 ADD	X15, X5, #5

    (2314) 0x4b1a68 LDR	X27, [X25, X15,LSL #3]

    (2314) 0x4b1a6c LDR	X18, [X21, X27,LSL #3]

    (2314) 0x4b1a70 CMP	X11, X18

    (2314) 0x4b1a74 B.NE	4b1a88

    (2314) 0x4b1a78 LDR	D19, [X22, X15,LSL #3]

    (2314) 0x4b1a7c FCMPE	D19, D22

    (2314) 0x4b1a80 FADD	D3, D3, D19

    (2314) 0x4b1a84 FCSEL	D22, D22, D19, #12

    (2314) 0x4b1a88 ADD	X28, X5, #6

    (2314) 0x4b1a8c LDR	X15, [X25, X28,LSL #3]

    (2314) 0x4b1a90 LDR	X27, [X21, X15,LSL #3]

    (2314) 0x4b1a94 CMP	X11, X27

    (2314) 0x4b1a98 B.NE	4b1aac

    (2314) 0x4b1a9c LDR	D28, [X22, X28,LSL #3]

    (2314) 0x4b1aa0 FCMPE	D28, D22

    (2314) 0x4b1aa4 FADD	D3, D3, D28

    (2314) 0x4b1aa8 FCSEL	D22, D22, D28, #12

    (2314) 0x4b1aac ADD	X5, X5, #7

    (2314) 0x4b1ab0 CMP	X5, X9

    (2314) 0x4b1ab4 B.NE	4b1990

  (2313) 0x4b1ab8 LDR	X18, [X3]

  (2313) 0x4b1abc LDR	X15, [X12]

  (2313) 0x4b1ac0 CMP	X15, X18

  (2313) 0x4b1ac4 B.GE	4b1cd8

(2300) 0x4b1ac8 SUB	X28, X18, X15

(2300) 0x4b1acc LDR	X11, [X21, X4,LSL #3]

(2300) 0x4b1ad0 ORR	X5, XZR, X15

(2300) 0x4b1ad4 ANDS	X27, X28, #4224

(2300) 0x4b1ad8 B.EQ	4b1bb0

(2300) 0x4b1adc CMP	X27, #1

(2300) 0x4b1ae0 B.EQ	4b1b84

(2300) 0x4b1ae4 CMP	X27, #2

(2300) 0x4b1ae8 B.EQ	4b1b70

(2300) 0x4b1aec CMP	X27, #3

(2300) 0x4b1af0 B.EQ	4b1b5c

(2300) 0x4b1af4 CMP	X27, #4

(2300) 0x4b1af8 B.EQ	4b1b48

(2300) 0x4b1afc CMP	X27, #5

(2300) 0x4b1b00 B.EQ	4b1b34

(2300) 0x4b1b04 CMP	X27, #6

(2300) 0x4b1b08 B.EQ	4b1b20

(2300) 0x4b1b0c LDR	X5, [X24, X15,LSL #3]

(2300) 0x4b1b10 LDR	X28, [X26, X5,LSL #3]

(2300) 0x4b1b14 CMP	X11, X28

(2300) 0x4b1b18 B.EQ	4b2e50

(2300) 0x4b1b1c ADD	X5, X15, #1

(2300) 0x4b1b20 LDR	X27, [X24, X5,LSL #3]

(2300) 0x4b1b24 LDR	X28, [X26, X27,LSL #3]

(2300) 0x4b1b28 CMP	X11, X28

(2300) 0x4b1b2c B.EQ	4b2d8c

(2300) 0x4b1b30 ADD	X5, X5, #1

(2300) 0x4b1b34 LDR	X27, [X24, X5,LSL #3]

(2300) 0x4b1b38 LDR	X28, [X26, X27,LSL #3]

(2300) 0x4b1b3c CMP	X11, X28

(2300) 0x4b1b40 B.EQ	4b2d14

(2300) 0x4b1b44 ADD	X5, X5, #1

(2300) 0x4b1b48 LDR	X27, [X24, X5,LSL #3]

(2300) 0x4b1b4c LDR	X28, [X26, X27,LSL #3]

(2300) 0x4b1b50 CMP	X11, X28

(2300) 0x4b1b54 B.EQ	4b2cd8

(2300) 0x4b1b58 ADD	X5, X5, #1

(2300) 0x4b1b5c LDR	X27, [X24, X5,LSL #3]

(2300) 0x4b1b60 LDR	X28, [X26, X27,LSL #3]

(2300) 0x4b1b64 CMP	X11, X28

(2300) 0x4b1b68 B.EQ	4b1efc

(2300) 0x4b1b6c ADD	X5, X5, #1

(2300) 0x4b1b70 LDR	X27, [X24, X5,LSL #3]

(2300) 0x4b1b74 LDR	X28, [X26, X27,LSL #3]

(2300) 0x4b1b78 CMP	X11, X28

(2300) 0x4b1b7c B.EQ	4b1ee8

(2300) 0x4b1b80 ADD	X5, X5, #1

(2300) 0x4b1b84 LDR	X27, [X24, X5,LSL #3]

(2300) 0x4b1b88 LDR	X28, [X26, X27,LSL #3]

(2300) 0x4b1b8c CMP	X11, X28

(2300) 0x4b1b90 B.NE	4b1ba4

(2300) 0x4b1b94 LDR	D7, [X23, X5,LSL #3]

(2300) 0x4b1b98 FCMPE	D7, D22

(2300) 0x4b1b9c FADD	D3, D3, D7

(2300) 0x4b1ba0 FCSEL	D22, D22, D7, #12

(2300) 0x4b1ba4 ADD	X5, X5, #1

(2300) 0x4b1ba8 CMP	X5, X18

(2300) 0x4b1bac B.EQ	4b1cd8

  (2322) 0x4b1bb0 LDR	X27, [X24, X5,LSL #3]

  (2322) 0x4b1bb4 LDR	X28, [X26, X27,LSL #3]

  (2322) 0x4b1bb8 CMP	X11, X28

  (2322) 0x4b1bbc B.NE	4b1bd0

  (2322) 0x4b1bc0 LDR	D27, [X23, X5,LSL #3]

  (2322) 0x4b1bc4 FCMPE	D27, D22

  (2322) 0x4b1bc8 FADD	D3, D3, D27

  (2322) 0x4b1bcc FCSEL	D22, D22, D27, #12

  (2322) 0x4b1bd0 ADD	X5, X5, #1

  (2322) 0x4b1bd4 LDR	X27, [X24, X5,LSL #3]

  (2322) 0x4b1bd8 LDR	X28, [X26, X27,LSL #3]

  (2322) 0x4b1bdc CMP	X11, X28

  (2322) 0x4b1be0 B.NE	4b1bf4

  (2322) 0x4b1be4 LDR	D6, [X23, X5,LSL #3]

  (2322) 0x4b1be8 FCMPE	D6, D22

  (2322) 0x4b1bec FADD	D3, D3, D6

  (2322) 0x4b1bf0 FCSEL	D22, D22, D6, #12

  (2322) 0x4b1bf4 ADD	X27, X5, #1

  (2322) 0x4b1bf8 LDR	X28, [X24, X27,LSL #3]

  (2322) 0x4b1bfc LDR	X28, [X26, X28,LSL #3]

  (2322) 0x4b1c00 CMP	X11, X28

  (2322) 0x4b1c04 B.NE	4b1c18

  (2322) 0x4b1c08 LDR	D5, [X23, X27,LSL #3]

  (2322) 0x4b1c0c FCMPE	D5, D22

  (2322) 0x4b1c10 FADD	D3, D3, D5

  (2322) 0x4b1c14 FCSEL	D22, D22, D5, #12

  (2322) 0x4b1c18 ADD	X27, X5, #2

  (2322) 0x4b1c1c LDR	X28, [X24, X27,LSL #3]

  (2322) 0x4b1c20 LDR	X28, [X26, X28,LSL #3]

  (2322) 0x4b1c24 CMP	X11, X28

  (2322) 0x4b1c28 B.NE	4b1c3c

  (2322) 0x4b1c2c LDR	D2, [X23, X27,LSL #3]

  (2322) 0x4b1c30 FCMPE	D2, D22

  (2322) 0x4b1c34 FADD	D3, D3, D2

  (2322) 0x4b1c38 FCSEL	D22, D22, D2, #12

  (2322) 0x4b1c3c ADD	X27, X5, #3

  (2322) 0x4b1c40 LDR	X28, [X24, X27,LSL #3]

  (2322) 0x4b1c44 LDR	X28, [X26, X28,LSL #3]

  (2322) 0x4b1c48 CMP	X11, X28

  (2322) 0x4b1c4c B.NE	4b1c60

  (2322) 0x4b1c50 LDR	D21, [X23, X27,LSL #3]

  (2322) 0x4b1c54 FCMPE	D21, D22

  (2322) 0x4b1c58 FADD	D3, D3, D21

  (2322) 0x4b1c5c FCSEL	D22, D22, D21, #12

  (2322) 0x4b1c60 ADD	X27, X5, #4

  (2322) 0x4b1c64 LDR	X28, [X24, X27,LSL #3]

  (2322) 0x4b1c68 LDR	X28, [X26, X28,LSL #3]

  (2322) 0x4b1c6c CMP	X11, X28

  (2322) 0x4b1c70 B.NE	4b1c84

  (2322) 0x4b1c74 LDR	D1, [X23, X27,LSL #3]

  (2322) 0x4b1c78 FCMPE	D1, D22

  (2322) 0x4b1c7c FADD	D3, D3, D1

  (2322) 0x4b1c80 FCSEL	D22, D22, D1, #12

  (2322) 0x4b1c84 ADD	X27, X5, #5

  (2322) 0x4b1c88 LDR	X28, [X24, X27,LSL #3]

  (2322) 0x4b1c8c LDR	X28, [X26, X28,LSL #3]

  (2322) 0x4b1c90 CMP	X11, X28

  (2322) 0x4b1c94 B.NE	4b1ca8

  (2322) 0x4b1c98 LDR	D20, [X23, X27,LSL #3]

  (2322) 0x4b1c9c FCMPE	D20, D22

  (2322) 0x4b1ca0 FADD	D3, D3, D20

  (2322) 0x4b1ca4 FCSEL	D22, D22, D20, #12

  (2322) 0x4b1ca8 ADD	X27, X5, #6

  (2322) 0x4b1cac LDR	X28, [X24, X27,LSL #3]

  (2322) 0x4b1cb0 LDR	X28, [X26, X28,LSL #3]

  (2322) 0x4b1cb4 CMP	X11, X28

  (2322) 0x4b1cb8 B.NE	4b1ccc

  (2322) 0x4b1cbc LDR	D0, [X23, X27,LSL #3]

  (2322) 0x4b1cc0 FCMPE	D0, D22

  (2322) 0x4b1cc4 FADD	D3, D3, D0

  (2322) 0x4b1cc8 FCSEL	D22, D22, D0, #12

  (2322) 0x4b1ccc ADD	X5, X5, #7

  (2322) 0x4b1cd0 CMP	X5, X18

  (2322) 0x4b1cd4 B.NE	4b1bb0

(2300) 0x4b1cd8 FABS	D4, D4

(2300) 0x4b1cdc SUB	X6, X9, X6

(2300) 0x4b1ce0 FABS	D24, D3

(2300) 0x4b1ce4 SUB	X9, X18, X15

(2300) 0x4b1ce8 STR	X13, [X19, X14]

(2300) 0x4b1cec LDP	X18, X15, [X0, #1016]

(2300) 0x4b1cf0 SUB	X14, X6, #1

(2300) 0x4b1cf4 ADD	X2, X2, X9

(2300) 0x4b1cf8 ADD	X1, X1, X14

(2300) 0x4b1cfc FMUL	D25, D4, D15

(2300) 0x4b1d00 ADD	X27, X18, #1

(2300) 0x4b1d04 FCMPE	D25, D24

(2300) 0x4b1d08 B.MI	4b2838

(2300) 0x4b1d0c CMP	X27, X15

(2300) 0x4b1d10 B.GE	4b1d5c

(2300) 0x4b1d14 FMUL	D26, D14, D22

(2300) 0x4b1d18 HINT	#0

(2300) 0x4b1d1c HINT	#0

  (2321) 0x4b1d20 LDR	D19, [X22, X27,LSL #3]

  (2321) 0x4b1d24 FCMPE	D26, D19

  (2321) 0x4b1d28 B.LS	4b1d40

  (2321) 0x4b1d2c LDR	X28, [X25, X27,LSL #3]

  (2321) 0x4b1d30 LDR	X15, [X21, X4,LSL #3]

  (2321) 0x4b1d34 LDR	X11, [X21, X28,LSL #3]

  (2321) 0x4b1d38 CMP	X11, X15

  (2321) 0x4b1d3c B.EQ	4b1d48

  (2321) 0x4b1d40 SUB	X1, X1, #1

  (2321) 0x4b1d44 MOVN	X28, #0

  (2321) 0x4b1d48 STR	X28, [X19, X27,LSL #3]

  (2321) 0x4b1d4c ADD	X27, X27, #1

  (2321) 0x4b1d50 LDR	X5, [X0]

  (2321) 0x4b1d54 CMP	X5, X27

  (2321) 0x4b1d58 B.GT	4b1d20

(2300) 0x4b1d5c LDR	X27, [X3]

(2300) 0x4b1d60 LDR	X18, [X12]

(2300) 0x4b1d64 CMP	X18, X27

(2300) 0x4b1d68 B.GE	4b1dac

(2300) 0x4b1d6c FMUL	D28, D14, D22

  (2320) 0x4b1d70 LDR	D3, [X23, X18,LSL #3]

  (2320) 0x4b1d74 FCMPE	D28, D3

  (2320) 0x4b1d78 B.LS	4b1d90

  (2320) 0x4b1d7c LDR	X6, [X24, X18,LSL #3]

  (2320) 0x4b1d80 LDR	X9, [X21, X4,LSL #3]

  (2320) 0x4b1d84 LDR	X14, [X26, X6,LSL #3]

  (2320) 0x4b1d88 CMP	X14, X9

  (2320) 0x4b1d8c B.EQ	4b1d98

  (2320) 0x4b1d90 SUB	X2, X2, #1

  (2320) 0x4b1d94 MOVN	X6, #0

  (2320) 0x4b1d98 STR	X6, [X20, X18,LSL #3]

  (2320) 0x4b1d9c ADD	X18, X18, #1

  (2320) 0x4b1da0 LDR	X15, [X3]

  (2320) 0x4b1da4 CMP	X15, X18

  (2320) 0x4b1da8 B.GT	4b1d70

    (2299) 0x4b1dac ADD	X4, X4, #1

    (2299) 0x4b1db0 ADD	X12, X12, #8

    (2299) 0x4b1db4 ADD	X3, X3, #8

    (2299) 0x4b1db8 ADD	X0, X0, #8

    (2299) 0x4b1dbc CMP	X4, X30

    (2299) 0x4b1dc0 B.NE	4b1870

(2300) 0x4b1dc4 LDP	X27, X28, [SP, #120]

(2300) 0x4b1dc8 LDP	X18, X15, [SP, #136]

(2300) 0x4b1dcc STP	X1, X2, [SP, #192]

(2300) 0x4b1dd0 ADD	X1, X7, X18,LSL #3

(2300) 0x4b1dd4 ADD	X2, SP, #200

(2300) 0x4b1dd8 ADD	X0, SP, #192

(2300) 0x4b1ddc ADD	X3, X8, X18,LSL #3

(2300) 0x4b1de0 LDR	X4, [SP, #112]

(2300) 0x4b1de4 STP	X7, X8, [SP, #112]

(2300) 0x4b1de8 STP	X15, X10, [SP, #128]

(2300) 0x4b1dec BL	52f124

(2300) 0x4b1df0 LDP	X1, X21, [SP, #176]

(2300) 0x4b1df4 CMP	X1, X21

(2300) 0x4b1df8 B.GE	4b1ea0

(2300) 0x4b1dfc LDP	X16, X10, [SP, #128]

(2300) 0x4b1e00 LDP	X7, X8, [SP, #112]

(2300) 0x4b1e04 ADD	X22, X10, #8

(2300) 0x4b1e08 ADD	X23, X16, #8

(2300) 0x4b1e0c LDP	X17, X13, [SP, #192]

  (2323) 0x4b1e10 LDR	X2, [X7, X1,LSL #3]

  (2323) 0x4b1e14 ADD	X24, X2, X17

  (2323) 0x4b1e18 STR	X24, [X7, X1,LSL #3]

  (2323) 0x4b1e1c LDR	X25, [X8, X1,LSL #3]

  (2323) 0x4b1e20 ADD	X14, X13, X25

  (2323) 0x4b1e24 STR	X14, [X8, X1,LSL #3]

  (2323) 0x4b1e28 LDR	X30, [X10, X1,LSL #3]

  (2323) 0x4b1e2c LDR	X5, [X22, X1,LSL #3]

  (2323) 0x4b1e30 LDR	X11, [X7, X1,LSL #3]

  (2323) 0x4b1e34 CMP	X30, X5

  (2323) 0x4b1e38 B.GE	4b1e64

  (2323) 0x4b1e3c HINT	#0

    (2326) 0x4b1e40 LDR	X26, [X19, X30,LSL #3]

    (2326) 0x4b1e44 ADD	X30, X30, #1

    (2326) 0x4b1e48 TBNZ	X26, #63, 4b1f10

    (2326) 0x4b1e4c STR	X26, [X28, X11,LSL #3]

    (2326) 0x4b1e50 ADD	X11, X11, #1

    (2326) 0x4b1e54 LDR	X5, [X22, X1,LSL #3]

    (2326) 0x4b1e58 CMP	X5, X30

    (2326) 0x4b1e5c B.GT	4b1e40

  (2323) 0x4b1e60 LDR	X14, [X8, X1,LSL #3]

  (2323) 0x4b1e64 LDR	X6, [X16, X1,LSL #3]

  (2323) 0x4b1e68 LDR	X4, [X23, X1,LSL #3]

    (2324) 0x4b1e6c CMP	X6, X4

    (2324) 0x4b1e70 B.GE	4b1e94

      (2325) 0x4b1e74 LDR	X9, [X20, X6,LSL #3]

      (2325) 0x4b1e78 ADD	X6, X6, #1

      (2325) 0x4b1e7c TBNZ	X9, #63, 4b1e6c

      (2325) 0x4b1e80 STR	X9, [X27, X14,LSL #3]

      (2325) 0x4b1e84 ADD	X14, X14, #1

      (2325) 0x4b1e88 LDR	X4, [X23, X1,LSL #3]

      (2325) 0x4b1e8c CMP	X4, X6

      (2325) 0x4b1e90 B.GT	4b1e74

  (2323) 0x4b1e94 ADD	X1, X1, #1

  (2323) 0x4b1e98 CMP	X1, X21

  (2323) 0x4b1e9c B.NE	4b1e10

(2300) 0x4b1ea0 LDP	D14, D15, [SP, #96]

(2300) 0x4b1ea4 LDP	X19, X20, [SP, #16]

(2300) 0x4b1ea8 LDP	X21, X22, [SP, #32]

(2300) 0x4b1eac LDP	X23, X24, [SP, #48]

(2300) 0x4b1eb0 LDP	X25, X26, [SP, #64]

(2300) 0x4b1eb4 LDP	X27, X28, [SP, #80]

(2300) 0x4b1eb8 LDP	X29, X30, [SP], #208

(2300) 0x4b1ebc RET

  (2316) 0x4b1ec0 LDR	D2, [X22, X5,LSL #3]

  (2316) 0x4b1ec4 FCMPE	D2, D22

  (2316) 0x4b1ec8 FADD	D3, D3, D2

  (2316) 0x4b1ecc FCSEL	D22, D22, D2, #12

  (2316) 0x4b1ed0 B	4b1960

    (2317) 0x4b1ed4 LDR	D5, [X22, X5,LSL #3]

    (2317) 0x4b1ed8 FCMPE	D5, D22

    (2317) 0x4b1edc FADD	D3, D3, D5

    (2317) 0x4b1ee0 FCSEL	D22, D22, D5, #12

    (2317) 0x4b1ee4 B	4b194c

(2300) 0x4b1ee8 LDR	D18, [X23, X5,LSL #3]

(2300) 0x4b1eec FCMPE	D18, D22

(2300) 0x4b1ef0 FADD	D3, D3, D18

(2300) 0x4b1ef4 FCSEL	D22, D22, D18, #12

(2300) 0x4b1ef8 B	4b1b80

(2300) 0x4b1efc LDR	D17, [X23, X5,LSL #3]

(2300) 0x4b1f00 FCMPE	D17, D22

(2300) 0x4b1f04 FADD	D3, D3, D17

(2300) 0x4b1f08 FCSEL	D22, D22, D17, #12

(2300) 0x4b1f0c B	4b1b6c

    (2326) 0x4b1f10 CMP	X30, X5

    (2326) 0x4b1f14 B.LT	4b1e40

  (2323) 0x4b1f18 B	4b1e60

    (2299) 0x4b1f1c FCMPE	D4, #0

    (2299) 0x4b1f20 B.MI	4b28c4

    (2299) 0x4b1f24 CMP	X5, X9

    (2299) 0x4b1f28 B.GE	4b2dcc

    (2299) 0x4b1f2c ADD	X15, X22, X9,LSL #3

    (2299) 0x4b1f30 ADD	X18, X14, #8

    (2299) 0x4b1f34 FMOV	D3, D4

    (2299) 0x4b1f38 MOVI	D23, #0

    (2299) 0x4b1f3c ADD	X5, X22, X18

    (2299) 0x4b1f40 SUB	X27, X15, X5

    (2299) 0x4b1f44 SUB	X28, X27, #8

    (2299) 0x4b1f48 UBFM	X11, X28, #3, #63

    (2299) 0x4b1f4c ADD	X27, X11, #1

    (2299) 0x4b1f50 ANDS	X28, X27, #4224

    (2299) 0x4b1f54 B.EQ	4b2004

    (2299) 0x4b1f58 CMP	X28, #1

    (2299) 0x4b1f5c B.EQ	4b1fec

    (2299) 0x4b1f60 CMP	X28, #2

    (2299) 0x4b1f64 B.EQ	4b1fdc

    (2299) 0x4b1f68 CMP	X28, #3

    (2299) 0x4b1f6c B.EQ	4b1fcc

    (2299) 0x4b1f70 CMP	X28, #4

    (2299) 0x4b1f74 B.EQ	4b1fbc

    (2299) 0x4b1f78 CMP	X28, #5

    (2299) 0x4b1f7c B.EQ	4b1fac

    (2299) 0x4b1f80 CMP	X28, #6

    (2299) 0x4b1f84 B.EQ	4b1f9c

    (2299) 0x4b1f88 LDR	D18, [X22, X18]

    (2299) 0x4b1f8c ADD	X5, X5, #8

    (2299) 0x4b1f90 FCMPE	D18, #0

    (2299) 0x4b1f94 FADD	D3, D4, D18

    (2299) 0x4b1f98 FCSEL	D23, D23, D18, #12

    (2299) 0x4b1f9c LDR	D17, [X5], #8

    (2299) 0x4b1fa0 FCMPE	D17, D23

    (2299) 0x4b1fa4 FADD	D3, D3, D17

    (2299) 0x4b1fa8 FCSEL	D23, D23, D17, #12

    (2299) 0x4b1fac LDR	D16, [X5], #8

    (2299) 0x4b1fb0 FCMPE	D16, D23

    (2299) 0x4b1fb4 FADD	D3, D3, D16

    (2299) 0x4b1fb8 FCSEL	D23, D23, D16, #12

    (2299) 0x4b1fbc LDR	D7, [X5], #8

    (2299) 0x4b1fc0 FCMPE	D7, D23

    (2299) 0x4b1fc4 FADD	D3, D3, D7

    (2299) 0x4b1fc8 FCSEL	D23, D23, D7, #12

    (2299) 0x4b1fcc LDR	D6, [X5], #8

    (2299) 0x4b1fd0 FCMPE	D6, D23

    (2299) 0x4b1fd4 FADD	D3, D3, D6

    (2299) 0x4b1fd8 FCSEL	D23, D23, D6, #12

    (2299) 0x4b1fdc LDR	D5, [X5], #8

    (2299) 0x4b1fe0 FCMPE	D5, D23

    (2299) 0x4b1fe4 FADD	D3, D3, D5

    (2299) 0x4b1fe8 FCSEL	D23, D23, D5, #12

    (2299) 0x4b1fec LDR	D2, [X5], #8

    (2299) 0x4b1ff0 FCMPE	D2, D23

    (2299) 0x4b1ff4 FADD	D3, D3, D2

    (2299) 0x4b1ff8 FCSEL	D23, D23, D2, #12

    (2299) 0x4b1ffc CMP	X5, X15

    (2299) 0x4b2000 B.EQ	4b208c

      (2308) 0x4b2004 ORR	X18, XZR, X5

      (2308) 0x4b2008 LDR	D27, [X5, #8]

      (2308) 0x4b200c LDR	D1, [X18], #8

      (2308) 0x4b2010 LDP	D20, D19, [X5, #24]

      (2308) 0x4b2014 LDP	D21, D22, [X5, #40]

      (2308) 0x4b2018 ADD	X5, X5, #64

      (2308) 0x4b201c FCMPE	D1, D23

      (2308) 0x4b2020 LDR	D29, [X18, #8]

      (2308) 0x4b2024 FADD	D0, D3, D1

      (2308) 0x4b2028 LDUR	D25, [X5, #504]

      (2308) 0x4b202c FADD	D26, D0, D27

      (2308) 0x4b2030 FCSEL	D24, D23, D1, #12

      (2308) 0x4b2034 FCMPE	D27, D24

      (2308) 0x4b2038 FADD	D30, D26, D29

      (2308) 0x4b203c FCSEL	D28, D24, D27, #12

      (2308) 0x4b2040 FADD	D18, D30, D20

      (2308) 0x4b2044 FCMPE	D29, D28

      (2308) 0x4b2048 FADD	D17, D18, D19

      (2308) 0x4b204c FCSEL	D16, D28, D29, #12

      (2308) 0x4b2050 FADD	D7, D17, D21

      (2308) 0x4b2054 FCMPE	D20, D16

      (2308) 0x4b2058 FADD	D6, D7, D22

      (2308) 0x4b205c FCSEL	D5, D16, D20, #12

      (2308) 0x4b2060 FADD	D3, D6, D25

      (2308) 0x4b2064 FCMPE	D19, D5

      (2308) 0x4b2068 FCSEL	D2, D5, D19, #12

      (2308) 0x4b206c FCMPE	D21, D2

      (2308) 0x4b2070 FCSEL	D23, D2, D21, #12

      (2308) 0x4b2074 FCMPE	D22, D23

      (2308) 0x4b2078 FCSEL	D1, D23, D22, #12

      (2308) 0x4b207c FCMPE	D25, D1

      (2308) 0x4b2080 FCSEL	D23, D1, D25, #12

      (2308) 0x4b2084 CMP	X5, X15

      (2308) 0x4b2088 B.NE	4b2004

    (2299) 0x4b208c LDR	X18, [X3]

    (2299) 0x4b2090 LDR	X15, [X12]

    (2299) 0x4b2094 CMP	X15, X18

    (2299) 0x4b2098 B.GE	4b21f4

    (2299) 0x4b209c ADD	X5, X23, X15,LSL #3

    (2299) 0x4b20a0 UBFM	X28, X15, #61, #60

    (2299) 0x4b20a4 ADD	X27, X23, X18,LSL #3

    (2299) 0x4b20a8 SUB	X11, X27, X5

    (2299) 0x4b20ac SUB	X11, X11, #8

    (2299) 0x4b20b0 UBFM	X11, X11, #3, #63

    (2299) 0x4b20b4 ADD	X11, X11, #1

    (2299) 0x4b20b8 ANDS	X11, X11, #4224

    (2299) 0x4b20bc B.EQ	4b216c

    (2299) 0x4b20c0 CMP	X11, #1

    (2299) 0x4b20c4 B.EQ	4b2154

    (2299) 0x4b20c8 CMP	X11, #2

    (2299) 0x4b20cc B.EQ	4b2144

    (2299) 0x4b20d0 CMP	X11, #3

    (2299) 0x4b20d4 B.EQ	4b2134

    (2299) 0x4b20d8 CMP	X11, #4

    (2299) 0x4b20dc B.EQ	4b2124

    (2299) 0x4b20e0 CMP	X11, #5

    (2299) 0x4b20e4 B.EQ	4b2114

    (2299) 0x4b20e8 CMP	X11, #6

    (2299) 0x4b20ec B.EQ	4b2104

    (2299) 0x4b20f0 LDR	D20, [X23, X28]

    (2299) 0x4b20f4 ADD	X5, X5, #8

    (2299) 0x4b20f8 FCMPE	D20, D23

    (2299) 0x4b20fc FADD	D3, D3, D20

    (2299) 0x4b2100 FCSEL	D23, D23, D20, #12

    (2299) 0x4b2104 LDR	D19, [X5], #8

    (2299) 0x4b2108 FCMPE	D19, D23

    (2299) 0x4b210c FADD	D3, D3, D19

    (2299) 0x4b2110 FCSEL	D23, D23, D19, #12

    (2299) 0x4b2114 LDR	D0, [X5], #8

    (2299) 0x4b2118 FCMPE	D0, D23

    (2299) 0x4b211c FADD	D3, D3, D0

    (2299) 0x4b2120 FCSEL	D23, D23, D0, #12

    (2299) 0x4b2124 LDR	D21, [X5], #8

    (2299) 0x4b2128 FCMPE	D21, D23

    (2299) 0x4b212c FADD	D3, D3, D21

    (2299) 0x4b2130 FCSEL	D23, D23, D21, #12

    (2299) 0x4b2134 LDR	D22, [X5], #8

    (2299) 0x4b2138 FCMPE	D22, D23

    (2299) 0x4b213c FADD	D3, D3, D22

    (2299) 0x4b2140 FCSEL	D23, D23, D22, #12

    (2299) 0x4b2144 LDR	D24, [X5], #8

    (2299) 0x4b2148 FCMPE	D24, D23

    (2299) 0x4b214c FADD	D3, D3, D24

    (2299) 0x4b2150 FCSEL	D23, D23, D24, #12

    (2299) 0x4b2154 LDR	D27, [X5], #8

    (2299) 0x4b2158 FCMPE	D27, D23

    (2299) 0x4b215c FADD	D3, D3, D27

    (2299) 0x4b2160 FCSEL	D23, D23, D27, #12

    (2299) 0x4b2164 CMP	X27, X5

    (2299) 0x4b2168 B.EQ	4b21f4

      (2307) 0x4b216c ORR	X28, XZR, X5

      (2307) 0x4b2170 LDR	D17, [X5, #8]

      (2307) 0x4b2174 LDR	D25, [X28], #8

      (2307) 0x4b2178 LDP	D26, D28, [X5, #24]

      (2307) 0x4b217c LDP	D29, D30, [X5, #40]

      (2307) 0x4b2180 ADD	X5, X5, #64

      (2307) 0x4b2184 FCMPE	D25, D23

      (2307) 0x4b2188 LDR	D5, [X28, #8]

      (2307) 0x4b218c FADD	D3, D3, D25

      (2307) 0x4b2190 LDUR	D16, [X5, #504]

      (2307) 0x4b2194 FADD	D7, D3, D17

      (2307) 0x4b2198 FCSEL	D18, D23, D25, #12

      (2307) 0x4b219c FCMPE	D17, D18

      (2307) 0x4b21a0 FADD	D2, D7, D5

      (2307) 0x4b21a4 FCSEL	D6, D18, D17, #12

      (2307) 0x4b21a8 FADD	D23, D2, D26

      (2307) 0x4b21ac FCMPE	D5, D6

      (2307) 0x4b21b0 FADD	D1, D23, D28

      (2307) 0x4b21b4 FCSEL	D20, D6, D5, #12

      (2307) 0x4b21b8 FADD	D19, D1, D29

      (2307) 0x4b21bc FCMPE	D26, D20

      (2307) 0x4b21c0 FADD	D0, D19, D30

      (2307) 0x4b21c4 FCSEL	D21, D20, D26, #12

      (2307) 0x4b21c8 FADD	D3, D0, D16

      (2307) 0x4b21cc FCMPE	D28, D21

      (2307) 0x4b21d0 FCSEL	D22, D21, D28, #12

      (2307) 0x4b21d4 FCMPE	D29, D22

      (2307) 0x4b21d8 FCSEL	D24, D22, D29, #12

      (2307) 0x4b21dc FCMPE	D30, D24

      (2307) 0x4b21e0 FCSEL	D27, D24, D30, #12

      (2307) 0x4b21e4 FCMPE	D16, D27

      (2307) 0x4b21e8 FCSEL	D23, D27, D16, #12

      (2307) 0x4b21ec CMP	X27, X5

      (2307) 0x4b21f0 B.NE	4b216c

    (2299) 0x4b21f4 FABS	D4, D4

    (2299) 0x4b21f8 SUB	X6, X9, X6

    (2299) 0x4b21fc FABS	D25, D3

    (2299) 0x4b2200 SUB	X9, X18, X15

    (2299) 0x4b2204 STR	X13, [X19, X14]

    (2299) 0x4b2208 LDP	X18, X15, [X0, #1016]

    (2299) 0x4b220c SUB	X14, X6, #1

    (2299) 0x4b2210 ADD	X2, X2, X9

    (2299) 0x4b2214 ADD	X1, X1, X14

    (2299) 0x4b2218 FMUL	D26, D4, D15

    (2299) 0x4b221c ADD	X27, X18, #1

    (2299) 0x4b2220 FCMPE	D26, D25

    (2299) 0x4b2224 B.MI	4b2c80

    (2299) 0x4b2228 CMP	X27, X15

    (2299) 0x4b222c B.GE	4b2264

    (2299) 0x4b2230 FMUL	D28, D14, D23

    (2299) 0x4b2234 HINT	#0

    (2299) 0x4b2238 HINT	#0

    (2299) 0x4b223c HINT	#0

      (2306) 0x4b2240 LDR	D3, [X22, X27,LSL #3]

      (2306) 0x4b2244 FCMPE	D3, D28

      (2306) 0x4b2248 B.GE	4b22c0

      (2306) 0x4b224c LDR	X11, [X25, X27,LSL #3]

      (2306) 0x4b2250 STR	X11, [X19, X27,LSL #3]

      (2306) 0x4b2254 ADD	X27, X27, #1

      (2306) 0x4b2258 LDR	X5, [X0]

      (2306) 0x4b225c CMP	X5, X27

      (2306) 0x4b2260 B.GT	4b2240

    (2299) 0x4b2264 LDR	X6, [X3]

    (2299) 0x4b2268 LDR	X18, [X12]

    (2299) 0x4b226c CMP	X18, X6

    (2299) 0x4b2270 B.GE	4b1dac

    (2299) 0x4b2274 FMUL	D29, D14, D23

    (2299) 0x4b2278 HINT	#0

    (2299) 0x4b227c HINT	#0

      (2305) 0x4b2280 LDR	D30, [X23, X18,LSL #3]

      (2305) 0x4b2284 FCMPE	D29, D30

      (2305) 0x4b2288 B.LS	4b22dc

      (2305) 0x4b228c LDR	X9, [X24, X18,LSL #3]

      (2305) 0x4b2290 STR	X9, [X20, X18,LSL #3]

      (2305) 0x4b2294 ADD	X18, X18, #1

      (2305) 0x4b2298 LDR	X14, [X3]

      (2305) 0x4b229c CMP	X14, X18

      (2305) 0x4b22a0 B.GT	4b2280

    (2299) 0x4b22a4 ADD	X4, X4, #1

    (2299) 0x4b22a8 ADD	X12, X12, #8

    (2299) 0x4b22ac ADD	X3, X3, #8

    (2299) 0x4b22b0 ADD	X0, X0, #8

    (2299) 0x4b22b4 CMP	X4, X30

    (2299) 0x4b22b8 B.NE	4b1870

(2300) 0x4b22bc B	4b1dc4

      (2306) 0x4b22c0 STR	X13, [X19, X27,LSL #3]

      (2306) 0x4b22c4 ADD	X27, X27, #1

      (2306) 0x4b22c8 SUB	X1, X1, #1

      (2306) 0x4b22cc LDR	X28, [X0]

      (2306) 0x4b22d0 CMP	X27, X28

      (2306) 0x4b22d4 B.LT	4b2240

    (2299) 0x4b22d8 B	4b2264

      (2305) 0x4b22dc STR	X13, [X20, X18,LSL #3]

      (2305) 0x4b22e0 ADD	X18, X18, #1

      (2305) 0x4b22e4 SUB	X2, X2, #1

      (2305) 0x4b22e8 LDR	X15, [X3]

      (2305) 0x4b22ec CMP	X18, X15

      (2305) 0x4b22f0 B.LT	4b2280

    (2299) 0x4b22f4 ADD	X4, X4, #1

    (2299) 0x4b22f8 ADD	X12, X12, #8

    (2299) 0x4b22fc ADD	X3, X3, #8

    (2299) 0x4b2300 ADD	X0, X0, #8

    (2299) 0x4b2304 CMP	X4, X30

    (2299) 0x4b2308 B.NE	4b1870

(2300) 0x4b230c B	4b1dc4

    (2299) 0x4b2310 CMP	X5, X9

    (2299) 0x4b2314 B.GE	4b2dc0

    (2299) 0x4b2318 SUB	X28, X9, X5

    (2299) 0x4b231c LDR	X11, [X21, X4,LSL #3]

    (2299) 0x4b2320 FMOV	D18, D4

    (2299) 0x4b2324 MOVI	D24, #0

    (2299) 0x4b2328 ANDS	X27, X28, #4224

    (2299) 0x4b232c B.EQ	4b2404

    (2299) 0x4b2330 CMP	X27, #1

    (2299) 0x4b2334 B.EQ	4b23d8

    (2299) 0x4b2338 CMP	X27, #2

    (2299) 0x4b233c B.EQ	4b23c4

    (2299) 0x4b2340 CMP	X27, #3

    (2299) 0x4b2344 B.EQ	4b23b0

    (2299) 0x4b2348 CMP	X27, #4

    (2299) 0x4b234c B.EQ	4b239c

    (2299) 0x4b2350 CMP	X27, #5

    (2299) 0x4b2354 B.EQ	4b2388

    (2299) 0x4b2358 CMP	X27, #6

    (2299) 0x4b235c B.EQ	4b2374

    (2299) 0x4b2360 LDR	X18, [X25, X5,LSL #3]

    (2299) 0x4b2364 LDR	X15, [X21, X18,LSL #3]

    (2299) 0x4b2368 CMP	X11, X15

    (2299) 0x4b236c B.EQ	4b2e68

    (2299) 0x4b2370 ADD	X5, X5, #1

    (2299) 0x4b2374 LDR	X28, [X25, X5,LSL #3]

    (2299) 0x4b2378 LDR	X27, [X21, X28,LSL #3]

    (2299) 0x4b237c CMP	X11, X27

    (2299) 0x4b2380 B.EQ	4b2e20

    (2299) 0x4b2384 ADD	X5, X5, #1

    (2299) 0x4b2388 LDR	X18, [X25, X5,LSL #3]

    (2299) 0x4b238c LDR	X15, [X21, X18,LSL #3]

    (2299) 0x4b2390 CMP	X11, X15

    (2299) 0x4b2394 B.EQ	4b2d64

    (2299) 0x4b2398 ADD	X5, X5, #1

    (2299) 0x4b239c LDR	X28, [X25, X5,LSL #3]

    (2299) 0x4b23a0 LDR	X27, [X21, X28,LSL #3]

    (2299) 0x4b23a4 CMP	X11, X27

    (2299) 0x4b23a8 B.EQ	4b2d50

    (2299) 0x4b23ac ADD	X5, X5, #1

    (2299) 0x4b23b0 LDR	X18, [X25, X5,LSL #3]

    (2299) 0x4b23b4 LDR	X15, [X21, X18,LSL #3]

    (2299) 0x4b23b8 CMP	X11, X15

    (2299) 0x4b23bc B.EQ	4b2cec

    (2299) 0x4b23c0 ADD	X5, X5, #1

    (2299) 0x4b23c4 LDR	X28, [X25, X5,LSL #3]

    (2299) 0x4b23c8 LDR	X27, [X21, X28,LSL #3]

    (2299) 0x4b23cc CMP	X11, X27

    (2299) 0x4b23d0 B.EQ	4b2cb0

    (2299) 0x4b23d4 ADD	X5, X5, #1

    (2299) 0x4b23d8 LDR	X18, [X25, X5,LSL #3]

    (2299) 0x4b23dc LDR	X15, [X21, X18,LSL #3]

    (2299) 0x4b23e0 CMP	X11, X15

    (2299) 0x4b23e4 B.NE	4b23f8

    (2299) 0x4b23e8 LDR	D7, [X22, X5,LSL #3]

    (2299) 0x4b23ec FCMPE	D7, D24

    (2299) 0x4b23f0 FADD	D18, D18, D7

    (2299) 0x4b23f4 FCSEL	D24, D7, D24, #12

    (2299) 0x4b23f8 ADD	X5, X5, #1

    (2299) 0x4b23fc CMP	X5, X9

    (2299) 0x4b2400 B.EQ	4b252c

      (2312) 0x4b2404 LDR	X28, [X25, X5,LSL #3]

      (2312) 0x4b2408 LDR	X27, [X21, X28,LSL #3]

      (2312) 0x4b240c CMP	X11, X27

      (2312) 0x4b2410 B.NE	4b2424

      (2312) 0x4b2414 LDR	D27, [X22, X5,LSL #3]

      (2312) 0x4b2418 FCMPE	D27, D24

      (2312) 0x4b241c FADD	D18, D18, D27

      (2312) 0x4b2420 FCSEL	D24, D27, D24, #12

      (2312) 0x4b2424 ADD	X5, X5, #1

      (2312) 0x4b2428 LDR	X18, [X25, X5,LSL #3]

      (2312) 0x4b242c LDR	X15, [X21, X18,LSL #3]

      (2312) 0x4b2430 CMP	X11, X15

      (2312) 0x4b2434 B.NE	4b2448

      (2312) 0x4b2438 LDR	D6, [X22, X5,LSL #3]

      (2312) 0x4b243c FCMPE	D6, D24

      (2312) 0x4b2440 FADD	D18, D18, D6

      (2312) 0x4b2444 FCSEL	D24, D6, D24, #12

      (2312) 0x4b2448 ADD	X28, X5, #1

      (2312) 0x4b244c LDR	X27, [X25, X28,LSL #3]

      (2312) 0x4b2450 LDR	X18, [X21, X27,LSL #3]

      (2312) 0x4b2454 CMP	X11, X18

      (2312) 0x4b2458 B.NE	4b246c

      (2312) 0x4b245c LDR	D5, [X22, X28,LSL #3]

      (2312) 0x4b2460 FCMPE	D5, D24

      (2312) 0x4b2464 FADD	D18, D18, D5

      (2312) 0x4b2468 FCSEL	D24, D5, D24, #12

      (2312) 0x4b246c ADD	X15, X5, #2

      (2312) 0x4b2470 LDR	X28, [X25, X15,LSL #3]

      (2312) 0x4b2474 LDR	X27, [X21, X28,LSL #3]

      (2312) 0x4b2478 CMP	X11, X27

      (2312) 0x4b247c B.NE	4b2490

      (2312) 0x4b2480 LDR	D2, [X22, X15,LSL #3]

      (2312) 0x4b2484 FCMPE	D2, D24

      (2312) 0x4b2488 FADD	D18, D18, D2

      (2312) 0x4b248c FCSEL	D24, D2, D24, #12

      (2312) 0x4b2490 ADD	X15, X5, #3

      (2312) 0x4b2494 LDR	X18, [X25, X15,LSL #3]

      (2312) 0x4b2498 LDR	X28, [X21, X18,LSL #3]

      (2312) 0x4b249c CMP	X11, X28

      (2312) 0x4b24a0 B.NE	4b24b4

      (2312) 0x4b24a4 LDR	D21, [X22, X15,LSL #3]

      (2312) 0x4b24a8 FCMPE	D21, D24

      (2312) 0x4b24ac FADD	D18, D18, D21

      (2312) 0x4b24b0 FCSEL	D24, D21, D24, #12

      (2312) 0x4b24b4 ADD	X27, X5, #4

      (2312) 0x4b24b8 LDR	X15, [X25, X27,LSL #3]

      (2312) 0x4b24bc LDR	X18, [X21, X15,LSL #3]

      (2312) 0x4b24c0 CMP	X11, X18

      (2312) 0x4b24c4 B.NE	4b24d8

      (2312) 0x4b24c8 LDR	D1, [X22, X27,LSL #3]

      (2312) 0x4b24cc FCMPE	D1, D24

      (2312) 0x4b24d0 FADD	D18, D18, D1

      (2312) 0x4b24d4 FCSEL	D24, D1, D24, #12

      (2312) 0x4b24d8 ADD	X28, X5, #5

      (2312) 0x4b24dc LDR	X27, [X25, X28,LSL #3]

      (2312) 0x4b24e0 LDR	X15, [X21, X27,LSL #3]

      (2312) 0x4b24e4 CMP	X11, X15

      (2312) 0x4b24e8 B.NE	4b24fc

      (2312) 0x4b24ec LDR	D20, [X22, X28,LSL #3]

      (2312) 0x4b24f0 FCMPE	D20, D24

      (2312) 0x4b24f4 FADD	D18, D18, D20

      (2312) 0x4b24f8 FCSEL	D24, D20, D24, #12

      (2312) 0x4b24fc ADD	X28, X5, #6

      (2312) 0x4b2500 LDR	X18, [X25, X28,LSL #3]

      (2312) 0x4b2504 LDR	X27, [X21, X18,LSL #3]

      (2312) 0x4b2508 CMP	X11, X27

      (2312) 0x4b250c B.NE	4b2520

      (2312) 0x4b2510 LDR	D0, [X22, X28,LSL #3]

      (2312) 0x4b2514 FCMPE	D0, D24

      (2312) 0x4b2518 FADD	D18, D18, D0

      (2312) 0x4b251c FCSEL	D24, D0, D24, #12

      (2312) 0x4b2520 ADD	X5, X5, #7

      (2312) 0x4b2524 CMP	X5, X9

      (2312) 0x4b2528 B.NE	4b2404

    (2299) 0x4b252c LDR	X18, [X3]

    (2299) 0x4b2530 LDR	X15, [X12]

    (2299) 0x4b2534 CMP	X15, X18

    (2299) 0x4b2538 B.GE	4b274c

    (2299) 0x4b253c SUB	X28, X18, X15

    (2299) 0x4b2540 LDR	X11, [X21, X4,LSL #3]

    (2299) 0x4b2544 ORR	X5, XZR, X15

    (2299) 0x4b2548 ANDS	X27, X28, #4224

    (2299) 0x4b254c B.EQ	4b2624

    (2299) 0x4b2550 CMP	X27, #1

    (2299) 0x4b2554 B.EQ	4b25f8

    (2299) 0x4b2558 CMP	X27, #2

    (2299) 0x4b255c B.EQ	4b25e4

    (2299) 0x4b2560 CMP	X27, #3

    (2299) 0x4b2564 B.EQ	4b25d0

    (2299) 0x4b2568 CMP	X27, #4

    (2299) 0x4b256c B.EQ	4b25bc

    (2299) 0x4b2570 CMP	X27, #5

    (2299) 0x4b2574 B.EQ	4b25a8

    (2299) 0x4b2578 CMP	X27, #6

    (2299) 0x4b257c B.EQ	4b2594

    (2299) 0x4b2580 LDR	X5, [X24, X15,LSL #3]

    (2299) 0x4b2584 LDR	X28, [X26, X5,LSL #3]

    (2299) 0x4b2588 CMP	X11, X28

    (2299) 0x4b258c B.EQ	4b2e7c

    (2299) 0x4b2590 ADD	X5, X15, #1

    (2299) 0x4b2594 LDR	X27, [X24, X5,LSL #3]

    (2299) 0x4b2598 LDR	X28, [X26, X27,LSL #3]

    (2299) 0x4b259c CMP	X11, X28

    (2299) 0x4b25a0 B.EQ	4b2e08

    (2299) 0x4b25a4 ADD	X5, X5, #1

    (2299) 0x4b25a8 LDR	X27, [X24, X5,LSL #3]

    (2299) 0x4b25ac LDR	X28, [X26, X27,LSL #3]

    (2299) 0x4b25b0 CMP	X11, X28

    (2299) 0x4b25b4 B.EQ	4b2d78

    (2299) 0x4b25b8 ADD	X5, X5, #1

    (2299) 0x4b25bc LDR	X27, [X24, X5,LSL #3]

    (2299) 0x4b25c0 LDR	X28, [X26, X27,LSL #3]

    (2299) 0x4b25c4 CMP	X11, X28

    (2299) 0x4b25c8 B.EQ	4b2d3c

    (2299) 0x4b25cc ADD	X5, X5, #1

    (2299) 0x4b25d0 LDR	X27, [X24, X5,LSL #3]

    (2299) 0x4b25d4 LDR	X28, [X26, X27,LSL #3]

    (2299) 0x4b25d8 CMP	X11, X28

    (2299) 0x4b25dc B.EQ	4b2d00

    (2299) 0x4b25e0 ADD	X5, X5, #1

    (2299) 0x4b25e4 LDR	X27, [X24, X5,LSL #3]

    (2299) 0x4b25e8 LDR	X28, [X26, X27,LSL #3]

    (2299) 0x4b25ec CMP	X11, X28

    (2299) 0x4b25f0 B.EQ	4b2c9c

    (2299) 0x4b25f4 ADD	X5, X5, #1

    (2299) 0x4b25f8 LDR	X27, [X24, X5,LSL #3]

    (2299) 0x4b25fc LDR	X28, [X26, X27,LSL #3]

    (2299) 0x4b2600 CMP	X11, X28

    (2299) 0x4b2604 B.NE	4b2618

    (2299) 0x4b2608 LDR	D29, [X23, X5,LSL #3]

    (2299) 0x4b260c FCMPE	D29, D24

    (2299) 0x4b2610 FADD	D18, D18, D29

    (2299) 0x4b2614 FCSEL	D24, D29, D24, #12

    (2299) 0x4b2618 ADD	X5, X5, #1

    (2299) 0x4b261c CMP	X5, X18

    (2299) 0x4b2620 B.EQ	4b274c

      (2311) 0x4b2624 LDR	X27, [X24, X5,LSL #3]

      (2311) 0x4b2628 LDR	X28, [X26, X27,LSL #3]

      (2311) 0x4b262c CMP	X11, X28

      (2311) 0x4b2630 B.NE	4b2644

      (2311) 0x4b2634 LDR	D23, [X23, X5,LSL #3]

      (2311) 0x4b2638 FCMPE	D23, D24

      (2311) 0x4b263c FADD	D18, D18, D23

      (2311) 0x4b2640 FCSEL	D24, D23, D24, #12

      (2311) 0x4b2644 ADD	X5, X5, #1

      (2311) 0x4b2648 LDR	X27, [X24, X5,LSL #3]

      (2311) 0x4b264c LDR	X28, [X26, X27,LSL #3]

      (2311) 0x4b2650 CMP	X11, X28

      (2311) 0x4b2654 B.NE	4b2668

      (2311) 0x4b2658 LDR	D30, [X23, X5,LSL #3]

      (2311) 0x4b265c FCMPE	D30, D24

      (2311) 0x4b2660 FADD	D18, D18, D30

      (2311) 0x4b2664 FCSEL	D24, D30, D24, #12

      (2311) 0x4b2668 ADD	X27, X5, #1

      (2311) 0x4b266c LDR	X28, [X24, X27,LSL #3]

      (2311) 0x4b2670 LDR	X28, [X26, X28,LSL #3]

      (2311) 0x4b2674 CMP	X11, X28

      (2311) 0x4b2678 B.NE	4b268c

      (2311) 0x4b267c LDR	D16, [X23, X27,LSL #3]

      (2311) 0x4b2680 FCMPE	D16, D24

      (2311) 0x4b2684 FADD	D18, D18, D16

      (2311) 0x4b2688 FCSEL	D24, D16, D24, #12

      (2311) 0x4b268c ADD	X27, X5, #2

      (2311) 0x4b2690 LDR	X28, [X24, X27,LSL #3]

      (2311) 0x4b2694 LDR	X28, [X26, X28,LSL #3]

      (2311) 0x4b2698 CMP	X11, X28

      (2311) 0x4b269c B.NE	4b26b0

      (2311) 0x4b26a0 LDR	D17, [X23, X27,LSL #3]

      (2311) 0x4b26a4 FCMPE	D17, D24

      (2311) 0x4b26a8 FADD	D18, D18, D17

      (2311) 0x4b26ac FCSEL	D24, D17, D24, #12

      (2311) 0x4b26b0 ADD	X27, X5, #3

      (2311) 0x4b26b4 LDR	X28, [X24, X27,LSL #3]

      (2311) 0x4b26b8 LDR	X28, [X26, X28,LSL #3]

      (2311) 0x4b26bc CMP	X11, X28

      (2311) 0x4b26c0 B.NE	4b26d4

      (2311) 0x4b26c4 LDR	D7, [X23, X27,LSL #3]

      (2311) 0x4b26c8 FCMPE	D7, D24

      (2311) 0x4b26cc FADD	D18, D18, D7

      (2311) 0x4b26d0 FCSEL	D24, D7, D24, #12

      (2311) 0x4b26d4 ADD	X27, X5, #4

      (2311) 0x4b26d8 LDR	X28, [X24, X27,LSL #3]

      (2311) 0x4b26dc LDR	X28, [X26, X28,LSL #3]

      (2311) 0x4b26e0 CMP	X11, X28

      (2311) 0x4b26e4 B.NE	4b26f8

      (2311) 0x4b26e8 LDR	D27, [X23, X27,LSL #3]

      (2311) 0x4b26ec FCMPE	D27, D24

      (2311) 0x4b26f0 FADD	D18, D18, D27

      (2311) 0x4b26f4 FCSEL	D24, D27, D24, #12

      (2311) 0x4b26f8 ADD	X27, X5, #5

      (2311) 0x4b26fc LDR	X28, [X24, X27,LSL #3]

      (2311) 0x4b2700 LDR	X28, [X26, X28,LSL #3]

      (2311) 0x4b2704 CMP	X11, X28

      (2311) 0x4b2708 B.NE	4b271c

      (2311) 0x4b270c LDR	D6, [X23, X27,LSL #3]

      (2311) 0x4b2710 FCMPE	D6, D24

      (2311) 0x4b2714 FADD	D18, D18, D6

      (2311) 0x4b2718 FCSEL	D24, D6, D24, #12

      (2311) 0x4b271c ADD	X27, X5, #6

      (2311) 0x4b2720 LDR	X28, [X24, X27,LSL #3]

      (2311) 0x4b2724 LDR	X28, [X26, X28,LSL #3]

      (2311) 0x4b2728 CMP	X11, X28

      (2311) 0x4b272c B.NE	4b2740

      (2311) 0x4b2730 LDR	D5, [X23, X27,LSL #3]

      (2311) 0x4b2734 FCMPE	D5, D24

      (2311) 0x4b2738 FADD	D18, D18, D5

      (2311) 0x4b273c FCSEL	D24, D5, D24, #12

      (2311) 0x4b2740 ADD	X5, X5, #7

      (2311) 0x4b2744 CMP	X5, X18

      (2311) 0x4b2748 B.NE	4b2624

    (2299) 0x4b274c FABS	D4, D4

    (2299) 0x4b2750 FABS	D2, D18

    (2299) 0x4b2754 STR	X13, [X19, X14]

    (2299) 0x4b2758 SUB	X14, X18, X15

    (2299) 0x4b275c SUB	X9, X9, X6

    (2299) 0x4b2760 LDP	X18, X15, [X0, #1016]

    (2299) 0x4b2764 SUB	X6, X9, #1

    (2299) 0x4b2768 ADD	X2, X2, X14

    (2299) 0x4b276c ADD	X1, X1, X6

    (2299) 0x4b2770 FMUL	D21, D4, D15

    (2299) 0x4b2774 ADD	X27, X18, #1

    (2299) 0x4b2778 FCMPE	D21, D2

    (2299) 0x4b277c B.MI	4b2c74

    (2299) 0x4b2780 CMP	X15, X27

    (2299) 0x4b2784 B.LE	4b27c8

    (2299) 0x4b2788 FMUL	D1, D14, D24

      (2310) 0x4b278c LDR	D20, [X22, X27,LSL #3]

      (2310) 0x4b2790 FCMPE	D1, D20

      (2310) 0x4b2794 B.GE	4b27ac

      (2310) 0x4b2798 LDR	X28, [X25, X27,LSL #3]

      (2310) 0x4b279c LDR	X15, [X21, X4,LSL #3]

      (2310) 0x4b27a0 LDR	X11, [X21, X28,LSL #3]

      (2310) 0x4b27a4 CMP	X11, X15

      (2310) 0x4b27a8 B.EQ	4b27b4

      (2310) 0x4b27ac SUB	X1, X1, #1

      (2310) 0x4b27b0 MOVN	X28, #0

      (2310) 0x4b27b4 STR	X28, [X19, X27,LSL #3]

      (2310) 0x4b27b8 ADD	X27, X27, #1

      (2310) 0x4b27bc LDR	X5, [X0]

      (2310) 0x4b27c0 CMP	X5, X27

      (2310) 0x4b27c4 B.GT	4b278c

    (2299) 0x4b27c8 LDR	X27, [X3]

    (2299) 0x4b27cc LDR	X18, [X12]

    (2299) 0x4b27d0 CMP	X18, X27

    (2299) 0x4b27d4 B.GE	4b1dac

    (2299) 0x4b27d8 FMUL	D0, D14, D24

    (2299) 0x4b27dc HINT	#0

      (2309) 0x4b27e0 LDR	D18, [X23, X18,LSL #3]

      (2309) 0x4b27e4 FCMPE	D0, D18

      (2309) 0x4b27e8 B.GE	4b2800

      (2309) 0x4b27ec LDR	X6, [X24, X18,LSL #3]

      (2309) 0x4b27f0 LDR	X9, [X21, X4,LSL #3]

      (2309) 0x4b27f4 LDR	X14, [X26, X6,LSL #3]

      (2309) 0x4b27f8 CMP	X14, X9

      (2309) 0x4b27fc B.EQ	4b2808

      (2309) 0x4b2800 SUB	X2, X2, #1

      (2309) 0x4b2804 MOVN	X6, #0

      (2309) 0x4b2808 STR	X6, [X20, X18,LSL #3]

      (2309) 0x4b280c ADD	X18, X18, #1

      (2309) 0x4b2810 LDR	X15, [X3]

      (2309) 0x4b2814 CMP	X15, X18

      (2309) 0x4b2818 B.GT	4b27e0

    (2299) 0x4b281c ADD	X4, X4, #1

    (2299) 0x4b2820 ADD	X12, X12, #8

    (2299) 0x4b2824 ADD	X3, X3, #8

    (2299) 0x4b2828 ADD	X0, X0, #8

    (2299) 0x4b282c CMP	X4, X30

    (2299) 0x4b2830 B.NE	4b1870

(2300) 0x4b2834 B	4b1dc4

(2300) 0x4b2838 FCMPE	D15, D31

(2300) 0x4b283c B.MI	4b2844

(2300) 0x4b2840 B	4b1d0c

  (2298) 0x4b2844 MOVN	X11, #0

  (2298) 0x4b2848 CMP	X27, X15

  (2298) 0x4b284c B.GE	4b286c

    (2319) 0x4b2850 STR	X11, [X19, X27,LSL #3]

    (2319) 0x4b2854 ADD	X27, X27, #1

    (2319) 0x4b2858 LDR	X15, [X0]

    (2319) 0x4b285c CMP	X15, X27

    (2319) 0x4b2860 B.GT	4b2850

  (2298) 0x4b2864 LDUR	X28, [X0, #504]

  (2298) 0x4b2868 ADD	X27, X28, #1

  (2298) 0x4b286c LDR	X14, [X3]

  (2298) 0x4b2870 SUB	X5, X15, X27

  (2298) 0x4b2874 MOVN	X27, #0

  (2298) 0x4b2878 SUB	X1, X1, X5

  (2298) 0x4b287c LDR	X9, [X12]

  (2298) 0x4b2880 CMP	X9, X14

  (2298) 0x4b2884 B.GE	4b28a0

    (2318) 0x4b2888 STR	X27, [X20, X9,LSL #3]

    (2318) 0x4b288c ADD	X9, X9, #1

    (2318) 0x4b2890 LDR	X14, [X3]

    (2318) 0x4b2894 CMP	X14, X9

    (2318) 0x4b2898 B.GT	4b2888

  (2298) 0x4b289c LDR	X9, [X12]

  (2298) 0x4b28a0 SUB	X6, X14, X9

  (2298) 0x4b28a4 ADD	X4, X4, #1

  (2298) 0x4b28a8 SUB	X2, X2, X6

  (2298) 0x4b28ac ADD	X12, X12, #8

  (2298) 0x4b28b0 ADD	X3, X3, #8

  (2298) 0x4b28b4 ADD	X0, X0, #8

  (2298) 0x4b28b8 CMP	X4, X30

  (2298) 0x4b28bc B.NE	4b1870

(2300) 0x4b28c0 B	4b1dc4

    (2299) 0x4b28c4 CMP	X5, X9

    (2299) 0x4b28c8 B.GE	4b2e90

    (2299) 0x4b28cc ADD	X28, X22, X9,LSL #3

    (2299) 0x4b28d0 ADD	X27, X14, #8

    (2299) 0x4b28d4 FMOV	D23, D4

    (2299) 0x4b28d8 MOVI	D21, #0

    (2299) 0x4b28dc ADD	X5, X22, X27

    (2299) 0x4b28e0 SUB	X11, X28, X5

    (2299) 0x4b28e4 SUB	X18, X11, #8

    (2299) 0x4b28e8 UBFM	X15, X18, #3, #63

    (2299) 0x4b28ec ADD	X11, X15, #1

    (2299) 0x4b28f0 ANDS	X18, X11, #4224

    (2299) 0x4b28f4 B.EQ	4b2990

    (2299) 0x4b28f8 CMP	X18, #1

    (2299) 0x4b28fc B.EQ	4b2978

    (2299) 0x4b2900 CMP	X18, #2

    (2299) 0x4b2904 B.EQ	4b2968

    (2299) 0x4b2908 CMP	X18, #3

    (2299) 0x4b290c B.EQ	4b2958

    (2299) 0x4b2910 CMP	X18, #4

    (2299) 0x4b2914 B.EQ	4b2948

    (2299) 0x4b2918 CMP	X18, #5

    (2299) 0x4b291c B.EQ	4b2938

    (2299) 0x4b2920 CMP	X18, #6

    (2299) 0x4b2924 B.NE	4b2dd8

    (2299) 0x4b2928 LDR	D17, [X5], #8

    (2299) 0x4b292c FCMPE	D17, D21

    (2299) 0x4b2930 FADD	D23, D23, D17

    (2299) 0x4b2934 FCSEL	D21, D17, D21, #12

    (2299) 0x4b2938 LDR	D16, [X5], #8

    (2299) 0x4b293c FCMPE	D16, D21

    (2299) 0x4b2940 FADD	D23, D23, D16

    (2299) 0x4b2944 FCSEL	D21, D16, D21, #12

    (2299) 0x4b2948 LDR	D7, [X5], #8

    (2299) 0x4b294c FCMPE	D7, D21

    (2299) 0x4b2950 FADD	D23, D23, D7

    (2299) 0x4b2954 FCSEL	D21, D7, D21, #12

    (2299) 0x4b2958 LDR	D6, [X5], #8

    (2299) 0x4b295c FCMPE	D6, D21

    (2299) 0x4b2960 FADD	D23, D23, D6

    (2299) 0x4b2964 FCSEL	D21, D6, D21, #12

    (2299) 0x4b2968 LDR	D5, [X5], #8

    (2299) 0x4b296c FCMPE	D5, D21

    (2299) 0x4b2970 FADD	D23, D23, D5

    (2299) 0x4b2974 FCSEL	D21, D5, D21, #12

    (2299) 0x4b2978 LDR	D2, [X5], #8

    (2299) 0x4b297c FCMPE	D2, D21

    (2299) 0x4b2980 FADD	D23, D23, D2

    (2299) 0x4b2984 FCSEL	D21, D2, D21, #12

    (2299) 0x4b2988 CMP	X5, X28

    (2299) 0x4b298c B.EQ	4b2a18

      (2304) 0x4b2990 ORR	X27, XZR, X5

      (2304) 0x4b2994 LDR	D19, [X5, #8]

      (2304) 0x4b2998 LDR	D1, [X27], #8

      (2304) 0x4b299c LDP	D20, D0, [X5, #24]

      (2304) 0x4b29a0 LDP	D24, D25, [X5, #40]

      (2304) 0x4b29a4 ADD	X5, X5, #64

      (2304) 0x4b29a8 FCMPE	D1, D21

      (2304) 0x4b29ac LDR	D3, [X27, #8]

      (2304) 0x4b29b0 FADD	D22, D23, D1

      (2304) 0x4b29b4 LDUR	D28, [X5, #504]

      (2304) 0x4b29b8 FADD	D27, D22, D19

      (2304) 0x4b29bc FCSEL	D26, D1, D21, #12

      (2304) 0x4b29c0 FCMPE	D19, D26

      (2304) 0x4b29c4 FADD	D30, D27, D3

      (2304) 0x4b29c8 FCSEL	D29, D19, D26, #12

      (2304) 0x4b29cc FADD	D18, D30, D20

      (2304) 0x4b29d0 FCMPE	D3, D29

      (2304) 0x4b29d4 FADD	D17, D18, D0

      (2304) 0x4b29d8 FCSEL	D16, D3, D29, #12

      (2304) 0x4b29dc FADD	D7, D17, D24

      (2304) 0x4b29e0 FCMPE	D20, D16

      (2304) 0x4b29e4 FADD	D6, D7, D25

      (2304) 0x4b29e8 FCSEL	D5, D20, D16, #12

      (2304) 0x4b29ec FADD	D23, D6, D28

      (2304) 0x4b29f0 FCMPE	D0, D5

      (2304) 0x4b29f4 FCSEL	D2, D0, D5, #12

      (2304) 0x4b29f8 FCMPE	D24, D2

      (2304) 0x4b29fc FCSEL	D21, D24, D2, #12

      (2304) 0x4b2a00 FCMPE	D25, D21

      (2304) 0x4b2a04 FCSEL	D1, D25, D21, #12

      (2304) 0x4b2a08 FCMPE	D28, D1

      (2304) 0x4b2a0c FCSEL	D21, D28, D1, #12

      (2304) 0x4b2a10 CMP	X5, X28

      (2304) 0x4b2a14 B.NE	4b2990

    (2299) 0x4b2a18 LDR	X18, [X3]

    (2299) 0x4b2a1c LDR	X15, [X12]

    (2299) 0x4b2a20 CMP	X15, X18

    (2299) 0x4b2a24 B.GE	4b2b6c

    (2299) 0x4b2a28 ADD	X5, X23, X15,LSL #3

    (2299) 0x4b2a2c UBFM	X28, X15, #61, #60

    (2299) 0x4b2a30 ADD	X27, X23, X18,LSL #3

    (2299) 0x4b2a34 SUB	X11, X27, X5

    (2299) 0x4b2a38 SUB	X11, X11, #8

    (2299) 0x4b2a3c UBFM	X11, X11, #3, #63

    (2299) 0x4b2a40 ADD	X11, X11, #1

    (2299) 0x4b2a44 ANDS	X11, X11, #4224

    (2299) 0x4b2a48 B.EQ	4b2ae4

    (2299) 0x4b2a4c CMP	X11, #1

    (2299) 0x4b2a50 B.EQ	4b2acc

    (2299) 0x4b2a54 CMP	X11, #2

    (2299) 0x4b2a58 B.EQ	4b2abc

    (2299) 0x4b2a5c CMP	X11, #3

    (2299) 0x4b2a60 B.EQ	4b2aac

    (2299) 0x4b2a64 CMP	X11, #4

    (2299) 0x4b2a68 B.EQ	4b2a9c

    (2299) 0x4b2a6c CMP	X11, #5

    (2299) 0x4b2a70 B.EQ	4b2a8c

    (2299) 0x4b2a74 CMP	X11, #6

    (2299) 0x4b2a78 B.NE	4b2df0

    (2299) 0x4b2a7c LDR	D0, [X5], #8

    (2299) 0x4b2a80 FCMPE	D0, D21

    (2299) 0x4b2a84 FADD	D23, D23, D0

    (2299) 0x4b2a88 FCSEL	D21, D0, D21, #12

    (2299) 0x4b2a8c LDR	D22, [X5], #8

    (2299) 0x4b2a90 FCMPE	D22, D21

    (2299) 0x4b2a94 FADD	D23, D23, D22

    (2299) 0x4b2a98 FCSEL	D21, D22, D21, #12

    (2299) 0x4b2a9c LDR	D24, [X5], #8

    (2299) 0x4b2aa0 FCMPE	D24, D21

    (2299) 0x4b2aa4 FADD	D23, D23, D24

    (2299) 0x4b2aa8 FCSEL	D21, D24, D21, #12

    (2299) 0x4b2aac LDR	D25, [X5], #8

    (2299) 0x4b2ab0 FCMPE	D25, D21

    (2299) 0x4b2ab4 FADD	D23, D23, D25

    (2299) 0x4b2ab8 FCSEL	D21, D25, D21, #12

    (2299) 0x4b2abc LDR	D26, [X5], #8

    (2299) 0x4b2ac0 FCMPE	D26, D21

    (2299) 0x4b2ac4 FADD	D23, D23, D26

    (2299) 0x4b2ac8 FCSEL	D21, D26, D21, #12

    (2299) 0x4b2acc LDR	D19, [X5], #8

    (2299) 0x4b2ad0 FCMPE	D19, D21

    (2299) 0x4b2ad4 FADD	D23, D23, D19

    (2299) 0x4b2ad8 FCSEL	D21, D19, D21, #12

    (2299) 0x4b2adc CMP	X27, X5

    (2299) 0x4b2ae0 B.EQ	4b2b6c

      (2303) 0x4b2ae4 ORR	X28, XZR, X5

      (2303) 0x4b2ae8 LDR	D18, [X5, #8]

      (2303) 0x4b2aec LDR	D28, [X28], #8

      (2303) 0x4b2af0 LDP	D29, D3, [X5, #24]

      (2303) 0x4b2af4 LDP	D30, D16, [X5, #40]

      (2303) 0x4b2af8 ADD	X5, X5, #64

      (2303) 0x4b2afc FCMPE	D28, D21

      (2303) 0x4b2b00 LDR	D5, [X28, #8]

      (2303) 0x4b2b04 FADD	D23, D23, D28

      (2303) 0x4b2b08 LDUR	D7, [X5, #504]

      (2303) 0x4b2b0c FADD	D27, D23, D18

      (2303) 0x4b2b10 FCSEL	D17, D28, D21, #12

      (2303) 0x4b2b14 FCMPE	D18, D17

      (2303) 0x4b2b18 FADD	D2, D27, D5

      (2303) 0x4b2b1c FCSEL	D6, D18, D17, #12

      (2303) 0x4b2b20 FADD	D21, D2, D29

      (2303) 0x4b2b24 FCMPE	D5, D6

      (2303) 0x4b2b28 FADD	D1, D21, D3

      (2303) 0x4b2b2c FCSEL	D20, D5, D6, #12

      (2303) 0x4b2b30 FADD	D0, D1, D30

      (2303) 0x4b2b34 FCMPE	D29, D20

      (2303) 0x4b2b38 FADD	D22, D0, D16

      (2303) 0x4b2b3c FCSEL	D24, D29, D20, #12

      (2303) 0x4b2b40 FADD	D23, D22, D7

      (2303) 0x4b2b44 FCMPE	D3, D24

      (2303) 0x4b2b48 FCSEL	D25, D3, D24, #12

      (2303) 0x4b2b4c FCMPE	D30, D25

      (2303) 0x4b2b50 FCSEL	D26, D30, D25, #12

      (2303) 0x4b2b54 FCMPE	D16, D26

      (2303) 0x4b2b58 FCSEL	D19, D16, D26, #12

      (2303) 0x4b2b5c FCMPE	D7, D19

      (2303) 0x4b2b60 FCSEL	D21, D7, D19, #12

      (2303) 0x4b2b64 CMP	X27, X5

      (2303) 0x4b2b68 B.NE	4b2ae4

    (2299) 0x4b2b6c FABS	D4, D4

    (2299) 0x4b2b70 SUB	X6, X9, X6

    (2299) 0x4b2b74 FABS	D28, D23

    (2299) 0x4b2b78 SUB	X9, X18, X15

    (2299) 0x4b2b7c STR	X13, [X19, X14]

    (2299) 0x4b2b80 LDP	X18, X15, [X0, #1016]

    (2299) 0x4b2b84 SUB	X14, X6, #1

    (2299) 0x4b2b88 ADD	X2, X2, X9

    (2299) 0x4b2b8c ADD	X1, X1, X14

    (2299) 0x4b2b90 FMUL	D29, D4, D15

    (2299) 0x4b2b94 ADD	X27, X18, #1

    (2299) 0x4b2b98 FCMPE	D28, D29

    (2299) 0x4b2b9c B.GT	4b2c8c

    (2299) 0x4b2ba0 CMP	X27, X15

    (2299) 0x4b2ba4 B.GE	4b2bd0

    (2299) 0x4b2ba8 FMUL	D23, D14, D21

      (2302) 0x4b2bac LDR	D30, [X22, X27,LSL #3]

      (2302) 0x4b2bb0 FCMPE	D23, D30

      (2302) 0x4b2bb4 B.GE	4b2c24

      (2302) 0x4b2bb8 LDR	X15, [X25, X27,LSL #3]

      (2302) 0x4b2bbc STR	X15, [X19, X27,LSL #3]

      (2302) 0x4b2bc0 ADD	X27, X27, #1

      (2302) 0x4b2bc4 LDR	X11, [X0]

      (2302) 0x4b2bc8 CMP	X11, X27

      (2302) 0x4b2bcc B.GT	4b2bac

    (2299) 0x4b2bd0 LDR	X27, [X3]

    (2299) 0x4b2bd4 LDR	X9, [X12]

    (2299) 0x4b2bd8 CMP	X9, X27

    (2299) 0x4b2bdc B.GE	4b1dac

    (2299) 0x4b2be0 FMUL	D16, D14, D21

      (2301) 0x4b2be4 LDR	D17, [X23, X9,LSL #3]

      (2301) 0x4b2be8 FCMPE	D16, D17

      (2301) 0x4b2bec B.GE	4b2c40

      (2301) 0x4b2bf0 LDR	X28, [X24, X9,LSL #3]

      (2301) 0x4b2bf4 STR	X28, [X20, X9,LSL #3]

      (2301) 0x4b2bf8 ADD	X9, X9, #1

      (2301) 0x4b2bfc LDR	X6, [X3]

      (2301) 0x4b2c00 CMP	X6, X9

      (2301) 0x4b2c04 B.GT	4b2be4

    (2299) 0x4b2c08 ADD	X4, X4, #1

    (2299) 0x4b2c0c ADD	X12, X12, #8

    (2299) 0x4b2c10 ADD	X3, X3, #8

    (2299) 0x4b2c14 ADD	X0, X0, #8

    (2299) 0x4b2c18 CMP	X4, X30

    (2299) 0x4b2c1c B.NE	4b1870

(2300) 0x4b2c20 B	4b1dc4

      (2302) 0x4b2c24 STR	X13, [X19, X27,LSL #3]

      (2302) 0x4b2c28 ADD	X27, X27, #1

      (2302) 0x4b2c2c SUB	X1, X1, #1

      (2302) 0x4b2c30 LDR	X5, [X0]

      (2302) 0x4b2c34 CMP	X5, X27

      (2302) 0x4b2c38 B.GT	4b2bac

    (2299) 0x4b2c3c B	4b2bd0

      (2301) 0x4b2c40 STR	X13, [X20, X9,LSL #3]

      (2301) 0x4b2c44 ADD	X9, X9, #1

      (2301) 0x4b2c48 SUB	X2, X2, #1

      (2301) 0x4b2c4c LDR	X14, [X3]

      (2301) 0x4b2c50 CMP	X14, X9

      (2301) 0x4b2c54 B.GT	4b2be4

    (2299) 0x4b2c58 ADD	X4, X4, #1

    (2299) 0x4b2c5c ADD	X12, X12, #8

    (2299) 0x4b2c60 ADD	X3, X3, #8

    (2299) 0x4b2c64 ADD	X0, X0, #8

    (2299) 0x4b2c68 CMP	X4, X30

    (2299) 0x4b2c6c B.NE	4b1870

(2300) 0x4b2c70 B	4b1dc4

    (2299) 0x4b2c74 FCMPE	D15, D31

    (2299) 0x4b2c78 B.MI	4b2844

    (2299) 0x4b2c7c B	4b2780

    (2299) 0x4b2c80 FCMPE	D15, D31

    (2299) 0x4b2c84 B.MI	4b2844

    (2299) 0x4b2c88 B	4b2228

    (2299) 0x4b2c8c FMOV	D3, #1.0000000

    (2299) 0x4b2c90 FCMPE	D15, D3

    (2299) 0x4b2c94 B.MI	4b2844

    (2299) 0x4b2c98 B	4b2ba0

    (2299) 0x4b2c9c LDR	D22, [X23, X5,LSL #3]

    (2299) 0x4b2ca0 FCMPE	D22, D24

    (2299) 0x4b2ca4 FADD	D18, D18, D22

    (2299) 0x4b2ca8 FCSEL	D24, D22, D24, #12

    (2299) 0x4b2cac B	4b25f4

    (2299) 0x4b2cb0 LDR	D17, [X22, X5,LSL #3]

    (2299) 0x4b2cb4 FCMPE	D17, D24

    (2299) 0x4b2cb8 FADD	D18, D18, D17

    (2299) 0x4b2cbc FCSEL	D24, D17, D24, #12

    (2299) 0x4b2cc0 B	4b23d4

    (2317) 0x4b2cc4 LDR	D6, [X22, X5,LSL #3]

    (2317) 0x4b2cc8 FCMPE	D6, D22

    (2317) 0x4b2ccc FADD	D3, D3, D6

    (2317) 0x4b2cd0 FCSEL	D22, D22, D6, #12

    (2317) 0x4b2cd4 B	4b1938

(2300) 0x4b2cd8 LDR	D16, [X23, X5,LSL #3]

(2300) 0x4b2cdc FCMPE	D16, D22

(2300) 0x4b2ce0 FADD	D3, D3, D16

(2300) 0x4b2ce4 FCSEL	D22, D22, D16, #12

(2300) 0x4b2ce8 B	4b1b58

    (2299) 0x4b2cec LDR	D16, [X22, X5,LSL #3]

    (2299) 0x4b2cf0 FCMPE	D16, D24

    (2299) 0x4b2cf4 FADD	D18, D18, D16

    (2299) 0x4b2cf8 FCSEL	D24, D16, D24, #12

    (2299) 0x4b2cfc B	4b23c0

    (2299) 0x4b2d00 LDR	D3, [X23, X5,LSL #3]

    (2299) 0x4b2d04 FCMPE	D3, D24

    (2299) 0x4b2d08 FADD	D18, D18, D3

    (2299) 0x4b2d0c FCSEL	D24, D3, D24, #12

    (2299) 0x4b2d10 B	4b25e0

(2300) 0x4b2d14 LDR	D30, [X23, X5,LSL #3]

(2300) 0x4b2d18 FCMPE	D30, D22

(2300) 0x4b2d1c FADD	D3, D3, D30

(2300) 0x4b2d20 FCSEL	D22, D22, D30, #12

(2300) 0x4b2d24 B	4b1b44

    (2317) 0x4b2d28 LDR	D27, [X22, X5,LSL #3]

    (2317) 0x4b2d2c FCMPE	D27, D22

    (2317) 0x4b2d30 FADD	D3, D3, D27

    (2317) 0x4b2d34 FCSEL	D22, D22, D27, #12

    (2317) 0x4b2d38 B	4b1924

    (2299) 0x4b2d3c LDR	D28, [X23, X5,LSL #3]

    (2299) 0x4b2d40 FCMPE	D28, D24

    (2299) 0x4b2d44 FADD	D18, D18, D28

    (2299) 0x4b2d48 FCSEL	D24, D28, D24, #12

    (2299) 0x4b2d4c B	4b25cc

    (2299) 0x4b2d50 LDR	D30, [X22, X5,LSL #3]

    (2299) 0x4b2d54 FCMPE	D30, D24

    (2299) 0x4b2d58 FADD	D18, D18, D30

    (2299) 0x4b2d5c FCSEL	D24, D30, D24, #12

    (2299) 0x4b2d60 B	4b23ac

    (2299) 0x4b2d64 LDR	D23, [X22, X5,LSL #3]

    (2299) 0x4b2d68 FCMPE	D23, D24

    (2299) 0x4b2d6c FADD	D18, D18, D23

    (2299) 0x4b2d70 FCSEL	D24, D23, D24, #12

    (2299) 0x4b2d74 B	4b2398

    (2299) 0x4b2d78 LDR	D19, [X23, X5,LSL #3]

    (2299) 0x4b2d7c FCMPE	D19, D24

    (2299) 0x4b2d80 FADD	D18, D18, D19

    (2299) 0x4b2d84 FCSEL	D24, D19, D24, #12

    (2299) 0x4b2d88 B	4b25b8

(2300) 0x4b2d8c LDR	D23, [X23, X5,LSL #3]

(2300) 0x4b2d90 FCMPE	D23, D22

(2300) 0x4b2d94 FADD	D3, D3, D23

(2300) 0x4b2d98 FCSEL	D22, D22, D23, #12

(2300) 0x4b2d9c B	4b1b30

    (2317) 0x4b2da0 LDR	D7, [X22, X5,LSL #3]

    (2317) 0x4b2da4 FCMPE	D7, D22

    (2317) 0x4b2da8 FADD	D3, D3, D7

    (2317) 0x4b2dac FCSEL	D22, D22, D7, #12

    (2317) 0x4b2db0 B	4b1910

  (2313) 0x4b2db4 FMOV	D3, D4

  (2313) 0x4b2db8 MOVI	D22, #0

  (2313) 0x4b2dbc B	4b1ab8

    (2299) 0x4b2dc0 FMOV	D18, D4

    (2299) 0x4b2dc4 MOVI	D24, #0

    (2299) 0x4b2dc8 B	4b252c

    (2299) 0x4b2dcc FMOV	D3, D4

    (2299) 0x4b2dd0 MOVI	D23, #0

    (2299) 0x4b2dd4 B	4b208c

    (2299) 0x4b2dd8 LDR	D18, [X22, X27]

    (2299) 0x4b2ddc ADD	X5, X5, #8

    (2299) 0x4b2de0 FCMPE	D18, #0

    (2299) 0x4b2de4 FADD	D23, D4, D18

    (2299) 0x4b2de8 FCSEL	D21, D18, D21, #12

    (2299) 0x4b2dec B	4b2928

    (2299) 0x4b2df0 LDR	D20, [X23, X28]

    (2299) 0x4b2df4 ADD	X5, X5, #8

    (2299) 0x4b2df8 FCMPE	D20, D21

    (2299) 0x4b2dfc FADD	D23, D23, D20

    (2299) 0x4b2e00 FCSEL	D21, D20, D21, #12

    (2299) 0x4b2e04 B	4b2a7c

    (2299) 0x4b2e08 LDR	D26, [X23, X5,LSL #3]

    (2299) 0x4b2e0c ADD	X5, X5, #1

    (2299) 0x4b2e10 FCMPE	D26, D24

    (2299) 0x4b2e14 FADD	D18, D18, D26

    (2299) 0x4b2e18 FCSEL	D24, D26, D24, #12

    (2299) 0x4b2e1c B	4b25a8

    (2299) 0x4b2e20 LDR	D29, [X22, X5,LSL #3]

    (2299) 0x4b2e24 ADD	X5, X5, #1

    (2299) 0x4b2e28 FCMPE	D29, D24

    (2299) 0x4b2e2c FADD	D18, D18, D29

    (2299) 0x4b2e30 FCSEL	D24, D29, D24, #12

    (2299) 0x4b2e34 B	4b2388

    (2317) 0x4b2e38 LDR	D18, [X22, X5,LSL #3]

    (2317) 0x4b2e3c ADD	X5, X5, #1

    (2317) 0x4b2e40 FCMPE	D18, #0

    (2317) 0x4b2e44 FADD	D3, D4, D18

    (2317) 0x4b2e48 FCSEL	D22, D22, D18, #12

    (2317) 0x4b2e4c B	4b1900

(2300) 0x4b2e50 LDR	D29, [X23, X15,LSL #3]

(2300) 0x4b2e54 ADD	X5, X15, #1

(2300) 0x4b2e58 FCMPE	D29, D22

(2300) 0x4b2e5c FADD	D3, D3, D29

(2300) 0x4b2e60 FCSEL	D22, D22, D29, #12

(2300) 0x4b2e64 B	4b1b20

    (2299) 0x4b2e68 LDR	D22, [X22, X5,LSL #3]

    (2299) 0x4b2e6c FCMPE	D22, #0

    (2299) 0x4b2e70 FADD	D18, D4, D22

    (2299) 0x4b2e74 FCSEL	D24, D22, D24, #12

    (2299) 0x4b2e78 B	4b2370

    (2299) 0x4b2e7c LDR	D25, [X23, X15,LSL #3]

    (2299) 0x4b2e80 FCMPE	D25, D24

    (2299) 0x4b2e84 FADD	D18, D18, D25

    (2299) 0x4b2e88 FCSEL	D24, D25, D24, #12

    (2299) 0x4b2e8c B	4b2590

    (2299) 0x4b2e90 FMOV	D23, D4

    (2299) 0x4b2e94 MOVI	D21, #0

    (2299) 0x4b2e98 B	4b2a18

0x4b2e9c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.44+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-355,363-369,376-382,392-398,405-411,424-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.83 to 1.50 cycles (7.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 79% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 10.83 to 9.50 cycles (1.14x speedup).

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
5% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.83 to 0.50 cycles (21.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 232 bytes. The binary function is storing 224 bytes.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	2.67	2.67	2.67	2.67	2.67	2.67	0.50	0.50	0.50	0.50	10.83	10.50	10.67	8.00	8.00
cycles	1.00	1.00	2.67	2.67	2.67	2.67	2.67	2.67	0.50	0.50	0.50	0.50	10.83	10.50	10.67	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Overall L1	10.83

Vectorization ratios

INT

all	5%
load	7%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	7%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.83 cycles. At this rate:

22% of peak load performance is reached (21.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (20.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4b17ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #816]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X3, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, SP, #184	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP X5, X2, [X3, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP D14, D15, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP X5, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X2, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X21, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X22, [X3, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X23, [X3, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X7, X28, [X3, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X24, [X3, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X27, [X3, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X6, [X3, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X20, [X3, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 52df80 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP XZR, XZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X4, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X8, X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B.GE 4b1dd0 <hypre_BoomerAMGCreateS._omp_fn.1+0x624>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X12, X15, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X16, X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MOVN X13, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X15, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X10, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.83 to 1.50 cycles (7.22x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
5% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.83 to 0.50 cycles (21.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 232 bytes. The binary function is storing 224 bytes.

General properties

nb instructions	50
loop length	200
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	2.67	2.67	2.67	2.67	2.67	2.67	0.50	0.50	0.50	0.50	10.83	10.50	10.67	8.00	8.00
cycles	1.00	1.00	2.67	2.67	2.67	2.67	2.67	2.67	0.50	0.50	0.50	0.50	10.83	10.50	10.67	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Overall L1	10.83

Vectorization ratios

INT

all	5%
load	7%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	7%
store	5%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.83 cycles. At this rate:

22% of peak load performance is reached (21.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
43% of peak store performance is reached (20.68 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4b17ac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #816]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X3, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, SP, #184	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP X5, X2, [X3, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP D14, D15, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP X5, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X2, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X21, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X22, [X3, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X23, [X3, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X7, X28, [X3, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X24, [X3, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X27, [X3, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X26, X6, [X3, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X20, [X3, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
BL 52df80 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP XZR, XZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X4, X30	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X18, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X8, X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B.GE 4b1dd0 <hypre_BoomerAMGCreateS._omp_fn.1+0x624>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X12, X15, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X16, X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MOVN X13, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X15, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X10, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, X28, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreateS._omp_fn.1–	0.45	0.07
▼Loop 2300 - par_strength.c:246-513 - exec–	0.00	0.00
▼Loop 2323 - par_strength.c:492-513 - exec–	0.01	0.01
○Loop 2326 - par_strength.c:498-503 - exec	0.12	0.02
▼Loop 2324 - par_strength.c:508-513 - exec–	0.00	0.00
○Loop 2325 - par_strength.c:508-513 - exec	0.00	0.00
▼Loop 2313 - par_strength.c:264-297 - exec–	0.00	0.00
○Loop 2314 - par_strength.c:289-294 - exec	0.00	0.00
▼Loop 2316 - par_strength.c:264-294 - exec–	0.00	0.00
▼Loop 2317 - par_strength.c:264-294 - exec–	0.00	0.00
○Loop 2315 - par_strength.c:264-291 - exec	0.00	0.00
▼Loop 2298 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2299 - par_strength.c:253-472 - exec–	0.09	0.01
○Loop 2306 - par_strength.c:451-460 - exec	0.20	0.03
○Loop 2308 - par_strength.c:324-327 - exec	0.03	0.01
○Loop 2310 - par_strength.c:363-369 - exec	0.00	0.00
○Loop 2305 - par_strength.c:463-472 - exec	0.00	0.00
○Loop 2304 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2302 - par_strength.c:424-433 - exec	0.00	0.00
○Loop 2303 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2312 - par_strength.c:270-275 - exec	0.00	0.00
○Loop 2309 - par_strength.c:376-382 - exec	0.00	0.00
○Loop 2301 - par_strength.c:436-445 - exec	0.00	0.00
○Loop 2311 - par_strength.c:278-283 - exec	0.00	0.00
○Loop 2307 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 2319 - par_strength.c:345-347 - exec	0.00	0.00
○Loop 2318 - par_strength.c:351-353 - exec	0.00	0.00
○Loop 2320 - par_strength.c:405-411 - exec	0.00	0.00
○Loop 2321 - par_strength.c:392-398 - exec	0.00	0.00
○Loop 2322 - par_strength.c:297-302 - exec	0.00	0.00

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Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code