OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.9	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.27% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1584:            tmp_marker = NULL;

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

1600:            {  thread_stop = pass_pointer[1] + pass_length; }

1601:            else

1602:            {  thread_stop = pass_pointer[1] + (pass_length/num_threads)*(my_thread_num+1); }

1603:

1604:            /* determine P for points of pass 1, i.e. neighbors of coarse points */

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x45c260 STP	X29, X30, [SP, #736]!

0x45c264 ADD	X29, SP, #0

0x45c268 STP	X19, X20, [SP, #16]

0x45c26c STP	X21, X22, [SP, #32]

0x45c270 STP	X23, X24, [SP, #48]

0x45c274 STP	X25, X26, [SP, #64]

0x45c278 STP	X27, X28, [SP, #80]

0x45c27c LDP	X27, X1, [X0, #16]

0x45c280 LDP	X26, X10, [X0]

0x45c284 STR	X1, [SP, #192]

0x45c288 LDP	X2, X24, [X0, #64]

0x45c28c LDP	X28, X11, [X0, #32]

0x45c290 LDP	X25, X15, [X0, #48]

0x45c294 STR	X2, [SP, #144]

0x45c298 LDP	X12, X4, [X0, #96]

0x45c29c LDP	X3, X7, [X0, #80]

0x45c2a0 STR	X4, [SP, #104]

0x45c2a4 LDP	X5, X23, [X0, #128]

0x45c2a8 LDP	X6, X18, [X0, #112]

0x45c2ac STR	X5, [SP, #96]

0x45c2b0 LDP	X13, X22, [X0, #144]

0x45c2b4 LDP	X21, X8, [X0, #160]

0x45c2b8 STR	X8, [SP, #152]

0x45c2bc LDP	X9, X14, [X0, #176]

0x45c2c0 STR	X9, [SP, #120]

0x45c2c4 STR	X14, [SP, #136]

0x45c2c8 LDP	X16, X17, [X0, #192]

0x45c2cc STR	X16, [SP, #128]

0x45c2d0 STR	X17, [SP, #184]

0x45c2d4 LDP	X19, X20, [X0, #208]

0x45c2d8 STP	X20, X19, [SP, #168]

0x45c2dc LDP	X4, X30, [X0, #224]

0x45c2e0 LDP	X0, X1, [X0, #240]

0x45c2e4 STR	X1, [SP, #112]

0x45c2e8 STR	X0, [SP, #160]

0x45c2ec CBNZ	X30, 45cdd4

0x45c2f0 CBNZ	X3, 45c788

0x45c2f4 MOVZ	X19, #0

0x45c2f8 MOVZ	X20, #0

0x45c2fc STP	X4, X13, [SP, #208]

0x45c300 STP	X18, X6, [SP, #224]

0x45c304 STP	X12, X7, [SP, #240]

0x45c308 STP	X15, X11, [SP, #256]

0x45c30c STR	X10, [SP, #272]

0x45c310 BL	52df60

0x45c314 STR	X0, [SP, #200]

0x45c318 BL	52df40

0x45c31c LDP	X3, X1, [SP, #112]

0x45c320 SUB	X14, X0, #1

0x45c324 LDP	X2, X8, [SP, #200]

0x45c328 SDIV	X0, X3, X0

0x45c32c LDP	X13, X18, [SP, #216]

0x45c330 CMP	X2, X14

0x45c334 LDP	X6, X12, [SP, #232]

0x45c338 LDP	X7, X15, [SP, #248]

0x45c33c MADD	X9, X2, X0, XZR

0x45c340 LDP	X11, X10, [SP, #264]

0x45c344 ADD	X14, X0, X9

0x45c348 LDR	X4, [X1, #8]

0x45c34c LDR	X1, [SP, #152]

0x45c350 ADD	X2, X4, X9

0x45c354 ADD	X5, X3, X4

0x45c358 ADD	X3, X14, X4

0x45c35c CSEL	X4, X5, X3, #0

0x45c360 CMP	X4, X2

0x45c364 ADD	X0, X1, X4,LSL #3

0x45c368 ADD	X17, X1, X2,LSL #3

0x45c36c STR	X0, [SP, #152]

0x45c370 B.LE	45cc2c

0x45c374 HINT	#0

0x45c378 HINT	#0

0x45c37c HINT	#0

(869) 0x45c380 LDR	X3, [X17]

(869) 0x45c384 LDR	X30, [SP, #136]

(869) 0x45c388 UBFM	X5, X3, #61, #60

(869) 0x45c38c ADD	X14, X5, #8

(869) 0x45c390 LDR	X2, [X12, X5]

(869) 0x45c394 LDR	X16, [X12, X14]

(869) 0x45c398 LDR	X0, [X30, X5]

(869) 0x45c39c ADD	X9, X0, X16

(869) 0x45c3a0 SUB	X1, X9, X2

(869) 0x45c3a4 CMP	X0, X1

(869) 0x45c3a8 B.GE	45c4dc

(869) 0x45c3ac LDR	X2, [SP, #184]

(869) 0x45c3b0 UBFM	X16, X0, #61, #60

(869) 0x45c3b4 LDR	X4, [X2, #8]

(869) 0x45c3b8 ADD	X30, X4, X1,LSL #3

(869) 0x45c3bc ADD	X0, X4, X0,LSL #3

(869) 0x45c3c0 SUB	X9, X30, X0

(869) 0x45c3c4 SUB	X1, X9, #8

(869) 0x45c3c8 UBFM	X2, X1, #3, #63

(869) 0x45c3cc ADD	X9, X2, #1

(869) 0x45c3d0 ANDS	X1, X9, #4224

(869) 0x45c3d4 B.EQ	45c468

(869) 0x45c3d8 CMP	X1, #1

(869) 0x45c3dc B.EQ	45c454

(869) 0x45c3e0 CMP	X1, #2

(869) 0x45c3e4 B.EQ	45c448

(869) 0x45c3e8 CMP	X1, #3

(869) 0x45c3ec B.EQ	45c43c

(869) 0x45c3f0 CMP	X1, #4

(869) 0x45c3f4 B.EQ	45c430

(869) 0x45c3f8 CMP	X1, #5

(869) 0x45c3fc B.EQ	45c424

(869) 0x45c400 CMP	X1, #6

(869) 0x45c404 B.EQ	45c418

(869) 0x45c408 LDR	X16, [X4, X16]

(869) 0x45c40c ADD	X0, X0, #8

(869) 0x45c410 LDR	X4, [X22, X16,LSL #3]

(869) 0x45c414 STR	X3, [X20, X4,LSL #3]

(869) 0x45c418 LDR	X2, [X0], #8

(869) 0x45c41c LDR	X9, [X22, X2,LSL #3]

(869) 0x45c420 STR	X3, [X20, X9,LSL #3]

(869) 0x45c424 LDR	X1, [X0], #8

(869) 0x45c428 LDR	X16, [X22, X1,LSL #3]

(869) 0x45c42c STR	X3, [X20, X16,LSL #3]

(869) 0x45c430 LDR	X4, [X0], #8

(869) 0x45c434 LDR	X2, [X22, X4,LSL #3]

(869) 0x45c438 STR	X3, [X20, X2,LSL #3]

(869) 0x45c43c LDR	X9, [X0], #8

(869) 0x45c440 LDR	X1, [X22, X9,LSL #3]

(869) 0x45c444 STR	X3, [X20, X1,LSL #3]

(869) 0x45c448 LDR	X16, [X0], #8

(869) 0x45c44c LDR	X4, [X22, X16,LSL #3]

(869) 0x45c450 STR	X3, [X20, X4,LSL #3]

(869) 0x45c454 LDR	X2, [X0], #8

(869) 0x45c458 LDR	X9, [X22, X2,LSL #3]

(869) 0x45c45c STR	X3, [X20, X9,LSL #3]

(869) 0x45c460 CMP	X30, X0

(869) 0x45c464 B.EQ	45c4d8

  (878) 0x45c468 ORR	X1, XZR, X0

  (878) 0x45c46c ADD	X0, X0, #64

  (878) 0x45c470 LDR	X16, [X1], #8

  (878) 0x45c474 LDR	X4, [X22, X16,LSL #3]

  (878) 0x45c478 STR	X3, [X20, X4,LSL #3]

  (878) 0x45c47c LDUR	X2, [X0, #456]

  (878) 0x45c480 LDR	X9, [X22, X2,LSL #3]

  (878) 0x45c484 STR	X3, [X20, X9,LSL #3]

  (878) 0x45c488 LDR	X1, [X1, #8]

  (878) 0x45c48c LDR	X16, [X22, X1,LSL #3]

  (878) 0x45c490 STR	X3, [X20, X16,LSL #3]

  (878) 0x45c494 LDUR	X4, [X0, #472]

  (878) 0x45c498 LDR	X2, [X22, X4,LSL #3]

  (878) 0x45c49c STR	X3, [X20, X2,LSL #3]

  (878) 0x45c4a0 LDUR	X9, [X0, #480]

  (878) 0x45c4a4 LDR	X1, [X22, X9,LSL #3]

  (878) 0x45c4a8 STR	X3, [X20, X1,LSL #3]

  (878) 0x45c4ac LDUR	X16, [X0, #488]

  (878) 0x45c4b0 LDR	X4, [X22, X16,LSL #3]

  (878) 0x45c4b4 STR	X3, [X20, X4,LSL #3]

  (878) 0x45c4b8 LDUR	X2, [X0, #496]

  (878) 0x45c4bc LDR	X9, [X22, X2,LSL #3]

  (878) 0x45c4c0 STR	X3, [X20, X9,LSL #3]

  (878) 0x45c4c4 LDUR	X1, [X0, #504]

  (878) 0x45c4c8 LDR	X16, [X22, X1,LSL #3]

  (878) 0x45c4cc STR	X3, [X20, X16,LSL #3]

  (878) 0x45c4d0 CMP	X30, X0

  (878) 0x45c4d4 B.NE	45c468

(869) 0x45c4d8 LDR	X2, [X12, X5]

(869) 0x45c4dc MOVI	D4, #0

(869) 0x45c4e0 ADD	X30, X11, X14

(869) 0x45c4e4 LDR	X0, [X11, X5]

(869) 0x45c4e8 LDR	X9, [X11, X14]

(869) 0x45c4ec FMOV	D29, D4

(869) 0x45c4f0 ADD	X0, X0, #1

(869) 0x45c4f4 CMP	X0, X9

(869) 0x45c4f8 B.GE	45c588

(869) 0x45c4fc CMP	X10, #1

(869) 0x45c500 B.EQ	45cc54

(869) 0x45c504 ORR	X16, XZR, X19

(869) 0x45c508 LDR	X19, [SP, #160]

(869) 0x45c50c STP	X8, X6, [SP, #112]

  (877) 0x45c510 LDR	X4, [X25, X0,LSL #3]

  (877) 0x45c514 UBFM	X1, X4, #61, #60

  (877) 0x45c518 LDR	X6, [X26, X1]

  (877) 0x45c51c CMN	X6, #3

  (877) 0x45c520 B.EQ	45c53c

  (877) 0x45c524 LDR	X6, [X27, X5]

  (877) 0x45c528 LDR	X8, [X27, X1]

  (877) 0x45c52c CMP	X6, X8

  (877) 0x45c530 B.NE	45c53c

  (877) 0x45c534 LDR	D21, [X28, X0,LSL #3]

  (877) 0x45c538 FADD	D4, D4, D21

  (877) 0x45c53c CMN	X4, #1

  (877) 0x45c540 B.EQ	45c574

  (877) 0x45c544 LDR	X4, [X20, X1]

  (877) 0x45c548 CMP	X3, X4

  (877) 0x45c54c B.NE	45c574

  (877) 0x45c550 LDR	D20, [X28, X0,LSL #3]

  (877) 0x45c554 UBFM	X9, X2, #61, #60

  (877) 0x45c558 ADD	X2, X2, #1

  (877) 0x45c55c LDR	X1, [X19, X1]

  (877) 0x45c560 LDR	X6, [SP, #104]

  (877) 0x45c564 FADD	D29, D29, D20

  (877) 0x45c568 STR	D20, [X7, X9]

  (877) 0x45c56c STR	X1, [X6, X9]

  (877) 0x45c570 LDR	X9, [X30]

  (877) 0x45c574 ADD	X0, X0, #1

  (877) 0x45c578 CMP	X0, X9

  (877) 0x45c57c B.LT	45c510

(869) 0x45c580 LDP	X8, X6, [SP, #112]

(869) 0x45c584 ORR	X19, XZR, X16

(869) 0x45c588 LDR	X0, [SP, #128]

(869) 0x45c58c LDR	X30, [X18, X14]

(869) 0x45c590 LDR	X1, [X18, X5]

(869) 0x45c594 LDR	X0, [X0, X5]

(869) 0x45c598 ADD	X16, X0, X30

(869) 0x45c59c SUB	X4, X16, X1

(869) 0x45c5a0 CMP	X0, X4

(869) 0x45c5a4 B.GE	45c6d8

(869) 0x45c5a8 LDR	X9, [SP, #176]

(869) 0x45c5ac UBFM	X30, X0, #61, #60

(869) 0x45c5b0 LDR	X16, [X9, #8]

(869) 0x45c5b4 ADD	X4, X16, X4,LSL #3

(869) 0x45c5b8 ADD	X0, X16, X0,LSL #3

(869) 0x45c5bc SUB	X1, X4, X0

(869) 0x45c5c0 SUB	X9, X1, #8

(869) 0x45c5c4 UBFM	X1, X9, #3, #63

(869) 0x45c5c8 ADD	X9, X1, #1

(869) 0x45c5cc ANDS	X1, X9, #4224

(869) 0x45c5d0 B.EQ	45c664

(869) 0x45c5d4 CMP	X1, #1

(869) 0x45c5d8 B.EQ	45c650

(869) 0x45c5dc CMP	X1, #2

(869) 0x45c5e0 B.EQ	45c644

(869) 0x45c5e4 CMP	X1, #3

(869) 0x45c5e8 B.EQ	45c638

(869) 0x45c5ec CMP	X1, #4

(869) 0x45c5f0 B.EQ	45c62c

(869) 0x45c5f4 CMP	X1, #5

(869) 0x45c5f8 B.EQ	45c620

(869) 0x45c5fc CMP	X1, #6

(869) 0x45c600 B.EQ	45c614

(869) 0x45c604 LDR	X30, [X16, X30]

(869) 0x45c608 ADD	X0, X0, #8

(869) 0x45c60c LDR	X16, [X21, X30,LSL #3]

(869) 0x45c610 STR	X3, [X19, X16,LSL #3]

(869) 0x45c614 LDR	X9, [X0], #8

(869) 0x45c618 LDR	X1, [X21, X9,LSL #3]

(869) 0x45c61c STR	X3, [X19, X1,LSL #3]

(869) 0x45c620 LDR	X30, [X0], #8

(869) 0x45c624 LDR	X16, [X21, X30,LSL #3]

(869) 0x45c628 STR	X3, [X19, X16,LSL #3]

(869) 0x45c62c LDR	X9, [X0], #8

(869) 0x45c630 LDR	X1, [X21, X9,LSL #3]

(869) 0x45c634 STR	X3, [X19, X1,LSL #3]

(869) 0x45c638 LDR	X30, [X0], #8

(869) 0x45c63c LDR	X16, [X21, X30,LSL #3]

(869) 0x45c640 STR	X3, [X19, X16,LSL #3]

(869) 0x45c644 LDR	X9, [X0], #8

(869) 0x45c648 LDR	X1, [X21, X9,LSL #3]

(869) 0x45c64c STR	X3, [X19, X1,LSL #3]

(869) 0x45c650 LDR	X30, [X0], #8

(869) 0x45c654 LDR	X16, [X21, X30,LSL #3]

(869) 0x45c658 STR	X3, [X19, X16,LSL #3]

(869) 0x45c65c CMP	X0, X4

(869) 0x45c660 B.EQ	45c6d4

  (875) 0x45c664 ORR	X1, XZR, X0

  (875) 0x45c668 ADD	X0, X0, #64

  (875) 0x45c66c LDR	X9, [X1], #8

  (875) 0x45c670 LDR	X30, [X21, X9,LSL #3]

  (875) 0x45c674 STR	X3, [X19, X30,LSL #3]

  (875) 0x45c678 LDUR	X16, [X0, #456]

  (875) 0x45c67c LDR	X9, [X21, X16,LSL #3]

  (875) 0x45c680 STR	X3, [X19, X9,LSL #3]

  (875) 0x45c684 LDR	X1, [X1, #8]

  (875) 0x45c688 LDR	X30, [X21, X1,LSL #3]

  (875) 0x45c68c STR	X3, [X19, X30,LSL #3]

  (875) 0x45c690 LDUR	X16, [X0, #472]

  (875) 0x45c694 LDR	X9, [X21, X16,LSL #3]

  (875) 0x45c698 STR	X3, [X19, X9,LSL #3]

  (875) 0x45c69c LDUR	X1, [X0, #480]

  (875) 0x45c6a0 LDR	X30, [X21, X1,LSL #3]

  (875) 0x45c6a4 STR	X3, [X19, X30,LSL #3]

  (875) 0x45c6a8 LDUR	X16, [X0, #488]

  (875) 0x45c6ac LDR	X9, [X21, X16,LSL #3]

  (875) 0x45c6b0 STR	X3, [X19, X9,LSL #3]

  (875) 0x45c6b4 LDUR	X1, [X0, #496]

  (875) 0x45c6b8 LDR	X30, [X21, X1,LSL #3]

  (875) 0x45c6bc STR	X3, [X19, X30,LSL #3]

  (875) 0x45c6c0 LDUR	X16, [X0, #504]

  (875) 0x45c6c4 LDR	X9, [X21, X16,LSL #3]

  (875) 0x45c6c8 STR	X3, [X19, X9,LSL #3]

  (875) 0x45c6cc CMP	X0, X4

  (875) 0x45c6d0 B.NE	45c664

(869) 0x45c6d4 LDR	X1, [X18, X5]

(869) 0x45c6d8 LDR	X4, [SP, #144]

(869) 0x45c6dc LDR	X0, [X4, X5]

(869) 0x45c6e0 ADD	X16, X4, X14

(869) 0x45c6e4 LDR	X14, [X4, X14]

(869) 0x45c6e8 CMP	X0, X14

(869) 0x45c6ec B.GE	45cd5c

(869) 0x45c6f0 LDR	X30, [SP, #192]

(869) 0x45c6f4 CBZ	X30, 45ccc8

(869) 0x45c6f8 ORR	X30, XZR, X21

(869) 0x45c6fc LDR	X21, [SP, #168]

(869) 0x45c700 STP	X7, X2, [SP, #112]

(869) 0x45c704 B	45c75c

  (874) 0x45c708 LDR	X2, [X27, X5]

  (874) 0x45c70c LDR	X7, [X13, X4]

  (874) 0x45c710 CMP	X2, X7

  (874) 0x45c714 B.EQ	45c77c

  (874) 0x45c718 CMN	X9, #1

  (874) 0x45c71c B.EQ	45c750

  (874) 0x45c720 LDR	X9, [X19, X4]

  (874) 0x45c724 CMP	X3, X9

  (874) 0x45c728 B.NE	45c750

  (874) 0x45c72c LDR	D5, [X15, X0,LSL #3]

  (874) 0x45c730 UBFM	X14, X1, #61, #60

  (874) 0x45c734 ADD	X1, X1, #1

  (874) 0x45c738 LDR	X4, [X21, X4]

  (874) 0x45c73c LDR	X2, [SP, #96]

  (874) 0x45c740 FADD	D29, D29, D5

  (874) 0x45c744 STR	D5, [X6, X14]

  (874) 0x45c748 STR	X4, [X2, X14]

  (874) 0x45c74c LDR	X14, [X16]

  (874) 0x45c750 ADD	X0, X0, #1

  (874) 0x45c754 CMP	X0, X14

  (874) 0x45c758 B.GE	45c808

  (874) 0x45c75c LDR	X7, [X24, X0,LSL #3]

  (874) 0x45c760 LDR	X9, [X8, X7,LSL #3]

  (874) 0x45c764 UBFM	X4, X9, #61, #60

  (874) 0x45c768 LDR	X2, [X23, X4]

  (874) 0x45c76c CMN	X2, #3

  (874) 0x45c770 B.EQ	45c718

  (874) 0x45c774 CMP	X10, #1

  (874) 0x45c778 B.NE	45c708

  (874) 0x45c77c LDR	D6, [X15, X0,LSL #3]

  (874) 0x45c780 FADD	D4, D4, D6

  (874) 0x45c784 B	45c718

0x45c788 MOVZ	X1, #8

0x45c78c ORR	X0, XZR, X3

0x45c790 STP	X3, X4, [SP, #200]

0x45c794 MOVZ	X20, #0

0x45c798 STP	X13, X18, [SP, #216]

0x45c79c STP	X6, X12, [SP, #232]

0x45c7a0 STP	X7, X15, [SP, #248]

0x45c7a4 STP	X11, X10, [SP, #264]

0x45c7a8 BL	52b308

0x45c7ac LDP	X5, X4, [SP, #200]

0x45c7b0 ORR	X19, XZR, X0

0x45c7b4 LDP	X13, X18, [SP, #216]

0x45c7b8 LDP	X6, X12, [SP, #232]

0x45c7bc LDP	X7, X15, [SP, #248]

0x45c7c0 LDP	X11, X10, [SP, #264]

0x45c7c4 CMP	X5, #0

0x45c7c8 B.LE	45c2fc

0x45c7cc UBFM	X2, X5, #61, #60

0x45c7d0 MOVZ	W1, #255

0x45c7d4 ORR	X0, XZR, X19

0x45c7d8 STP	X4, X13, [SP, #200]

0x45c7dc STP	X18, X6, [SP, #216]

0x45c7e0 STP	X12, X7, [SP, #232]

0x45c7e4 STP	X15, X11, [SP, #248]

0x45c7e8 STR	X10, [SP, #264]

0x45c7ec BL	410950

0x45c7f0 LDR	X10, [SP, #264]

0x45c7f4 LDP	X4, X13, [SP, #200]

0x45c7f8 LDP	X18, X6, [SP, #216]

0x45c7fc LDP	X12, X7, [SP, #232]

0x45c800 LDP	X15, X11, [SP, #248]

0x45c804 B	45c2fc

(869) 0x45c808 LDP	X7, X2, [SP, #112]

(869) 0x45c80c ORR	X21, XZR, X30

(869) 0x45c810 LDR	X4, [X18, X5]

(869) 0x45c814 LDR	X3, [X11, X5]

(869) 0x45c818 LDR	D27, [X28, X3,LSL #3]

(869) 0x45c81c FMUL	D0, D29, D27

(869) 0x45c820 FCMP	D0, #0

(869) 0x45c824 B.EQ	45c830

(869) 0x45c828 FNEG	D1, D4

(869) 0x45c82c FDIV	D31, D1, D0

(869) 0x45c830 LDR	X3, [X12, X5]

(869) 0x45c834 CMP	X3, X2

(869) 0x45c838 B.GE	45ca2c

(869) 0x45c83c SUB	X9, X2, X3

(869) 0x45c840 SUB	X5, X9, #1

(869) 0x45c844 CMP	X5, #2

(869) 0x45c848 B.LS	45c9e4

(869) 0x45c84c UBFM	X30, X9, #2, #63

(869) 0x45c850 ADD	X0, X7, X3,LSL #3

(869) 0x45c854 DUP	V26.2D, V31.D[0]

(869) 0x45c858 UBFM	X16, X3, #61, #60

(869) 0x45c85c UBFM	X14, X30, #59, #58

(869) 0x45c860 SUB	X14, X14, #32

(869) 0x45c864 ADD	X5, X0, X30,LSL #5

(869) 0x45c868 UBFM	X30, X14, #5, #63

(869) 0x45c86c ADD	X14, X30, #1

(869) 0x45c870 ANDS	X30, X14, #4224

(869) 0x45c874 B.EQ	45c92c

(869) 0x45c878 CMP	X30, #1

(869) 0x45c87c B.EQ	45c914

(869) 0x45c880 CMP	X30, #2

(869) 0x45c884 B.EQ	45c904

(869) 0x45c888 CMP	X30, #3

(869) 0x45c88c B.EQ	45c8f4

(869) 0x45c890 CMP	X30, #4

(869) 0x45c894 B.EQ	45c8e4

(869) 0x45c898 CMP	X30, #5

(869) 0x45c89c B.EQ	45c8d4

(869) 0x45c8a0 CMP	X30, #6

(869) 0x45c8a4 B.EQ	45c8c4

(869) 0x45c8a8 LDR	Q2, [X7, X16]

(869) 0x45c8ac ADD	X0, X0, #32

(869) 0x45c8b0 LDUR	Q3, [X0, #496]

(869) 0x45c8b4 FMUL	V22.2D, V2.2D, V26.2D

(869) 0x45c8b8 FMUL	V23.2D, V3.2D, V26.2D

(869) 0x45c8bc STR	Q22, [X7, X16]

(869) 0x45c8c0 STUR	Q23, [X0, #496]

(869) 0x45c8c4 LDP	Q24, Q30, [X0]

(869) 0x45c8c8 FMUL	V25.2D, V24.2D, V26.2D

(869) 0x45c8cc FMUL	V19.2D, V30.2D, V26.2D

(869) 0x45c8d0 STP	Q25, Q19, [X0], #32

(869) 0x45c8d4 LDP	Q4, Q28, [X0]

(869) 0x45c8d8 FMUL	V29.2D, V4.2D, V26.2D

(869) 0x45c8dc FMUL	V21.2D, V28.2D, V26.2D

(869) 0x45c8e0 STP	Q29, Q21, [X0], #32

(869) 0x45c8e4 LDP	Q20, Q6, [X0]

(869) 0x45c8e8 FMUL	V5.2D, V20.2D, V26.2D

(869) 0x45c8ec FMUL	V16.2D, V6.2D, V26.2D

(869) 0x45c8f0 STP	Q5, Q16, [X0], #32

(869) 0x45c8f4 LDP	Q7, Q18, [X0]

(869) 0x45c8f8 FMUL	V17.2D, V7.2D, V26.2D

(869) 0x45c8fc FMUL	V27.2D, V18.2D, V26.2D

(869) 0x45c900 STP	Q17, Q27, [X0], #32

(869) 0x45c904 LDP	Q0, Q1, [X0]

(869) 0x45c908 FMUL	V2.2D, V0.2D, V26.2D

(869) 0x45c90c FMUL	V22.2D, V1.2D, V26.2D

(869) 0x45c910 STP	Q2, Q22, [X0], #32

(869) 0x45c914 LDP	Q3, Q23, [X0]

(869) 0x45c918 FMUL	V24.2D, V3.2D, V26.2D

(869) 0x45c91c FMUL	V30.2D, V23.2D, V26.2D

(869) 0x45c920 STP	Q24, Q30, [X0], #32

(869) 0x45c924 CMP	X5, X0

(869) 0x45c928 B.EQ	45c9d4

(869) 0x45c92c STP	X19, X8, [SP, #112]

(869) 0x45c930 STR	X21, [SP, #200]

  (871) 0x45c934 LDP	Q25, Q19, [X0]

  (871) 0x45c938 ORR	X19, XZR, X0

  (871) 0x45c93c LDP	Q29, Q21, [X0, #32]

  (871) 0x45c940 LDP	Q20, Q5, [X0, #64]

  (871) 0x45c944 LDP	Q17, Q27, [X0, #96]

  (871) 0x45c948 LDP	Q30, Q2, [X0, #128]

  (871) 0x45c94c FMUL	V4.2D, V25.2D, V26.2D

  (871) 0x45c950 LDP	Q0, Q1, [X0, #160]

  (871) 0x45c954 FMUL	V28.2D, V19.2D, V26.2D

  (871) 0x45c958 LDP	Q24, Q25, [X0, #192]

  (871) 0x45c95c FMUL	V6.2D, V29.2D, V26.2D

  (871) 0x45c960 LDP	Q22, Q23, [X0, #224]

  (871) 0x45c964 ADD	X0, X0, #256

  (871) 0x45c968 FMUL	V16.2D, V21.2D, V26.2D

  (871) 0x45c96c FMUL	V7.2D, V20.2D, V26.2D

  (871) 0x45c970 FMUL	V18.2D, V5.2D, V26.2D

  (871) 0x45c974 FMUL	V3.2D, V17.2D, V26.2D

  (871) 0x45c978 FMUL	V19.2D, V27.2D, V26.2D

  (871) 0x45c97c FMUL	V29.2D, V0.2D, V26.2D

  (871) 0x45c980 FMUL	V21.2D, V1.2D, V26.2D

  (871) 0x45c984 STUR	Q7, [X0, #320]

  (871) 0x45c988 FMUL	V20.2D, V24.2D, V26.2D

  (871) 0x45c98c STUR	Q18, [X0, #336]

  (871) 0x45c990 FMUL	V5.2D, V25.2D, V26.2D

  (871) 0x45c994 STP	Q4, Q28, [X0, #1792]

  (871) 0x45c998 FMUL	V4.2D, V30.2D, V26.2D

  (871) 0x45c99c FMUL	V28.2D, V2.2D, V26.2D

  (871) 0x45c9a0 STP	Q6, Q16, [X0, #1824]

  (871) 0x45c9a4 FMUL	V6.2D, V22.2D, V26.2D

  (871) 0x45c9a8 FMUL	V16.2D, V23.2D, V26.2D

  (871) 0x45c9ac STP	Q3, Q19, [X0, #1888]

  (871) 0x45c9b0 STP	Q4, Q28, [X0, #1920]

  (871) 0x45c9b4 STP	Q29, Q21, [X0, #1952]

  (871) 0x45c9b8 STP	Q20, Q5, [X0, #1984]

  (871) 0x45c9bc STUR	Q6, [X0, #480]

  (871) 0x45c9c0 STR	Q16, [X19, #240]

  (871) 0x45c9c4 CMP	X5, X0

  (871) 0x45c9c8 B.NE	45c934

(869) 0x45c9cc LDR	X21, [SP, #200]

(869) 0x45c9d0 LDP	X19, X8, [SP, #112]

(869) 0x45c9d4 ANDS	XZR, X9, #4160

(869) 0x45c9d8 B.EQ	45ca2c

(869) 0x45c9dc AND	X9, X9, #8062

(869) 0x45c9e0 ADD	X3, X3, X9

(869) 0x45c9e4 UBFM	X16, X3, #61, #60

(869) 0x45c9e8 ADD	X5, X3, #1

(869) 0x45c9ec LDR	D26, [X7, X16]

(869) 0x45c9f0 FMUL	D7, D26, D31

(869) 0x45c9f4 STR	D7, [X7, X16]

(869) 0x45c9f8 CMP	X2, X5

(869) 0x45c9fc B.LE	45ca2c

(869) 0x45ca00 ADD	X14, X16, #8

(869) 0x45ca04 ADD	X30, X3, #2

(869) 0x45ca08 LDR	D18, [X7, X14]

(869) 0x45ca0c FMUL	D17, D18, D31

(869) 0x45ca10 STR	D17, [X7, X14]

(869) 0x45ca14 CMP	X2, X30

(869) 0x45ca18 B.LE	45ca2c

(869) 0x45ca1c ADD	X2, X16, #16

(869) 0x45ca20 LDR	D27, [X7, X2]

(869) 0x45ca24 FMUL	D30, D27, D31

(869) 0x45ca28 STR	D30, [X7, X2]

(869) 0x45ca2c CMP	X1, X4

(869) 0x45ca30 B.LE	45cc1c

(869) 0x45ca34 SUB	X3, X1, X4

(869) 0x45ca38 SUB	X0, X3, #1

(869) 0x45ca3c CMP	X0, #2

(869) 0x45ca40 B.LS	45cbd4

(869) 0x45ca44 UBFM	X16, X3, #2, #63

(869) 0x45ca48 ADD	X0, X6, X4,LSL #3

(869) 0x45ca4c DUP	V28.2D, V31.D[0]

(869) 0x45ca50 UBFM	X9, X4, #61, #60

(869) 0x45ca54 UBFM	X5, X16, #59, #58

(869) 0x45ca58 SUB	X14, X5, #32

(869) 0x45ca5c ADD	X2, X0, X16,LSL #5

(869) 0x45ca60 UBFM	X30, X14, #5, #63

(869) 0x45ca64 ADD	X16, X30, #1

(869) 0x45ca68 ANDS	X5, X16, #4224

(869) 0x45ca6c B.EQ	45cb24

(869) 0x45ca70 CMP	X5, #1

(869) 0x45ca74 B.EQ	45cb0c

(869) 0x45ca78 CMP	X5, #2

(869) 0x45ca7c B.EQ	45cafc

(869) 0x45ca80 CMP	X5, #3

(869) 0x45ca84 B.EQ	45caec

(869) 0x45ca88 CMP	X5, #4

(869) 0x45ca8c B.EQ	45cadc

(869) 0x45ca90 CMP	X5, #5

(869) 0x45ca94 B.EQ	45cacc

(869) 0x45ca98 CMP	X5, #6

(869) 0x45ca9c B.EQ	45cabc

(869) 0x45caa0 LDR	Q2, [X6, X9]

(869) 0x45caa4 ADD	X0, X0, #32

(869) 0x45caa8 LDUR	Q1, [X0, #496]

(869) 0x45caac FMUL	V0.2D, V2.2D, V28.2D

(869) 0x45cab0 FMUL	V24.2D, V1.2D, V28.2D

(869) 0x45cab4 STR	Q0, [X6, X9]

(869) 0x45cab8 STUR	Q24, [X0, #496]

(869) 0x45cabc LDP	Q25, Q22, [X0]

(869) 0x45cac0 FMUL	V23.2D, V25.2D, V28.2D

(869) 0x45cac4 FMUL	V3.2D, V22.2D, V28.2D

(869) 0x45cac8 STP	Q23, Q3, [X0], #32

(869) 0x45cacc LDP	Q19, Q4, [X0]

(869) 0x45cad0 FMUL	V29.2D, V19.2D, V28.2D

(869) 0x45cad4 FMUL	V21.2D, V4.2D, V28.2D

(869) 0x45cad8 STP	Q29, Q21, [X0], #32

(869) 0x45cadc LDP	Q20, Q5, [X0]

(869) 0x45cae0 FMUL	V6.2D, V20.2D, V28.2D

(869) 0x45cae4 FMUL	V16.2D, V5.2D, V28.2D

(869) 0x45cae8 STP	Q6, Q16, [X0], #32

(869) 0x45caec LDP	Q26, Q7, [X0]

(869) 0x45caf0 FMUL	V18.2D, V26.2D, V28.2D

(869) 0x45caf4 FMUL	V17.2D, V7.2D, V28.2D

(869) 0x45caf8 STP	Q18, Q17, [X0], #32

(869) 0x45cafc LDP	Q27, Q2, [X0]

(869) 0x45cb00 FMUL	V30.2D, V27.2D, V28.2D

(869) 0x45cb04 FMUL	V0.2D, V2.2D, V28.2D

(869) 0x45cb08 STP	Q30, Q0, [X0], #32

(869) 0x45cb0c LDP	Q1, Q24, [X0]

(869) 0x45cb10 FMUL	V25.2D, V1.2D, V28.2D

(869) 0x45cb14 FMUL	V22.2D, V24.2D, V28.2D

(869) 0x45cb18 STP	Q25, Q22, [X0], #32

(869) 0x45cb1c CMP	X2, X0

(869) 0x45cb20 B.EQ	45cbc4

(869) 0x45cb24 STR	X3, [SP, #112]

  (870) 0x45cb28 LDP	Q23, Q3, [X0]

  (870) 0x45cb2c ORR	X9, XZR, X0

  (870) 0x45cb30 LDP	Q29, Q5, [X0, #32]

  (870) 0x45cb34 LDP	Q6, Q20, [X0, #64]

  (870) 0x45cb38 LDP	Q17, Q18, [X0, #96]

  (870) 0x45cb3c LDP	Q30, Q0, [X0, #128]

  (870) 0x45cb40 FMUL	V19.2D, V23.2D, V28.2D

  (870) 0x45cb44 LDP	Q1, Q24, [X0, #160]

  (870) 0x45cb48 FMUL	V4.2D, V3.2D, V28.2D

  (870) 0x45cb4c LDP	Q25, Q22, [X0, #192]

  (870) 0x45cb50 FMUL	V21.2D, V29.2D, V28.2D

  (870) 0x45cb54 LDP	Q2, Q27, [X0, #224]

  (870) 0x45cb58 ADD	X0, X0, #256

  (870) 0x45cb5c FMUL	V16.2D, V5.2D, V28.2D

  (870) 0x45cb60 FMUL	V26.2D, V6.2D, V28.2D

  (870) 0x45cb64 FMUL	V7.2D, V20.2D, V28.2D

  (870) 0x45cb68 FMUL	V23.2D, V17.2D, V28.2D

  (870) 0x45cb6c FMUL	V29.2D, V30.2D, V28.2D

  (870) 0x45cb70 FMUL	V20.2D, V0.2D, V28.2D

  (870) 0x45cb74 FMUL	V5.2D, V1.2D, V28.2D

  (870) 0x45cb78 STUR	Q26, [X0, #320]

  (870) 0x45cb7c FMUL	V6.2D, V24.2D, V28.2D

  (870) 0x45cb80 STUR	Q7, [X0, #336]

  (870) 0x45cb84 FMUL	V3.2D, V25.2D, V28.2D

  (870) 0x45cb88 STP	Q19, Q4, [X0, #1792]

  (870) 0x45cb8c FMUL	V19.2D, V18.2D, V28.2D

  (870) 0x45cb90 FMUL	V4.2D, V22.2D, V28.2D

  (870) 0x45cb94 STP	Q21, Q16, [X0, #1824]

  (870) 0x45cb98 FMUL	V21.2D, V2.2D, V28.2D

  (870) 0x45cb9c FMUL	V16.2D, V27.2D, V28.2D

  (870) 0x45cba0 STP	Q23, Q19, [X0, #1888]

  (870) 0x45cba4 STP	Q29, Q20, [X0, #1920]

  (870) 0x45cba8 STP	Q5, Q6, [X0, #1952]

  (870) 0x45cbac STP	Q3, Q4, [X0, #1984]

  (870) 0x45cbb0 STUR	Q21, [X0, #480]

  (870) 0x45cbb4 STR	Q16, [X9, #240]

  (870) 0x45cbb8 CMP	X2, X0

  (870) 0x45cbbc B.NE	45cb28

(869) 0x45cbc0 LDR	X3, [SP, #112]

(869) 0x45cbc4 ANDS	XZR, X3, #4160

(869) 0x45cbc8 B.EQ	45cc1c

(869) 0x45cbcc AND	X14, X3, #8062

(869) 0x45cbd0 ADD	X4, X4, X14

(869) 0x45cbd4 UBFM	X30, X4, #61, #60

(869) 0x45cbd8 ADD	X2, X4, #1

(869) 0x45cbdc LDR	D28, [X6, X30]

(869) 0x45cbe0 FMUL	D26, D28, D31

(869) 0x45cbe4 STR	D26, [X6, X30]

(869) 0x45cbe8 CMP	X1, X2

(869) 0x45cbec B.LE	45cc1c

(869) 0x45cbf0 ADD	X16, X30, #8

(869) 0x45cbf4 ADD	X4, X4, #2

(869) 0x45cbf8 LDR	D7, [X6, X16]

(869) 0x45cbfc FMUL	D17, D7, D31

(869) 0x45cc00 STR	D17, [X6, X16]

(869) 0x45cc04 CMP	X1, X4

(869) 0x45cc08 B.LE	45cc1c

(869) 0x45cc0c ADD	X1, X30, #16

(869) 0x45cc10 LDR	D18, [X6, X1]

(869) 0x45cc14 FMUL	D30, D18, D31

(869) 0x45cc18 STR	D30, [X6, X1]

(869) 0x45cc1c LDR	X5, [SP, #152]

(869) 0x45cc20 ADD	X17, X17, #8

(869) 0x45cc24 CMP	X17, X5

(869) 0x45cc28 B.NE	45c380

0x45cc2c ORR	X0, XZR, X20

0x45cc30 BL	52b3a0

0x45cc34 ORR	X0, XZR, X19

0x45cc38 LDP	X21, X22, [SP, #32]

0x45cc3c LDP	X19, X20, [SP, #16]

0x45cc40 LDP	X23, X24, [SP, #48]

0x45cc44 LDP	X25, X26, [SP, #64]

0x45cc48 LDP	X27, X28, [SP, #80]

0x45cc4c LDP	X29, X30, [SP], #288

0x45cc50 B	52b3a0

(869) 0x45cc54 LDR	X16, [SP, #160]

(869) 0x45cc58 STR	X5, [SP, #112]

(869) 0x45cc5c HINT	#0

  (876) 0x45cc60 LDR	X1, [X25, X0,LSL #3]

  (876) 0x45cc64 UBFM	X4, X1, #61, #60

  (876) 0x45cc68 LDR	X5, [X26, X4]

  (876) 0x45cc6c CMN	X5, #3

  (876) 0x45cc70 B.EQ	45cc7c

  (876) 0x45cc74 LDR	D19, [X28, X0,LSL #3]

  (876) 0x45cc78 FADD	D4, D4, D19

  (876) 0x45cc7c CMN	X1, #1

  (876) 0x45cc80 B.EQ	45ccb4

  (876) 0x45cc84 LDR	X1, [X20, X4]

  (876) 0x45cc88 CMP	X3, X1

  (876) 0x45cc8c B.NE	45ccb4

  (876) 0x45cc90 LDR	D28, [X28, X0,LSL #3]

  (876) 0x45cc94 UBFM	X9, X2, #61, #60

  (876) 0x45cc98 ADD	X2, X2, #1

  (876) 0x45cc9c LDR	X4, [X16, X4]

  (876) 0x45cca0 LDR	X5, [SP, #104]

  (876) 0x45cca4 FADD	D29, D29, D28

  (876) 0x45cca8 STR	D28, [X7, X9]

  (876) 0x45ccac STR	X4, [X5, X9]

  (876) 0x45ccb0 LDR	X9, [X30]

  (876) 0x45ccb4 ADD	X0, X0, #1

  (876) 0x45ccb8 CMP	X0, X9

  (876) 0x45ccbc B.LT	45cc60

(869) 0x45ccc0 LDR	X5, [SP, #112]

(869) 0x45ccc4 B	45c588

(869) 0x45ccc8 CMP	X10, #1

(869) 0x45cccc B.EQ	45cd64

(869) 0x45ccd0 LDR	X30, [SP, #168]

(869) 0x45ccd4 ORR	X9, XZR, X8

(869) 0x45ccd8 STP	X7, X2, [SP, #112]

(869) 0x45ccdc HINT	#0

  (873) 0x45cce0 LDR	X8, [X24, X0,LSL #3]

  (873) 0x45cce4 UBFM	X4, X8, #61, #60

  (873) 0x45cce8 LDR	X7, [X23, X4]

  (873) 0x45ccec CMN	X7, #3

  (873) 0x45ccf0 B.EQ	45cd0c

  (873) 0x45ccf4 LDR	X2, [X13, X4]

  (873) 0x45ccf8 LDR	X7, [X27, X5]

  (873) 0x45ccfc CMP	X2, X7

  (873) 0x45cd00 B.NE	45cd0c

  (873) 0x45cd04 LDR	D18, [X15, X0,LSL #3]

  (873) 0x45cd08 FADD	D4, D4, D18

  (873) 0x45cd0c CMN	X8, #1

  (873) 0x45cd10 B.EQ	45cd44

  (873) 0x45cd14 LDR	X8, [X19, X4]

  (873) 0x45cd18 CMP	X3, X8

  (873) 0x45cd1c B.NE	45cd44

  (873) 0x45cd20 LDR	D17, [X15, X0,LSL #3]

  (873) 0x45cd24 UBFM	X14, X1, #61, #60

  (873) 0x45cd28 ADD	X1, X1, #1

  (873) 0x45cd2c LDR	X4, [X30, X4]

  (873) 0x45cd30 LDR	X2, [SP, #96]

  (873) 0x45cd34 FADD	D29, D29, D17

  (873) 0x45cd38 STR	D17, [X6, X14]

  (873) 0x45cd3c STR	X4, [X2, X14]

  (873) 0x45cd40 LDR	X14, [X16]

  (873) 0x45cd44 ADD	X0, X0, #1

  (873) 0x45cd48 CMP	X14, X0

  (873) 0x45cd4c B.GT	45cce0

(869) 0x45cd50 LDP	X7, X2, [SP, #112]

(869) 0x45cd54 ORR	X8, XZR, X9

(869) 0x45cd58 B	45c810

(869) 0x45cd5c ORR	X4, XZR, X1

(869) 0x45cd60 B	45c814

(869) 0x45cd64 LDR	X30, [SP, #168]

(869) 0x45cd68 STR	X2, [SP, #112]

  (872) 0x45cd6c LDR	X4, [X24, X0,LSL #3]

  (872) 0x45cd70 UBFM	X9, X4, #61, #60

  (872) 0x45cd74 LDR	X2, [X23, X9]

  (872) 0x45cd78 CMN	X2, #3

  (872) 0x45cd7c B.EQ	45cd88

  (872) 0x45cd80 LDR	D16, [X15, X0,LSL #3]

  (872) 0x45cd84 FADD	D4, D4, D16

  (872) 0x45cd88 CMN	X4, #1

  (872) 0x45cd8c B.EQ	45cdc0

  (872) 0x45cd90 LDR	X4, [X19, X9]

  (872) 0x45cd94 CMP	X3, X4

  (872) 0x45cd98 B.NE	45cdc0

  (872) 0x45cd9c LDR	D7, [X15, X0,LSL #3]

  (872) 0x45cda0 UBFM	X14, X1, #61, #60

  (872) 0x45cda4 ADD	X1, X1, #1

  (872) 0x45cda8 LDR	X9, [X30, X9]

  (872) 0x45cdac LDR	X2, [SP, #96]

  (872) 0x45cdb0 FADD	D29, D29, D7

  (872) 0x45cdb4 STR	D7, [X6, X14]

  (872) 0x45cdb8 STR	X9, [X2, X14]

  (872) 0x45cdbc LDR	X14, [X16]

  (872) 0x45cdc0 ADD	X0, X0, #1

  (872) 0x45cdc4 CMP	X14, X0

  (872) 0x45cdc8 B.GT	45cd6c

(869) 0x45cdcc LDR	X2, [SP, #112]

(869) 0x45cdd0 B	45c810

0x45cdd4 MOVZ	X1, #8

0x45cdd8 ORR	X0, XZR, X30

0x45cddc STP	X30, X4, [SP, #200]

0x45cde0 STP	X13, X18, [SP, #216]

0x45cde4 STP	X6, X12, [SP, #232]

0x45cde8 STP	X7, X3, [SP, #248]

0x45cdec STP	X15, X11, [SP, #264]

0x45cdf0 STR	X10, [SP, #280]

0x45cdf4 BL	52b308

0x45cdf8 LDP	X7, X3, [SP, #248]

0x45cdfc ORR	X20, XZR, X0

0x45ce00 LDP	X2, X4, [SP, #200]

0x45ce04 LDP	X13, X18, [SP, #216]

0x45ce08 LDP	X6, X12, [SP, #232]

0x45ce0c LDP	X15, X11, [SP, #264]

0x45ce10 LDR	X10, [SP, #280]

0x45ce14 CBNZ	X3, 45ce4c

0x45ce18 MOVZ	X19, #0

0x45ce1c CMP	X2, #0

0x45ce20 B.LE	45c2fc

0x45ce24 UBFM	X2, X2, #61, #60

0x45ce28 MOVZ	W1, #255

0x45ce2c STP	X4, X13, [SP, #200]

0x45ce30 MOVZ	X19, #0

0x45ce34 STP	X18, X6, [SP, #216]

0x45ce38 STP	X12, X7, [SP, #232]

0x45ce3c STP	X15, X11, [SP, #248]

0x45ce40 STR	X10, [SP, #264]

0x45ce44 BL	410950

0x45ce48 B	45c7f0

0x45ce4c MOVZ	X1, #8

0x45ce50 ORR	X0, XZR, X3

0x45ce54 STP	X3, X2, [SP, #200]

0x45ce58 STP	X4, X13, [SP, #216]

0x45ce5c STP	X18, X6, [SP, #232]

0x45ce60 STP	X12, X7, [SP, #248]

0x45ce64 STP	X15, X11, [SP, #264]

0x45ce68 STR	X10, [SP, #280]

0x45ce6c BL	52b308

0x45ce70 LDP	X5, X8, [SP, #200]

0x45ce74 ORR	X19, XZR, X0

0x45ce78 LDP	X4, X13, [SP, #216]

0x45ce7c LDP	X18, X6, [SP, #232]

0x45ce80 LDP	X12, X7, [SP, #248]

0x45ce84 LDP	X15, X11, [SP, #264]

0x45ce88 LDR	X10, [SP, #280]

0x45ce8c CMP	X8, #0

0x45ce90 B.LE	45c7c4

0x45ce94 UBFM	X2, X8, #61, #60

0x45ce98 MOVZ	W1, #255

0x45ce9c STP	X4, X13, [SP, #200]

0x45cea0 ORR	X0, XZR, X20

0x45cea4 STP	X18, X6, [SP, #216]

0x45cea8 STP	X12, X7, [SP, #232]

0x45ceac STP	X5, X15, [SP, #248]

0x45ceb0 STP	X11, X10, [SP, #264]

0x45ceb4 BL	410950

0x45ceb8 LDP	X4, X13, [SP, #200]

0x45cebc LDP	X18, X6, [SP, #216]

0x45cec0 LDP	X12, X7, [SP, #232]

0x45cec4 LDP	X5, X15, [SP, #248]

0x45cec8 LDP	X11, X10, [SP, #264]

0x45cecc B	45c7c4

Coverage (%)	Name	Source Location	Module
►99.23+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1584-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 82% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 38.17 to 34.33 cycles (1.11x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 38.17 to 4.50 cycles (8.48x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 872 bytes. The binary function is storing 768 bytes.

General properties

nb instructions	177
loop length	708
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.00	10.00	8.33	8.33	8.33	8.33	8.33	8.33	0.00	0.00	0.00	0.00	38.17	37.83	38.00	28.50	28.50
cycles	10.00	10.00	8.33	8.33	8.33	8.33	8.33	8.33	0.00	0.00	0.00	0.00	38.17	37.83	38.00	28.50	28.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	21.75
Overall L1	38.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 38.17 cycles. At this rate:

23% of peak load performance is reached (22.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
41% of peak store performance is reached (20.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45c260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X27, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X10, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X24, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X11, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X15, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X4, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X3, X7, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X23, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X18, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X13, X22, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X8, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X14, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X16, X17, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X20, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X20, X19, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X4, X30, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X0, X1, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X30, 45cdd4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X3, 45c788 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X20, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X6, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X14, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X2, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SDIV X0, X3, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X2, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X9, X2, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X14, X0, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X4, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X4, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X3, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X14, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CSEL X4, X5, X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X0, X1, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X1, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.LE 45cc2c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X3, X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X20, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X5, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45c2fc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 45c2fc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 52b3a0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X30, X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X3, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X3, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X2, X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X3, 45ce4c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45c2fc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X19, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45c7f0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X3, X2, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X13, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X13, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 45c7c4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X5, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 45c7c4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1584-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 38.17 to 4.50 cycles (8.48x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 872 bytes. The binary function is storing 768 bytes.

General properties

nb instructions	177
loop length	708
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.00	10.00	8.33	8.33	8.33	8.33	8.33	8.33	0.00	0.00	0.00	0.00	38.17	37.83	38.00	28.50	28.50
cycles	10.00	10.00	8.33	8.33	8.33	8.33	8.33	8.33	0.00	0.00	0.00	0.00	38.17	37.83	38.00	28.50	28.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	21.75
Overall L1	38.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 38.17 cycles. At this rate:

23% of peak load performance is reached (22.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
41% of peak store performance is reached (20.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45c260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X27, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X10, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X24, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X11, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X15, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X4, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X3, X7, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X5, X23, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X18, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X13, X22, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X8, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X14, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X16, X17, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X17, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X20, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X20, X19, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X4, X30, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X0, X1, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X30, 45cdd4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X3, 45c788 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X20, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X4, X13, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X6, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X3, X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X14, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X2, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SDIV X0, X3, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
LDP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X2, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X9, X2, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X14, X0, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X4, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X4, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X3, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X14, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CSEL X4, X5, X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X0, X1, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X1, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.LE 45cc2c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X3, X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X20, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X5, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45c2fc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 45c2fc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 52b3a0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X30, X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X7, X3, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X3, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X2, X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X13, X18, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X3, 45ce4c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X19, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45c2fc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X19, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 45c7f0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X3, X2, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X13, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X18, X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X15, X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X5, X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X13, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X15, X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 45c7c4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X4, X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X5, X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X11, X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 45c7c4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.9–	0.27	0.04
▼Loop 869 - par_multi_interp.c:1593-1660 - exec–	0.05	0.01
○Loop 876 - par_multi_interp.c:1618-1628 - exec	0.22	0.03
○Loop 873 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 870 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 878 - par_multi_interp.c:1612-1615 - exec	0.00	0.00
○Loop 874 - par_multi_interp.c:1639-1652 - exec	0.00	0.00
○Loop 871 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 877 - par_multi_interp.c:1618-1628 - exec	0.00	0.00
○Loop 875 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 872 - par_multi_interp.c:1639-1652 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code