OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.10	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.28% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1746:              tmp_marker = NULL;

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x45aec8 STP	X29, X30, [SP, #656]!

0x45aecc ADD	X29, SP, #0

0x45aed0 STP	X19, X20, [SP, #16]

0x45aed4 STP	X21, X22, [SP, #32]

0x45aed8 STP	X23, X24, [SP, #48]

0x45aedc STP	X25, X26, [SP, #64]

0x45aee0 STP	X27, X28, [SP, #80]

0x45aee4 LDP	X1, X11, [X0, #80]

0x45aee8 STR	X1, [SP, #216]

0x45aeec LDP	X2, X10, [X0, #96]

0x45aef0 STR	X2, [SP, #208]

0x45aef4 LDP	X3, X20, [X0, #112]

0x45aef8 STR	X3, [SP, #96]

0x45aefc LDP	X4, X25, [X0, #128]

0x45af00 STR	X4, [SP, #120]

0x45af04 LDP	X19, X5, [X0, #144]

0x45af08 STR	X5, [SP, #112]

0x45af0c LDP	X24, X6, [X0, #160]

0x45af10 STR	X6, [SP, #304]

0x45af14 LDP	X6, X7, [X0, #176]

0x45af18 STR	X7, [SP, #280]

0x45af1c LDP	X8, X9, [X0, #192]

0x45af20 STR	X9, [SP, #144]

0x45af24 STR	X8, [SP, #336]

0x45af28 LDP	X12, X13, [X0, #208]

0x45af2c STP	X13, X12, [SP, #192]

0x45af30 LDP	X14, X15, [X0, #224]

0x45af34 STP	X15, X14, [SP, #264]

0x45af38 LDP	X16, X17, [X0, #240]

0x45af3c STR	X17, [SP, #296]

0x45af40 STR	X16, [SP, #312]

0x45af44 LDP	X18, X21, [X0, #256]

0x45af48 STR	X21, [SP, #104]

0x45af4c STR	X18, [SP, #256]

0x45af50 LDP	X28, X26, [X0, #304]

0x45af54 LDP	X2, X23, [X0, #272]

0x45af58 LDP	X22, X8, [X0, #288]

0x45af5c STR	X26, [SP, #248]

0x45af60 LDP	X3, X27, [X0, #320]

0x45af64 STR	X27, [SP, #128]

0x45af68 LDP	X27, X30, [X0, #16]

0x45af6c LDP	X7, X12, [X0]

0x45af70 STR	X30, [SP, #352]

0x45af74 LDP	X21, X1, [X0, #32]

0x45af78 STR	X1, [SP, #232]

0x45af7c LDP	X9, X4, [X0, #48]

0x45af80 STR	X4, [SP, #344]

0x45af84 LDP	X0, X5, [X0, #64]

0x45af88 STR	X0, [SP, #224]

0x45af8c STR	X5, [SP, #288]

0x45af90 CBNZ	X2, 45c210

0x45af94 MOVZ	X26, #0

0x45af98 LDR	X0, [SP, #96]

0x45af9c CBNZ	X0, 45c1d0

0x45afa0 MOVZ	X13, #0

0x45afa4 CBNZ	X23, 45c184

0x45afa8 CMP	X3, X22

0x45afac B.LE	45c164

0x45afb0 ORR	X0, XZR, X3

0x45afb4 STR	X13, [SP, #136]

0x45afb8 STP	X8, X2, [SP, #152]

0x45afbc STP	X6, X10, [SP, #168]

0x45afc0 STR	X11, [SP, #184]

0x45afc4 STR	X9, [SP, #240]

0x45afc8 STP	X12, X7, [SP, #320]

0x45afcc MOVZ	X1, #8

0x45afd0 BL	52b308

0x45afd4 LDP	X15, X1, [SP, #152]

0x45afd8 ORR	X22, XZR, X0

0x45afdc LDP	X4, X5, [SP, #168]

0x45afe0 LDP	X18, X6, [SP, #320]

0x45afe4 LDR	X14, [SP, #136]

0x45afe8 LDR	X3, [SP, #184]

0x45afec LDR	X8, [SP, #240]

0x45aff0 CMP	X1, #0

0x45aff4 B.LE	45b038

0x45aff8 UBFM	X2, X1, #61, #60

0x45affc ORR	X0, XZR, X26

0x45b000 STR	X14, [SP, #136]

0x45b004 MOVZ	W1, #255

0x45b008 STP	X15, X4, [SP, #152]

0x45b00c STP	X5, X3, [SP, #168]

0x45b010 STR	X8, [SP, #184]

0x45b014 STR	X18, [SP, #240]

0x45b018 STR	X6, [SP, #320]

0x45b01c BL	410950

0x45b020 LDR	X14, [SP, #136]

0x45b024 LDP	X15, X4, [SP, #152]

0x45b028 LDP	X5, X3, [SP, #168]

0x45b02c LDR	X8, [SP, #184]

0x45b030 LDR	X18, [SP, #240]

0x45b034 LDR	X6, [SP, #320]

0x45b038 LDR	X16, [SP, #96]

0x45b03c CMP	X16, #0

0x45b040 B.LE	45b080

0x45b044 ORR	X0, XZR, X14

0x45b048 UBFM	X2, X16, #61, #60

0x45b04c STR	X15, [SP, #136]

0x45b050 MOVZ	W1, #255

0x45b054 STP	X4, X5, [SP, #152]

0x45b058 STP	X3, X8, [SP, #168]

0x45b05c STR	X18, [SP, #184]

0x45b060 STR	X6, [SP, #240]

0x45b064 BL	410950

0x45b068 LDR	X15, [SP, #136]

0x45b06c ORR	X14, XZR, X0

0x45b070 LDP	X4, X5, [SP, #152]

0x45b074 LDP	X3, X8, [SP, #168]

0x45b078 LDR	X18, [SP, #184]

0x45b07c LDR	X6, [SP, #240]

0x45b080 STP	X14, X15, [SP, #152]

0x45b084 STP	X4, X5, [SP, #168]

0x45b088 STR	X3, [SP, #184]

0x45b08c STR	X8, [SP, #240]

0x45b090 STP	X18, X6, [SP, #320]

0x45b094 BL	52df60

0x45b098 STR	X0, [SP, #96]

0x45b09c BL	52df40

0x45b0a0 LDR	X14, [SP, #128]

0x45b0a4 SUB	X5, X0, #1

0x45b0a8 LDP	X2, X15, [SP, #144]

0x45b0ac LDP	X9, X6, [SP, #160]

0x45b0b0 SDIV	X3, X14, X0

0x45b0b4 LDP	X10, X11, [SP, #176]

0x45b0b8 LDP	X18, X7, [SP, #320]

0x45b0bc LDR	X13, [SP, #104]

0x45b0c0 LDR	X8, [SP, #96]

0x45b0c4 LDR	X12, [SP, #240]

0x45b0c8 UBFM	X1, X13, #61, #60

0x45b0cc LDR	X4, [X2, X1]

0x45b0d0 CMP	X8, X5

0x45b0d4 STR	X1, [SP, #136]

0x45b0d8 ADD	X13, X14, X4

0x45b0dc MADD	X14, X8, X3, XZR

0x45b0e0 ADD	X0, X3, X14

0x45b0e4 ADD	X1, X4, X14

0x45b0e8 ADD	X2, X0, X4

0x45b0ec CSEL	X4, X13, X2, #0

0x45b0f0 CMP	X4, X1

0x45b0f4 B.LE	45bac8

0x45b0f8 LDR	X5, [SP, #336]

0x45b0fc SUB	X30, X24, #8

0x45b100 SUB	X16, X25, #8

0x45b104 LDR	X8, [SP, #104]

0x45b108 ADD	X17, X5, X1,LSL #3

0x45b10c ADD	X3, X5, X4,LSL #3

0x45b110 SUB	X13, X8, #1

0x45b114 STR	X17, [SP, #128]

0x45b118 STP	X13, X30, [SP, #96]

0x45b11c LDP	X17, X30, [SP, #344]

0x45b120 STR	X3, [SP, #240]

(857) 0x45b124 LDR	X14, [SP, #128]

(857) 0x45b128 LDR	X1, [SP, #120]

(857) 0x45b12c LDR	X0, [SP, #200]

(857) 0x45b130 LDR	X3, [X14]

(857) 0x45b134 UBFM	X4, X3, #61, #60

(857) 0x45b138 ADD	X8, X4, #8

(857) 0x45b13c LDR	X14, [X0, X4]

(857) 0x45b140 LDR	X2, [X1, X8]

(857) 0x45b144 LDR	X0, [X1, X4]

(857) 0x45b148 ADD	X5, X14, X2

(857) 0x45b14c SUB	X1, X5, X0

(857) 0x45b150 CMP	X14, X1

(857) 0x45b154 B.GE	45b300

(857) 0x45b158 SUB	X13, X0, X14

(857) 0x45b15c ADD	X13, X13, X1

(857) 0x45b160 LDR	X1, [SP, #272]

(857) 0x45b164 SUB	X2, X13, X0

(857) 0x45b168 ANDS	X5, X2, #4224

(857) 0x45b16c LDR	X2, [SP, #136]

(857) 0x45b170 LDR	X2, [X1, X2]

(857) 0x45b174 SUB	X1, XZR, X0,LSL #3

(857) 0x45b178 ADD	X14, X1, X14,LSL #3

(857) 0x45b17c ADD	X1, X2, X14

(857) 0x45b180 B.EQ	45b248

(857) 0x45b184 CMP	X5, #1

(857) 0x45b188 B.EQ	45b22c

(857) 0x45b18c CMP	X5, #2

(857) 0x45b190 B.EQ	45b218

(857) 0x45b194 CMP	X5, #3

(857) 0x45b198 B.EQ	45b204

(857) 0x45b19c CMP	X5, #4

(857) 0x45b1a0 B.EQ	45b1f0

(857) 0x45b1a4 CMP	X5, #5

(857) 0x45b1a8 B.EQ	45b1dc

(857) 0x45b1ac CMP	X5, #6

(857) 0x45b1b0 B.EQ	45b1c8

(857) 0x45b1b4 LDR	X5, [X1, X0,LSL #3]

(857) 0x45b1b8 STR	X0, [X23, X5,LSL #3]

(857) 0x45b1bc STR	XZR, [X20, X0,LSL #3]

(857) 0x45b1c0 ADD	X0, X0, #1

(857) 0x45b1c4 STR	X5, [X16, X0,LSL #3]

(857) 0x45b1c8 LDR	X2, [X1, X0,LSL #3]

(857) 0x45b1cc STR	X0, [X23, X2,LSL #3]

(857) 0x45b1d0 STR	XZR, [X20, X0,LSL #3]

(857) 0x45b1d4 ADD	X0, X0, #1

(857) 0x45b1d8 STR	X2, [X16, X0,LSL #3]

(857) 0x45b1dc LDR	X14, [X1, X0,LSL #3]

(857) 0x45b1e0 STR	X0, [X23, X14,LSL #3]

(857) 0x45b1e4 STR	XZR, [X20, X0,LSL #3]

(857) 0x45b1e8 ADD	X0, X0, #1

(857) 0x45b1ec STR	X14, [X16, X0,LSL #3]

(857) 0x45b1f0 LDR	X5, [X1, X0,LSL #3]

(857) 0x45b1f4 STR	X0, [X23, X5,LSL #3]

(857) 0x45b1f8 STR	XZR, [X20, X0,LSL #3]

(857) 0x45b1fc ADD	X0, X0, #1

(857) 0x45b200 STR	X5, [X16, X0,LSL #3]

(857) 0x45b204 LDR	X2, [X1, X0,LSL #3]

(857) 0x45b208 STR	X0, [X23, X2,LSL #3]

(857) 0x45b20c STR	XZR, [X20, X0,LSL #3]

(857) 0x45b210 ADD	X0, X0, #1

(857) 0x45b214 STR	X2, [X16, X0,LSL #3]

(857) 0x45b218 LDR	X14, [X1, X0,LSL #3]

(857) 0x45b21c STR	X0, [X23, X14,LSL #3]

(857) 0x45b220 STR	XZR, [X20, X0,LSL #3]

(857) 0x45b224 ADD	X0, X0, #1

(857) 0x45b228 STR	X14, [X16, X0,LSL #3]

(857) 0x45b22c LDR	X5, [X1, X0,LSL #3]

(857) 0x45b230 STR	X0, [X23, X5,LSL #3]

(857) 0x45b234 STR	XZR, [X20, X0,LSL #3]

(857) 0x45b238 ADD	X0, X0, #1

(857) 0x45b23c STR	X5, [X16, X0,LSL #3]

(857) 0x45b240 CMP	X13, X0

(857) 0x45b244 B.EQ	45b300

(857) 0x45b248 STP	X26, X15, [SP, #144]

(857) 0x45b24c STP	X22, X28, [SP, #160]

  (868) 0x45b250 ADD	X2, X0, #1

  (868) 0x45b254 ADD	X26, X0, #2

  (868) 0x45b258 ADD	X22, X0, #3

  (868) 0x45b25c ADD	X15, X0, #4

  (868) 0x45b260 LDR	X28, [X1, X0,LSL #3]

  (868) 0x45b264 ADD	X14, X0, #5

  (868) 0x45b268 ADD	X5, X0, #6

  (868) 0x45b26c STR	X0, [X23, X28,LSL #3]

  (868) 0x45b270 STR	XZR, [X20, X0,LSL #3]

  (868) 0x45b274 STR	X28, [X16, X2,LSL #3]

  (868) 0x45b278 LDR	X28, [X1, X2,LSL #3]

  (868) 0x45b27c STR	X2, [X23, X28,LSL #3]

  (868) 0x45b280 STR	XZR, [X20, X2,LSL #3]

  (868) 0x45b284 ADD	X2, X0, #7

  (868) 0x45b288 ADD	X0, X0, #8

  (868) 0x45b28c STR	X28, [X16, X26,LSL #3]

  (868) 0x45b290 LDR	X28, [X1, X26,LSL #3]

  (868) 0x45b294 STR	X26, [X23, X28,LSL #3]

  (868) 0x45b298 STR	XZR, [X20, X26,LSL #3]

  (868) 0x45b29c STR	X28, [X16, X22,LSL #3]

  (868) 0x45b2a0 LDR	X26, [X1, X22,LSL #3]

  (868) 0x45b2a4 STR	X22, [X23, X26,LSL #3]

  (868) 0x45b2a8 STR	XZR, [X20, X22,LSL #3]

  (868) 0x45b2ac STR	X26, [X16, X15,LSL #3]

  (868) 0x45b2b0 LDR	X22, [X1, X15,LSL #3]

  (868) 0x45b2b4 STR	X15, [X23, X22,LSL #3]

  (868) 0x45b2b8 STR	XZR, [X20, X15,LSL #3]

  (868) 0x45b2bc STR	X22, [X16, X14,LSL #3]

  (868) 0x45b2c0 LDR	X15, [X1, X14,LSL #3]

  (868) 0x45b2c4 STR	X14, [X23, X15,LSL #3]

  (868) 0x45b2c8 STR	XZR, [X20, X14,LSL #3]

  (868) 0x45b2cc STR	X15, [X16, X5,LSL #3]

  (868) 0x45b2d0 LDR	X14, [X1, X5,LSL #3]

  (868) 0x45b2d4 STR	X5, [X23, X14,LSL #3]

  (868) 0x45b2d8 STR	XZR, [X20, X5,LSL #3]

  (868) 0x45b2dc STR	X14, [X16, X2,LSL #3]

  (868) 0x45b2e0 LDR	X5, [X1, X2,LSL #3]

  (868) 0x45b2e4 STR	X2, [X23, X5,LSL #3]

  (868) 0x45b2e8 STR	XZR, [X20, X2,LSL #3]

  (868) 0x45b2ec STR	X5, [X16, X0,LSL #3]

  (868) 0x45b2f0 CMP	X13, X0

  (868) 0x45b2f4 B.NE	45b250

(857) 0x45b2f8 LDP	X26, X15, [SP, #144]

(857) 0x45b2fc LDP	X22, X28, [SP, #160]

(857) 0x45b300 LDR	X0, [SP, #112]

(857) 0x45b304 LDR	X13, [SP, #192]

(857) 0x45b308 LDR	X2, [X0, X8]

(857) 0x45b30c LDR	X1, [X13, X4]

(857) 0x45b310 LDR	X0, [X0, X4]

(857) 0x45b314 ADD	X14, X1, X2

(857) 0x45b318 SUB	X5, X14, X0

(857) 0x45b31c CMP	X1, X5

(857) 0x45b320 B.GE	45b4f0

(857) 0x45b324 LDR	X13, [SP, #136]

(857) 0x45b328 LDR	X2, [SP, #264]

(857) 0x45b32c LDR	X14, [X2, X13]

(857) 0x45b330 SUB	X13, X0, X1

(857) 0x45b334 UBFM	X1, X1, #61, #60

(857) 0x45b338 ADD	X13, X13, X5

(857) 0x45b33c SUB	X2, X1, X0,LSL #3

(857) 0x45b340 SUB	X5, X13, X0

(857) 0x45b344 ANDS	X5, X5, #4224

(857) 0x45b348 ADD	X1, X14, X2

(857) 0x45b34c B.EQ	45c134

(857) 0x45b350 CMP	X5, #1

(857) 0x45b354 B.EQ	45b410

(857) 0x45b358 CMP	X5, #2

(857) 0x45b35c B.EQ	45b3f8

(857) 0x45b360 CMP	X5, #3

(857) 0x45b364 B.EQ	45b3e0

(857) 0x45b368 CMP	X5, #4

(857) 0x45b36c B.EQ	45b3c8

(857) 0x45b370 CMP	X5, #5

(857) 0x45b374 B.EQ	45b3b0

(857) 0x45b378 CMP	X5, #6

(857) 0x45b37c B.EQ	45b398

(857) 0x45b380 LDR	X14, [X1, X0,LSL #3]

(857) 0x45b384 LDR	X2, [SP, #104]

(857) 0x45b388 STR	X0, [X22, X14,LSL #3]

(857) 0x45b38c STR	XZR, [X19, X0,LSL #3]

(857) 0x45b390 ADD	X0, X0, #1

(857) 0x45b394 STR	X14, [X2, X0,LSL #3]

(857) 0x45b398 LDR	X5, [X1, X0,LSL #3]

(857) 0x45b39c LDR	X14, [SP, #104]

(857) 0x45b3a0 STR	X0, [X22, X5,LSL #3]

(857) 0x45b3a4 STR	XZR, [X19, X0,LSL #3]

(857) 0x45b3a8 ADD	X0, X0, #1

(857) 0x45b3ac STR	X5, [X14, X0,LSL #3]

(857) 0x45b3b0 LDR	X5, [X1, X0,LSL #3]

(857) 0x45b3b4 LDR	X2, [SP, #104]

(857) 0x45b3b8 STR	X0, [X22, X5,LSL #3]

(857) 0x45b3bc STR	XZR, [X19, X0,LSL #3]

(857) 0x45b3c0 ADD	X0, X0, #1

(857) 0x45b3c4 STR	X5, [X2, X0,LSL #3]

(857) 0x45b3c8 LDR	X14, [X1, X0,LSL #3]

(857) 0x45b3cc LDR	X5, [SP, #104]

(857) 0x45b3d0 STR	X0, [X22, X14,LSL #3]

(857) 0x45b3d4 STR	XZR, [X19, X0,LSL #3]

(857) 0x45b3d8 ADD	X0, X0, #1

(857) 0x45b3dc STR	X14, [X5, X0,LSL #3]

(857) 0x45b3e0 LDR	X14, [X1, X0,LSL #3]

(857) 0x45b3e4 LDR	X2, [SP, #104]

(857) 0x45b3e8 STR	X0, [X22, X14,LSL #3]

(857) 0x45b3ec STR	XZR, [X19, X0,LSL #3]

(857) 0x45b3f0 ADD	X0, X0, #1

(857) 0x45b3f4 STR	X14, [X2, X0,LSL #3]

(857) 0x45b3f8 LDR	X5, [X1, X0,LSL #3]

(857) 0x45b3fc LDR	X14, [SP, #104]

(857) 0x45b400 STR	X0, [X22, X5,LSL #3]

(857) 0x45b404 STR	XZR, [X19, X0,LSL #3]

(857) 0x45b408 ADD	X0, X0, #1

(857) 0x45b40c STR	X5, [X14, X0,LSL #3]

(857) 0x45b410 LDR	X5, [X1, X0,LSL #3]

(857) 0x45b414 LDR	X2, [SP, #104]

(857) 0x45b418 STR	X0, [X22, X5,LSL #3]

(857) 0x45b41c STR	XZR, [X19, X0,LSL #3]

(857) 0x45b420 ADD	X0, X0, #1

(857) 0x45b424 STR	X5, [X2, X0,LSL #3]

(857) 0x45b428 CMP	X0, X13

(857) 0x45b42c B.EQ	45b4f0

(857) 0x45b430 STP	X26, X15, [SP, #144]

(857) 0x45b434 STP	X23, X28, [SP, #160]

(857) 0x45b438 STR	X9, [SP, #176]

  (867) 0x45b43c LDR	X9, [X1, X0,LSL #3]

  (867) 0x45b440 ADD	X5, X0, #1

  (867) 0x45b444 ADD	X26, X0, #2

  (867) 0x45b448 ADD	X23, X0, #3

  (867) 0x45b44c ADD	X15, X0, #4

  (867) 0x45b450 ADD	X14, X0, #5

  (867) 0x45b454 STR	X0, [X22, X9,LSL #3]

  (867) 0x45b458 STR	XZR, [X19, X0,LSL #3]

  (867) 0x45b45c STR	X9, [X2, X5,LSL #3]

  (867) 0x45b460 ADD	X9, X0, #6

  (867) 0x45b464 LDR	X28, [X1, X5,LSL #3]

  (867) 0x45b468 STR	X5, [X22, X28,LSL #3]

  (867) 0x45b46c STR	XZR, [X19, X5,LSL #3]

  (867) 0x45b470 ADD	X5, X0, #7

  (867) 0x45b474 ADD	X0, X0, #8

  (867) 0x45b478 STR	X28, [X2, X26,LSL #3]

  (867) 0x45b47c LDR	X28, [X1, X26,LSL #3]

  (867) 0x45b480 STR	X26, [X22, X28,LSL #3]

  (867) 0x45b484 STR	XZR, [X19, X26,LSL #3]

  (867) 0x45b488 STR	X28, [X2, X23,LSL #3]

  (867) 0x45b48c LDR	X26, [X1, X23,LSL #3]

  (867) 0x45b490 STR	X23, [X22, X26,LSL #3]

  (867) 0x45b494 STR	XZR, [X19, X23,LSL #3]

  (867) 0x45b498 STR	X26, [X2, X15,LSL #3]

  (867) 0x45b49c LDR	X23, [X1, X15,LSL #3]

  (867) 0x45b4a0 STR	X15, [X22, X23,LSL #3]

  (867) 0x45b4a4 STR	XZR, [X19, X15,LSL #3]

  (867) 0x45b4a8 STR	X23, [X2, X14,LSL #3]

  (867) 0x45b4ac LDR	X15, [X1, X14,LSL #3]

  (867) 0x45b4b0 STR	X14, [X22, X15,LSL #3]

  (867) 0x45b4b4 STR	XZR, [X19, X14,LSL #3]

  (867) 0x45b4b8 STR	X15, [X2, X9,LSL #3]

  (867) 0x45b4bc LDR	X14, [X1, X9,LSL #3]

  (867) 0x45b4c0 STR	X9, [X22, X14,LSL #3]

  (867) 0x45b4c4 STR	XZR, [X19, X9,LSL #3]

  (867) 0x45b4c8 STR	X14, [X2, X5,LSL #3]

  (867) 0x45b4cc LDR	X9, [X1, X5,LSL #3]

  (867) 0x45b4d0 STR	X5, [X22, X9,LSL #3]

  (867) 0x45b4d4 STR	XZR, [X19, X5,LSL #3]

  (867) 0x45b4d8 STR	X9, [X2, X0,LSL #3]

  (867) 0x45b4dc CMP	X0, X13

  (867) 0x45b4e0 B.NE	45b43c

(857) 0x45b4e4 LDR	X9, [SP, #176]

(857) 0x45b4e8 LDP	X26, X15, [SP, #144]

(857) 0x45b4ec LDP	X23, X28, [SP, #160]

(857) 0x45b4f0 LDR	X0, [SP, #216]

(857) 0x45b4f4 LDR	X1, [X0, X4]

(857) 0x45b4f8 ADD	X14, X0, X8

(857) 0x45b4fc LDR	X13, [X0, X8]

(857) 0x45b500 CMP	X1, X13

(857) 0x45b504 B.GE	45b52c

  (866) 0x45b508 LDR	X2, [X11, X1,LSL #3]

  (866) 0x45b50c LDR	X5, [SP, #96]

  (866) 0x45b510 UBFM	X0, X2, #61, #60

  (866) 0x45b514 LDR	X2, [X9, X0]

  (866) 0x45b518 CMP	X5, X2

  (866) 0x45b51c B.EQ	45bb1c

  (866) 0x45b520 ADD	X1, X1, #1

  (866) 0x45b524 CMP	X1, X13

  (866) 0x45b528 B.LT	45b508

(857) 0x45b52c LDR	X0, [SP, #208]

(857) 0x45b530 LDR	X1, [X0, X4]

(857) 0x45b534 ADD	X14, X0, X8

(857) 0x45b538 LDR	X13, [X0, X8]

(857) 0x45b53c CMP	X1, X13

(857) 0x45b540 B.GE	45b568

  (865) 0x45b544 LDR	X2, [X10, X1,LSL #3]

  (865) 0x45b548 LDR	X5, [SP, #96]

  (865) 0x45b54c UBFM	X0, X2, #61, #60

  (865) 0x45b550 LDR	X2, [X28, X0]

  (865) 0x45b554 CMP	X5, X2

  (865) 0x45b558 B.EQ	45bb04

  (865) 0x45b55c ADD	X1, X1, #1

  (865) 0x45b560 CMP	X1, X13

  (865) 0x45b564 B.LT	45b544

(857) 0x45b568 LDR	X14, [SP, #232]

(857) 0x45b56c MOVI	D20, #0

(857) 0x45b570 FMOV	D29, D20

(857) 0x45b574 LDR	X1, [X14, X4]

(857) 0x45b578 LDR	X14, [X14, X8]

(857) 0x45b57c ADD	X0, X1, #1

(857) 0x45b580 CMP	X0, X14

(857) 0x45b584 B.GE	45b604

(857) 0x45b588 ORR	X13, XZR, X6

(857) 0x45b58c ORR	X6, XZR, X9

(857) 0x45b590 STP	X15, X28, [SP, #144]

(857) 0x45b594 ORR	X9, XZR, X11

(857) 0x45b598 B	45b5b8

  (862) 0x45b59c LDR	X11, [X27, X2]

  (862) 0x45b5a0 LDR	X5, [X27, X4]

  (862) 0x45b5a4 CMP	X5, X11

  (862) 0x45b5a8 B.EQ	45b5e0

  (862) 0x45b5ac ADD	X0, X0, #1

  (862) 0x45b5b0 CMP	X0, X14

  (862) 0x45b5b4 B.EQ	45b5f4

  (862) 0x45b5b8 LDR	X11, [X12, X0,LSL #3]

  (862) 0x45b5bc UBFM	X2, X11, #61, #60

  (862) 0x45b5c0 LDR	X28, [X26, X2]

  (862) 0x45b5c4 CMP	X3, X28

  (862) 0x45b5c8 B.EQ	45bb34

  (862) 0x45b5cc LDR	X15, [X7, X2]

  (862) 0x45b5d0 CMN	X15, #3

  (862) 0x45b5d4 B.EQ	45b5ac

  (862) 0x45b5d8 CMP	X18, #1

  (862) 0x45b5dc B.NE	45b59c

  (862) 0x45b5e0 LDR	D28, [X21, X0,LSL #3]

  (862) 0x45b5e4 ADD	X0, X0, #1

  (862) 0x45b5e8 FADD	D20, D20, D28

  (862) 0x45b5ec CMP	X0, X14

  (862) 0x45b5f0 B.NE	45b5b8

(857) 0x45b5f4 LDP	X15, X28, [SP, #144]

(857) 0x45b5f8 ORR	X11, XZR, X9

(857) 0x45b5fc ORR	X9, XZR, X6

(857) 0x45b600 ORR	X6, XZR, X13

(857) 0x45b604 LDR	X13, [SP, #224]

(857) 0x45b608 LDR	X0, [X13, X4]

(857) 0x45b60c LDR	X5, [X13, X8]

(857) 0x45b610 CMP	X0, X5

(857) 0x45b614 B.GE	45b6a0

(857) 0x45b618 STP	X26, X28, [SP, #144]

(857) 0x45b61c STP	X9, X24, [SP, #160]

(857) 0x45b620 LDP	X14, X24, [SP, #248]

(857) 0x45b624 STR	X1, [SP, #176]

(857) 0x45b628 LDP	X1, X9, [SP, #280]

(857) 0x45b62c B	45b64c

  (860) 0x45b630 LDR	X28, [X1, X2]

  (860) 0x45b634 LDR	X2, [X27, X4]

  (860) 0x45b638 CMP	X28, X2

  (860) 0x45b63c B.EQ	45b680

  (860) 0x45b640 ADD	X0, X0, #1

  (860) 0x45b644 CMP	X0, X5

  (860) 0x45b648 B.EQ	45b694

  (860) 0x45b64c LDR	X28, [X9, X0,LSL #3]

  (860) 0x45b650 CBZ	X30, 45b658

  (860) 0x45b654 LDR	X28, [X24, X28,LSL #3]

  (860) 0x45b658 UBFM	X2, X28, #61, #60

  (860) 0x45b65c TBNZ	X28, #63, 45b66c

  (860) 0x45b660 LDR	X26, [X15, X2]

  (860) 0x45b664 CMP	X3, X26

  (860) 0x45b668 B.EQ	45be74

  (860) 0x45b66c LDR	X13, [X6, X2]

  (860) 0x45b670 CMN	X13, #3

  (860) 0x45b674 B.EQ	45b640

  (860) 0x45b678 CMP	X18, #1

  (860) 0x45b67c B.NE	45b630

  (860) 0x45b680 LDR	D7, [X17, X0,LSL #3]

  (860) 0x45b684 ADD	X0, X0, #1

  (860) 0x45b688 FADD	D20, D20, D7

  (860) 0x45b68c CMP	X0, X5

  (860) 0x45b690 B.NE	45b64c

(857) 0x45b694 LDR	X1, [SP, #176]

(857) 0x45b698 LDP	X26, X28, [SP, #144]

(857) 0x45b69c LDP	X9, X24, [SP, #160]

(857) 0x45b6a0 LDR	D21, [X21, X1,LSL #3]

(857) 0x45b6a4 FMUL	D22, D29, D21

(857) 0x45b6a8 FCMP	D22, #0

(857) 0x45b6ac B.EQ	45b6b8

(857) 0x45b6b0 FNEG	D20, D20

(857) 0x45b6b4 FDIV	D31, D20, D22

(857) 0x45b6b8 LDR	X3, [SP, #120]

(857) 0x45b6bc LDR	X1, [X3, X4]

(857) 0x45b6c0 LDR	X14, [X3, X8]

(857) 0x45b6c4 CMP	X1, X14

(857) 0x45b6c8 B.GE	45b8b8

(857) 0x45b6cc SUB	X13, X14, X1

(857) 0x45b6d0 SUB	X2, X13, #1

(857) 0x45b6d4 CMP	X2, #2

(857) 0x45b6d8 B.LS	45b870

(857) 0x45b6dc UBFM	X3, X13, #2, #63

(857) 0x45b6e0 ADD	X0, X20, X1,LSL #3

(857) 0x45b6e4 DUP	V23.2D, V31.D[0]

(857) 0x45b6e8 UBFM	X2, X1, #61, #60

(857) 0x45b6ec UBFM	X5, X3, #59, #58

(857) 0x45b6f0 SUB	X5, X5, #32

(857) 0x45b6f4 ADD	X3, X0, X3,LSL #5

(857) 0x45b6f8 UBFM	X5, X5, #5, #63

(857) 0x45b6fc ADD	X5, X5, #1

(857) 0x45b700 ANDS	X5, X5, #4224

(857) 0x45b704 B.EQ	45b7bc

(857) 0x45b708 CMP	X5, #1

(857) 0x45b70c B.EQ	45b7a4

(857) 0x45b710 CMP	X5, #2

(857) 0x45b714 B.EQ	45b794

(857) 0x45b718 CMP	X5, #3

(857) 0x45b71c B.EQ	45b784

(857) 0x45b720 CMP	X5, #4

(857) 0x45b724 B.EQ	45b774

(857) 0x45b728 CMP	X5, #5

(857) 0x45b72c B.EQ	45b764

(857) 0x45b730 CMP	X5, #6

(857) 0x45b734 B.EQ	45b754

(857) 0x45b738 LDR	Q27, [X20, X2]

(857) 0x45b73c ADD	X0, X0, #32

(857) 0x45b740 LDUR	Q17, [X0, #496]

(857) 0x45b744 FMUL	V30.2D, V27.2D, V23.2D

(857) 0x45b748 FMUL	V18.2D, V17.2D, V23.2D

(857) 0x45b74c STR	Q30, [X20, X2]

(857) 0x45b750 STUR	Q18, [X0, #496]

(857) 0x45b754 LDP	Q0, Q28, [X0]

(857) 0x45b758 FMUL	V26.2D, V0.2D, V23.2D

(857) 0x45b75c FMUL	V1.2D, V28.2D, V23.2D

(857) 0x45b760 STP	Q26, Q1, [X0], #32

(857) 0x45b764 LDP	Q25, Q24, [X0]

(857) 0x45b768 FMUL	V2.2D, V25.2D, V23.2D

(857) 0x45b76c FMUL	V7.2D, V24.2D, V23.2D

(857) 0x45b770 STP	Q2, Q7, [X0], #32

(857) 0x45b774 LDP	Q3, Q6, [X0]

(857) 0x45b778 FMUL	V16.2D, V3.2D, V23.2D

(857) 0x45b77c FMUL	V5.2D, V6.2D, V23.2D

(857) 0x45b780 STP	Q16, Q5, [X0], #32

(857) 0x45b784 LDP	Q19, Q4, [X0]

(857) 0x45b788 FMUL	V29.2D, V19.2D, V23.2D

(857) 0x45b78c FMUL	V21.2D, V4.2D, V23.2D

(857) 0x45b790 STP	Q29, Q21, [X0], #32

(857) 0x45b794 LDP	Q22, Q20, [X0]

(857) 0x45b798 FMUL	V27.2D, V22.2D, V23.2D

(857) 0x45b79c FMUL	V30.2D, V20.2D, V23.2D

(857) 0x45b7a0 STP	Q27, Q30, [X0], #32

(857) 0x45b7a4 LDP	Q17, Q18, [X0]

(857) 0x45b7a8 FMUL	V0.2D, V17.2D, V23.2D

(857) 0x45b7ac FMUL	V28.2D, V18.2D, V23.2D

(857) 0x45b7b0 STP	Q0, Q28, [X0], #32

(857) 0x45b7b4 CMP	X3, X0

(857) 0x45b7b8 B.EQ	45b860

(857) 0x45b7bc STP	X26, X15, [SP, #144]

(857) 0x45b7c0 STP	X23, X22, [SP, #160]

  (859) 0x45b7c4 ORR	X22, XZR, X0

  (859) 0x45b7c8 LDP	Q26, Q1, [X0]

  (859) 0x45b7cc LDP	Q29, Q21, [X0, #32]

  (859) 0x45b7d0 LDP	Q22, Q19, [X0, #64]

  (859) 0x45b7d4 LDP	Q16, Q27, [X0, #96]

  (859) 0x45b7d8 LDP	Q6, Q7, [X0, #128]

  (859) 0x45b7dc FMUL	V25.2D, V26.2D, V23.2D

  (859) 0x45b7e0 LDP	Q0, Q5, [X0, #160]

  (859) 0x45b7e4 FMUL	V24.2D, V1.2D, V23.2D

  (859) 0x45b7e8 LDP	Q3, Q4, [X0, #192]

  (859) 0x45b7ec FMUL	V20.2D, V29.2D, V23.2D

  (859) 0x45b7f0 LDP	Q30, Q2, [X0, #224]

  (859) 0x45b7f4 ADD	X0, X0, #256

  (859) 0x45b7f8 FMUL	V28.2D, V21.2D, V23.2D

  (859) 0x45b7fc FMUL	V18.2D, V22.2D, V23.2D

  (859) 0x45b800 FMUL	V26.2D, V19.2D, V23.2D

  (859) 0x45b804 FMUL	V1.2D, V16.2D, V23.2D

  (859) 0x45b808 FMUL	V17.2D, V27.2D, V23.2D

  (859) 0x45b80c FMUL	V29.2D, V7.2D, V23.2D

  (859) 0x45b810 FMUL	V21.2D, V5.2D, V23.2D

  (859) 0x45b814 FMUL	V22.2D, V3.2D, V23.2D

  (859) 0x45b818 FMUL	V19.2D, V4.2D, V23.2D

  (859) 0x45b81c FMUL	V16.2D, V30.2D, V23.2D

  (859) 0x45b820 STP	Q25, Q24, [X0, #1792]

  (859) 0x45b824 FMUL	V25.2D, V6.2D, V23.2D

  (859) 0x45b828 FMUL	V24.2D, V0.2D, V23.2D

  (859) 0x45b82c FMUL	V27.2D, V2.2D, V23.2D

  (859) 0x45b830 STUR	Q16, [X0, #480]

  (859) 0x45b834 STP	Q20, Q28, [X0, #1824]

  (859) 0x45b838 STP	Q18, Q26, [X0, #1856]

  (859) 0x45b83c STP	Q1, Q17, [X0, #1888]

  (859) 0x45b840 STP	Q25, Q29, [X0, #1920]

  (859) 0x45b844 STP	Q24, Q21, [X0, #1952]

  (859) 0x45b848 STP	Q22, Q19, [X0, #1984]

  (859) 0x45b84c STR	Q27, [X22, #240]

  (859) 0x45b850 CMP	X3, X0

  (859) 0x45b854 B.NE	45b7c4

(857) 0x45b858 LDP	X26, X15, [SP, #144]

(857) 0x45b85c LDP	X23, X22, [SP, #160]

(857) 0x45b860 AND	X2, X13, #8062

(857) 0x45b864 ADD	X1, X1, X2

(857) 0x45b868 ANDS	XZR, X13, #4160

(857) 0x45b86c B.EQ	45b8b8

(857) 0x45b870 UBFM	X13, X1, #61, #60

(857) 0x45b874 ADD	X3, X1, #1

(857) 0x45b878 LDR	D23, [X20, X13]

(857) 0x45b87c FMUL	D6, D23, D31

(857) 0x45b880 STR	D6, [X20, X13]

(857) 0x45b884 CMP	X14, X3

(857) 0x45b888 B.LE	45b8b8

(857) 0x45b88c ADD	X5, X13, #8

(857) 0x45b890 ADD	X0, X1, #2

(857) 0x45b894 LDR	D7, [X20, X5]

(857) 0x45b898 FMUL	D0, D7, D31

(857) 0x45b89c STR	D0, [X20, X5]

(857) 0x45b8a0 CMP	X0, X14

(857) 0x45b8a4 B.GE	45b8b8

(857) 0x45b8a8 ADD	X14, X13, #16

(857) 0x45b8ac LDR	D5, [X20, X14]

(857) 0x45b8b0 FMUL	D3, D5, D31

(857) 0x45b8b4 STR	D3, [X20, X14]

(857) 0x45b8b8 LDR	X2, [SP, #112]

(857) 0x45b8bc LDR	X1, [X2, X4]

(857) 0x45b8c0 LDR	X8, [X2, X8]

(857) 0x45b8c4 CMP	X1, X8

(857) 0x45b8c8 B.GE	45bab0

(857) 0x45b8cc SUB	X5, X8, X1

(857) 0x45b8d0 SUB	X4, X5, #1

(857) 0x45b8d4 CMP	X4, #2

(857) 0x45b8d8 B.LS	45ba68

(857) 0x45b8dc UBFM	X3, X5, #2, #63

(857) 0x45b8e0 ADD	X0, X19, X1,LSL #3

(857) 0x45b8e4 DUP	V28.2D, V31.D[0]

(857) 0x45b8e8 UBFM	X13, X1, #61, #60

(857) 0x45b8ec UBFM	X14, X3, #59, #58

(857) 0x45b8f0 SUB	X2, X14, #32

(857) 0x45b8f4 ADD	X3, X0, X3,LSL #5

(857) 0x45b8f8 UBFM	X4, X2, #5, #63

(857) 0x45b8fc ADD	X14, X4, #1

(857) 0x45b900 ANDS	X2, X14, #4224

(857) 0x45b904 B.EQ	45b9bc

(857) 0x45b908 CMP	X2, #1

(857) 0x45b90c B.EQ	45b9a4

(857) 0x45b910 CMP	X2, #2

(857) 0x45b914 B.EQ	45b994

(857) 0x45b918 CMP	X2, #3

(857) 0x45b91c B.EQ	45b984

(857) 0x45b920 CMP	X2, #4

(857) 0x45b924 B.EQ	45b974

(857) 0x45b928 CMP	X2, #5

(857) 0x45b92c B.EQ	45b964

(857) 0x45b930 CMP	X2, #6

(857) 0x45b934 B.EQ	45b954

(857) 0x45b938 LDR	Q4, [X19, X13]

(857) 0x45b93c ADD	X0, X0, #32

(857) 0x45b940 LDUR	Q2, [X0, #496]

(857) 0x45b944 FMUL	V30.2D, V4.2D, V28.2D

(857) 0x45b948 FMUL	V20.2D, V2.2D, V28.2D

(857) 0x45b94c STR	Q30, [X19, X13]

(857) 0x45b950 STUR	Q20, [X0, #496]

(857) 0x45b954 LDP	Q18, Q26, [X0]

(857) 0x45b958 FMUL	V1.2D, V18.2D, V28.2D

(857) 0x45b95c FMUL	V17.2D, V26.2D, V28.2D

(857) 0x45b960 STP	Q1, Q17, [X0], #32

(857) 0x45b964 LDP	Q25, Q29, [X0]

(857) 0x45b968 FMUL	V24.2D, V25.2D, V28.2D

(857) 0x45b96c FMUL	V21.2D, V29.2D, V28.2D

(857) 0x45b970 STP	Q24, Q21, [X0], #32

(857) 0x45b974 LDP	Q22, Q19, [X0]

(857) 0x45b978 FMUL	V16.2D, V22.2D, V28.2D

(857) 0x45b97c FMUL	V27.2D, V19.2D, V28.2D

(857) 0x45b980 STP	Q16, Q27, [X0], #32

(857) 0x45b984 LDP	Q23, Q6, [X0]

(857) 0x45b988 FMUL	V7.2D, V23.2D, V28.2D

(857) 0x45b98c FMUL	V0.2D, V6.2D, V28.2D

(857) 0x45b990 STP	Q7, Q0, [X0], #32

(857) 0x45b994 LDP	Q5, Q4, [X0]

(857) 0x45b998 FMUL	V3.2D, V5.2D, V28.2D

(857) 0x45b99c FMUL	V30.2D, V4.2D, V28.2D

(857) 0x45b9a0 STP	Q3, Q30, [X0], #32

(857) 0x45b9a4 LDP	Q20, Q2, [X0]

(857) 0x45b9a8 FMUL	V18.2D, V20.2D, V28.2D

(857) 0x45b9ac FMUL	V26.2D, V2.2D, V28.2D

(857) 0x45b9b0 STP	Q18, Q26, [X0], #32

(857) 0x45b9b4 CMP	X3, X0

(857) 0x45b9b8 B.EQ	45ba58

(857) 0x45b9bc STP	X26, X15, [SP, #144]

  (858) 0x45b9c0 ORR	X15, XZR, X0

  (858) 0x45b9c4 LDP	Q1, Q17, [X0]

  (858) 0x45b9c8 LDP	Q21, Q22, [X0, #32]

  (858) 0x45b9cc LDP	Q19, Q27, [X0, #64]

  (858) 0x45b9d0 LDP	Q23, Q0, [X0, #96]

  (858) 0x45b9d4 LDP	Q7, Q16, [X0, #128]

  (858) 0x45b9d8 FMUL	V25.2D, V1.2D, V28.2D

  (858) 0x45b9dc LDP	Q5, Q6, [X0, #160]

  (858) 0x45b9e0 FMUL	V29.2D, V17.2D, V28.2D

  (858) 0x45b9e4 LDP	Q3, Q4, [X0, #192]

  (858) 0x45b9e8 FMUL	V26.2D, V21.2D, V28.2D

  (858) 0x45b9ec LDP	Q30, Q24, [X0, #224]

  (858) 0x45b9f0 ADD	X0, X0, #256

  (858) 0x45b9f4 FMUL	V1.2D, V22.2D, V28.2D

  (858) 0x45b9f8 FMUL	V20.2D, V27.2D, V28.2D

  (858) 0x45b9fc FMUL	V17.2D, V23.2D, V28.2D

  (858) 0x45ba00 FMUL	V18.2D, V0.2D, V28.2D

  (858) 0x45ba04 FMUL	V21.2D, V16.2D, V28.2D

  (858) 0x45ba08 FMUL	V22.2D, V5.2D, V28.2D

  (858) 0x45ba0c FMUL	V27.2D, V3.2D, V28.2D

  (858) 0x45ba10 FMUL	V23.2D, V4.2D, V28.2D

  (858) 0x45ba14 FMUL	V2.2D, V30.2D, V28.2D

  (858) 0x45ba18 STP	Q25, Q29, [X0, #1792]

  (858) 0x45ba1c FMUL	V25.2D, V19.2D, V28.2D

  (858) 0x45ba20 FMUL	V29.2D, V7.2D, V28.2D

  (858) 0x45ba24 FMUL	V19.2D, V6.2D, V28.2D

  (858) 0x45ba28 STUR	Q2, [X0, #480]

  (858) 0x45ba2c FMUL	V0.2D, V24.2D, V28.2D

  (858) 0x45ba30 STP	Q26, Q1, [X0, #1824]

  (858) 0x45ba34 STP	Q25, Q20, [X0, #1856]

  (858) 0x45ba38 STP	Q17, Q18, [X0, #1888]

  (858) 0x45ba3c STP	Q29, Q21, [X0, #1920]

  (858) 0x45ba40 STP	Q22, Q19, [X0, #1952]

  (858) 0x45ba44 STP	Q27, Q23, [X0, #1984]

  (858) 0x45ba48 STR	Q0, [X15, #240]

  (858) 0x45ba4c CMP	X3, X0

  (858) 0x45ba50 B.NE	45b9c0

(857) 0x45ba54 LDP	X26, X15, [SP, #144]

(857) 0x45ba58 AND	X13, X5, #8062

(857) 0x45ba5c ADD	X1, X1, X13

(857) 0x45ba60 ANDS	XZR, X5, #4160

(857) 0x45ba64 B.EQ	45bab0

(857) 0x45ba68 UBFM	X5, X1, #61, #60

(857) 0x45ba6c ADD	X3, X1, #1

(857) 0x45ba70 LDR	D28, [X19, X5]

(857) 0x45ba74 FMUL	D7, D28, D31

(857) 0x45ba78 STR	D7, [X19, X5]

(857) 0x45ba7c CMP	X3, X8

(857) 0x45ba80 B.GE	45bab0

(857) 0x45ba84 ADD	X4, X5, #8

(857) 0x45ba88 ADD	X14, X1, #2

(857) 0x45ba8c LDR	D16, [X19, X4]

(857) 0x45ba90 FMUL	D5, D16, D31

(857) 0x45ba94 STR	D5, [X19, X4]

(857) 0x45ba98 CMP	X8, X14

(857) 0x45ba9c B.LE	45bab0

(857) 0x45baa0 ADD	X8, X5, #16

(857) 0x45baa4 LDR	D6, [X19, X8]

(857) 0x45baa8 FMUL	D3, D6, D31

(857) 0x45baac STR	D3, [X19, X8]

(857) 0x45bab0 LDR	X2, [SP, #128]

(857) 0x45bab4 LDR	X13, [SP, #240]

(857) 0x45bab8 ADD	X0, X2, #8

(857) 0x45babc STR	X0, [SP, #128]

(857) 0x45bac0 CMP	X13, X0

(857) 0x45bac4 B.NE	45b124

0x45bac8 ORR	X0, XZR, X26

0x45bacc STR	X15, [SP, #96]

0x45bad0 BL	52b3a0

0x45bad4 LDR	X0, [SP, #96]

0x45bad8 BL	52b3a0

0x45badc ORR	X0, XZR, X23

0x45bae0 BL	52b3a0

0x45bae4 ORR	X0, XZR, X22

0x45bae8 LDP	X19, X20, [SP, #16]

0x45baec LDP	X21, X22, [SP, #32]

0x45baf0 LDP	X23, X24, [SP, #48]

0x45baf4 LDP	X25, X26, [SP, #64]

0x45baf8 LDP	X27, X28, [SP, #80]

0x45bafc LDP	X29, X30, [SP], #368

0x45bb00 B	52b3a0

  (865) 0x45bb04 STR	X3, [X15, X0]

  (865) 0x45bb08 ADD	X1, X1, #1

  (865) 0x45bb0c LDR	X13, [X14]

  (865) 0x45bb10 CMP	X13, X1

  (865) 0x45bb14 B.GT	45b544

(857) 0x45bb18 B	45b568

  (866) 0x45bb1c STR	X3, [X26, X0]

  (866) 0x45bb20 ADD	X1, X1, #1

  (866) 0x45bb24 LDR	X13, [X14]

  (866) 0x45bb28 CMP	X13, X1

  (866) 0x45bb2c B.GT	45b508

(857) 0x45bb30 B	45b52c

  (862) 0x45bb34 LDR	X28, [SP, #120]

  (862) 0x45bb38 ADD	X11, X2, #8

  (862) 0x45bb3c LDR	X5, [X28, X2]

  (862) 0x45bb40 LDR	X15, [X28, X11]

  (862) 0x45bb44 CMP	X5, X15

  (862) 0x45bb48 B.GE	45bcd8

  (862) 0x45bb4c SUB	X28, X15, X5

  (862) 0x45bb50 ANDS	X28, X28, #4160

  (862) 0x45bb54 B.EQ	45bc00

  (862) 0x45bb58 CMP	X28, #1

  (862) 0x45bb5c B.EQ	45bbc8

  (862) 0x45bb60 CMP	X28, #2

  (862) 0x45bb64 B.EQ	45bb98

  (862) 0x45bb68 LDR	X28, [X25, X5,LSL #3]

  (862) 0x45bb6c LDR	D17, [X20, X5,LSL #3]

  (862) 0x45bb70 ADD	X5, X5, #1

  (862) 0x45bb74 LDR	D18, [X21, X0,LSL #3]

  (862) 0x45bb78 LDR	X28, [X23, X28,LSL #3]

  (862) 0x45bb7c FMUL	D0, D18, D17

  (862) 0x45bb80 UBFM	X28, X28, #61, #60

  (862) 0x45bb84 LDR	D26, [X20, X28]

  (862) 0x45bb88 FADD	D29, D29, D0

  (862) 0x45bb8c FADD	D20, D20, D0

  (862) 0x45bb90 FADD	D1, D26, D0

  (862) 0x45bb94 STR	D1, [X20, X28]

  (862) 0x45bb98 LDR	X28, [X25, X5,LSL #3]

  (862) 0x45bb9c LDR	D24, [X20, X5,LSL #3]

  (862) 0x45bba0 ADD	X5, X5, #1

  (862) 0x45bba4 LDR	D25, [X21, X0,LSL #3]

  (862) 0x45bba8 LDR	X28, [X23, X28,LSL #3]

  (862) 0x45bbac FMUL	D2, D25, D24

  (862) 0x45bbb0 UBFM	X28, X28, #61, #60

  (862) 0x45bbb4 LDR	D7, [X20, X28]

  (862) 0x45bbb8 FADD	D29, D29, D2

  (862) 0x45bbbc FADD	D20, D20, D2

  (862) 0x45bbc0 FADD	D3, D7, D2

  (862) 0x45bbc4 STR	D3, [X20, X28]

  (862) 0x45bbc8 LDR	X28, [X25, X5,LSL #3]

  (862) 0x45bbcc LDR	D5, [X20, X5,LSL #3]

  (862) 0x45bbd0 ADD	X5, X5, #1

  (862) 0x45bbd4 LDR	D6, [X21, X0,LSL #3]

  (862) 0x45bbd8 LDR	X28, [X23, X28,LSL #3]

  (862) 0x45bbdc FMUL	D31, D6, D5

  (862) 0x45bbe0 UBFM	X28, X28, #61, #60

  (862) 0x45bbe4 LDR	D4, [X20, X28]

  (862) 0x45bbe8 FADD	D29, D29, D31

  (862) 0x45bbec FADD	D20, D20, D31

  (862) 0x45bbf0 FADD	D16, D4, D31

  (862) 0x45bbf4 STR	D16, [X20, X28]

  (862) 0x45bbf8 CMP	X5, X15

  (862) 0x45bbfc B.EQ	45bcd8

  (862) 0x45bc00 STP	X26, X22, [SP, #160]

  (862) 0x45bc04 STP	X6, X13, [SP, #176]

    (864) 0x45bc08 ADD	X13, X5, #1

    (864) 0x45bc0c ADD	X26, X5, #3

    (864) 0x45bc10 ADD	X28, X13, #1

    (864) 0x45bc14 LDR	X22, [X25, X5,LSL #3]

    (864) 0x45bc18 LDR	D19, [X21, X0,LSL #3]

    (864) 0x45bc1c LDR	D21, [X20, X5,LSL #3]

    (864) 0x45bc20 ADD	X5, X5, #4

    (864) 0x45bc24 LDR	X6, [X23, X22,LSL #3]

    (864) 0x45bc28 LDR	X22, [X25, X13,LSL #3]

    (864) 0x45bc2c FMUL	D22, D19, D21

    (864) 0x45bc30 UBFM	X6, X6, #61, #60

    (864) 0x45bc34 LDR	D23, [X20, X6]

    (864) 0x45bc38 LDR	X22, [X23, X22,LSL #3]

    (864) 0x45bc3c FADD	D27, D29, D22

    (864) 0x45bc40 FADD	D30, D20, D22

    (864) 0x45bc44 FADD	D31, D23, D22

    (864) 0x45bc48 UBFM	X22, X22, #61, #60

    (864) 0x45bc4c STR	D31, [X20, X6]

    (864) 0x45bc50 LDR	D18, [X20, X13,LSL #3]

    (864) 0x45bc54 LDR	D28, [X21, X0,LSL #3]

    (864) 0x45bc58 LDR	D17, [X20, X22]

    (864) 0x45bc5c LDR	X13, [X25, X28,LSL #3]

    (864) 0x45bc60 FMUL	D0, D28, D18

    (864) 0x45bc64 LDR	X6, [X25, X26,LSL #3]

    (864) 0x45bc68 LDR	X13, [X23, X13,LSL #3]

    (864) 0x45bc6c LDR	X6, [X23, X6,LSL #3]

    (864) 0x45bc70 FADD	D26, D17, D0

    (864) 0x45bc74 FADD	D1, D27, D0

    (864) 0x45bc78 FADD	D25, D30, D0

    (864) 0x45bc7c UBFM	X13, X13, #61, #60

    (864) 0x45bc80 UBFM	X6, X6, #61, #60

    (864) 0x45bc84 STR	D26, [X20, X22]

    (864) 0x45bc88 LDR	D24, [X21, X0,LSL #3]

    (864) 0x45bc8c LDR	D2, [X20, X28,LSL #3]

    (864) 0x45bc90 LDR	D7, [X20, X13]

    (864) 0x45bc94 FMUL	D3, D24, D2

    (864) 0x45bc98 FADD	D6, D7, D3

    (864) 0x45bc9c FADD	D5, D1, D3

    (864) 0x45bca0 FADD	D4, D25, D3

    (864) 0x45bca4 STR	D6, [X20, X13]

    (864) 0x45bca8 LDR	D29, [X21, X0,LSL #3]

    (864) 0x45bcac LDR	D20, [X20, X26,LSL #3]

    (864) 0x45bcb0 LDR	D16, [X20, X6]

    (864) 0x45bcb4 FMUL	D31, D29, D20

    (864) 0x45bcb8 FADD	D19, D16, D31

    (864) 0x45bcbc FADD	D29, D5, D31

    (864) 0x45bcc0 FADD	D20, D4, D31

    (864) 0x45bcc4 STR	D19, [X20, X6]

    (864) 0x45bcc8 CMP	X5, X15

    (864) 0x45bccc B.NE	45bc08

  (862) 0x45bcd0 LDP	X26, X22, [SP, #160]

  (862) 0x45bcd4 LDP	X6, X13, [SP, #176]

  (862) 0x45bcd8 LDR	X15, [SP, #112]

  (862) 0x45bcdc LDR	X2, [X15, X2]

  (862) 0x45bce0 LDR	X28, [X15, X11]

  (862) 0x45bce4 CMP	X2, X28

  (862) 0x45bce8 B.GE	45b5ac

  (862) 0x45bcec SUB	X11, X28, X2

  (862) 0x45bcf0 ANDS	X5, X11, #4160

  (862) 0x45bcf4 B.EQ	45bda0

  (862) 0x45bcf8 CMP	X5, #1

  (862) 0x45bcfc B.EQ	45bd68

  (862) 0x45bd00 CMP	X5, #2

  (862) 0x45bd04 B.EQ	45bd38

  (862) 0x45bd08 LDR	X15, [X24, X2,LSL #3]

  (862) 0x45bd0c LDR	D22, [X19, X2,LSL #3]

  (862) 0x45bd10 ADD	X2, X2, #1

  (862) 0x45bd14 LDR	D21, [X21, X0,LSL #3]

  (862) 0x45bd18 LDR	X11, [X22, X15,LSL #3]

  (862) 0x45bd1c FMUL	D23, D21, D22

  (862) 0x45bd20 UBFM	X5, X11, #61, #60

  (862) 0x45bd24 LDR	D27, [X19, X5]

  (862) 0x45bd28 FADD	D29, D29, D23

  (862) 0x45bd2c FADD	D20, D20, D23

  (862) 0x45bd30 FADD	D30, D27, D23

  (862) 0x45bd34 STR	D30, [X19, X5]

  (862) 0x45bd38 LDR	X15, [X24, X2,LSL #3]

  (862) 0x45bd3c LDR	D28, [X19, X2,LSL #3]

  (862) 0x45bd40 ADD	X2, X2, #1

  (862) 0x45bd44 LDR	D31, [X21, X0,LSL #3]

  (862) 0x45bd48 LDR	X11, [X22, X15,LSL #3]

  (862) 0x45bd4c FMUL	D18, D31, D28

  (862) 0x45bd50 UBFM	X5, X11, #61, #60

  (862) 0x45bd54 LDR	D17, [X19, X5]

  (862) 0x45bd58 FADD	D29, D29, D18

  (862) 0x45bd5c FADD	D20, D20, D18

  (862) 0x45bd60 FADD	D0, D17, D18

  (862) 0x45bd64 STR	D0, [X19, X5]

  (862) 0x45bd68 LDR	X15, [X24, X2,LSL #3]

  (862) 0x45bd6c LDR	D1, [X19, X2,LSL #3]

  (862) 0x45bd70 ADD	X2, X2, #1

  (862) 0x45bd74 LDR	D26, [X21, X0,LSL #3]

  (862) 0x45bd78 LDR	X11, [X22, X15,LSL #3]

  (862) 0x45bd7c FMUL	D31, D26, D1

  (862) 0x45bd80 UBFM	X5, X11, #61, #60

  (862) 0x45bd84 LDR	D25, [X19, X5]

  (862) 0x45bd88 FADD	D29, D29, D31

  (862) 0x45bd8c FADD	D20, D20, D31

  (862) 0x45bd90 FADD	D24, D25, D31

  (862) 0x45bd94 STR	D24, [X19, X5]

  (862) 0x45bd98 CMP	X2, X28

  (862) 0x45bd9c B.EQ	45b5ac

  (862) 0x45bda0 STP	X26, X23, [SP, #160]

    (863) 0x45bda4 ADD	X11, X2, #1

    (863) 0x45bda8 ADD	X23, X2, #3

    (863) 0x45bdac LDR	X26, [X24, X2,LSL #3]

    (863) 0x45bdb0 LDR	D2, [X21, X0,LSL #3]

    (863) 0x45bdb4 LDR	D7, [X19, X2,LSL #3]

    (863) 0x45bdb8 ADD	X2, X2, #4

    (863) 0x45bdbc LDR	X15, [X22, X26,LSL #3]

    (863) 0x45bdc0 ADD	X26, X11, #1

    (863) 0x45bdc4 FMUL	D3, D2, D7

    (863) 0x45bdc8 UBFM	X5, X15, #61, #60

    (863) 0x45bdcc LDR	X15, [X24, X11,LSL #3]

    (863) 0x45bdd0 LDR	D6, [X19, X5]

    (863) 0x45bdd4 FADD	D5, D29, D3

    (863) 0x45bdd8 LDR	X15, [X22, X15,LSL #3]

    (863) 0x45bddc FADD	D4, D20, D3

    (863) 0x45bde0 FADD	D29, D6, D3

    (863) 0x45bde4 UBFM	X15, X15, #61, #60

    (863) 0x45bde8 STR	D29, [X19, X5]

    (863) 0x45bdec LDR	D20, [X21, X0,LSL #3]

    (863) 0x45bdf0 LDR	D16, [X19, X11,LSL #3]

    (863) 0x45bdf4 LDR	D19, [X19, X15]

    (863) 0x45bdf8 LDR	X11, [X24, X26,LSL #3]

    (863) 0x45bdfc FMUL	D21, D20, D16

    (863) 0x45be00 LDR	X5, [X24, X23,LSL #3]

    (863) 0x45be04 LDR	X11, [X22, X11,LSL #3]

    (863) 0x45be08 LDR	X5, [X22, X5,LSL #3]

    (863) 0x45be0c FADD	D22, D19, D21

    (863) 0x45be10 FADD	D23, D5, D21

    (863) 0x45be14 FADD	D27, D4, D21

    (863) 0x45be18 UBFM	X11, X11, #61, #60

    (863) 0x45be1c UBFM	X5, X5, #61, #60

    (863) 0x45be20 STR	D22, [X19, X15]

    (863) 0x45be24 LDR	D31, [X19, X26,LSL #3]

    (863) 0x45be28 LDR	D30, [X21, X0,LSL #3]

    (863) 0x45be2c LDR	D28, [X19, X11]

    (863) 0x45be30 FMUL	D17, D30, D31

    (863) 0x45be34 FADD	D18, D28, D17

    (863) 0x45be38 FADD	D0, D23, D17

    (863) 0x45be3c FADD	D26, D27, D17

    (863) 0x45be40 STR	D18, [X19, X11]

    (863) 0x45be44 LDR	D1, [X21, X0,LSL #3]

    (863) 0x45be48 LDR	D25, [X19, X23,LSL #3]

    (863) 0x45be4c LDR	D24, [X19, X5]

    (863) 0x45be50 FMUL	D31, D1, D25

    (863) 0x45be54 FADD	D2, D24, D31

    (863) 0x45be58 FADD	D29, D0, D31

    (863) 0x45be5c FADD	D20, D26, D31

    (863) 0x45be60 STR	D2, [X19, X5]

    (863) 0x45be64 CMP	X2, X28

    (863) 0x45be68 B.NE	45bda4

  (862) 0x45be6c LDP	X26, X23, [SP, #160]

  (862) 0x45be70 B	45b5ac

  (860) 0x45be74 LDP	X13, X26, [SP, #296]

  (860) 0x45be78 ADD	X28, X13, X2

  (860) 0x45be7c LDR	X2, [X26, X2]

  (860) 0x45be80 LDR	X13, [X28, #8]

  (860) 0x45be84 ADD	X26, X2, X13

  (860) 0x45be88 CMP	X2, X26

  (860) 0x45be8c B.GE	45b640

  (860) 0x45be90 LDR	X28, [SP, #136]

  (860) 0x45be94 LDR	X13, [SP, #312]

  (860) 0x45be98 LDR	X13, [X13, X28]

  (860) 0x45be9c SUB	X28, X26, X2

  (860) 0x45bea0 ANDS	X28, X28, #4160

  (860) 0x45bea4 B.EQ	45c024

  (860) 0x45bea8 CMP	X28, #1

  (860) 0x45beac B.EQ	45bf20

  (860) 0x45beb0 CMP	X28, #2

  (860) 0x45beb4 B.EQ	45beec

  (860) 0x45beb8 LDR	D3, [X17, X0,LSL #3]

  (860) 0x45bebc LDR	D6, [X14, X2,LSL #3]

  (860) 0x45bec0 LDR	X28, [X13, X2,LSL #3]

  (860) 0x45bec4 FMUL	D16, D3, D6

  (860) 0x45bec8 TBNZ	X28, #63, 45c148

  (860) 0x45becc LDR	X28, [X22, X28,LSL #3]

  (860) 0x45bed0 UBFM	X28, X28, #61, #60

  (860) 0x45bed4 LDR	D5, [X19, X28]

  (860) 0x45bed8 FADD	D4, D5, D16

  (860) 0x45bedc STR	D4, [X19, X28]

  (860) 0x45bee0 FADD	D29, D29, D16

  (860) 0x45bee4 FADD	D20, D20, D16

  (860) 0x45bee8 ADD	X2, X2, #1

  (860) 0x45beec LDR	D22, [X17, X0,LSL #3]

  (860) 0x45bef0 LDR	D23, [X14, X2,LSL #3]

  (860) 0x45bef4 LDR	X28, [X13, X2,LSL #3]

  (860) 0x45bef8 FMUL	D27, D22, D23

  (860) 0x45befc TBNZ	X28, #63, 45c118

  (860) 0x45bf00 LDR	X28, [X22, X28,LSL #3]

  (860) 0x45bf04 UBFM	X28, X28, #61, #60

  (860) 0x45bf08 LDR	D30, [X19, X28]

  (860) 0x45bf0c FADD	D31, D30, D27

  (860) 0x45bf10 STR	D31, [X19, X28]

  (860) 0x45bf14 FADD	D29, D29, D27

  (860) 0x45bf18 FADD	D20, D20, D27

  (860) 0x45bf1c ADD	X2, X2, #1

  (860) 0x45bf20 LDR	D18, [X17, X0,LSL #3]

  (860) 0x45bf24 LDR	D0, [X14, X2,LSL #3]

  (860) 0x45bf28 LDR	X28, [X13, X2,LSL #3]

  (860) 0x45bf2c FMUL	D31, D18, D0

  (860) 0x45bf30 TBNZ	X28, #63, 45c0fc

  (860) 0x45bf34 LDR	X28, [X22, X28,LSL #3]

  (860) 0x45bf38 UBFM	X28, X28, #61, #60

  (860) 0x45bf3c LDR	D26, [X19, X28]

  (860) 0x45bf40 FADD	D1, D26, D31

  (860) 0x45bf44 STR	D1, [X19, X28]

  (860) 0x45bf48 ADD	X2, X2, #1

  (860) 0x45bf4c FADD	D29, D29, D31

  (860) 0x45bf50 FADD	D20, D20, D31

  (860) 0x45bf54 CMP	X26, X2

  (860) 0x45bf58 B.NE	45c024

  (860) 0x45bf5c B	45b640

    (861) 0x45bf60 LDR	X28, [X22, X28,LSL #3]

    (861) 0x45bf64 ADD	X2, X2, #1

    (861) 0x45bf68 FADD	D29, D29, D3

    (861) 0x45bf6c FADD	D20, D20, D3

    (861) 0x45bf70 UBFM	X28, X28, #61, #60

    (861) 0x45bf74 LDR	D6, [X19, X28]

    (861) 0x45bf78 FADD	D16, D6, D3

    (861) 0x45bf7c STR	D16, [X19, X28]

    (861) 0x45bf80 LDR	D19, [X17, X0,LSL #3]

    (861) 0x45bf84 LDR	D21, [X14, X2,LSL #3]

    (861) 0x45bf88 LDR	X28, [X13, X2,LSL #3]

    (861) 0x45bf8c FMUL	D22, D19, D21

    (861) 0x45bf90 TBNZ	X28, #63, 45c070

    (861) 0x45bf94 LDR	X28, [X22, X28,LSL #3]

    (861) 0x45bf98 FADD	D18, D29, D22

    (861) 0x45bf9c FADD	D0, D20, D22

    (861) 0x45bfa0 UBFM	X28, X28, #61, #60

    (861) 0x45bfa4 LDR	D23, [X19, X28]

    (861) 0x45bfa8 FADD	D27, D23, D22

    (861) 0x45bfac STR	D27, [X19, X28]

    (861) 0x45bfb0 ADD	X28, X2, #1

    (861) 0x45bfb4 LDR	D17, [X17, X0,LSL #3]

    (861) 0x45bfb8 LDR	D28, [X14, X28,LSL #3]

    (861) 0x45bfbc LDR	X28, [X13, X28,LSL #3]

    (861) 0x45bfc0 FMUL	D26, D17, D28

    (861) 0x45bfc4 TBNZ	X28, #63, 45c0a8

    (861) 0x45bfc8 LDR	X28, [X22, X28,LSL #3]

    (861) 0x45bfcc FADD	D3, D18, D26

    (861) 0x45bfd0 FADD	D6, D0, D26

    (861) 0x45bfd4 UBFM	X28, X28, #61, #60

    (861) 0x45bfd8 LDR	D1, [X19, X28]

    (861) 0x45bfdc FADD	D25, D1, D26

    (861) 0x45bfe0 STR	D25, [X19, X28]

    (861) 0x45bfe4 ADD	X28, X2, #2

    (861) 0x45bfe8 LDR	D7, [X17, X0,LSL #3]

    (861) 0x45bfec LDR	D16, [X14, X28,LSL #3]

    (861) 0x45bff0 LDR	X28, [X13, X28,LSL #3]

    (861) 0x45bff4 FMUL	D31, D7, D16

    (861) 0x45bff8 TBNZ	X28, #63, 45c0e0

    (861) 0x45bffc LDR	X28, [X22, X28,LSL #3]

    (861) 0x45c000 UBFM	X28, X28, #61, #60

    (861) 0x45c004 LDR	D5, [X19, X28]

    (861) 0x45c008 FADD	D4, D5, D31

    (861) 0x45c00c STR	D4, [X19, X28]

    (861) 0x45c010 ADD	X2, X2, #3

    (861) 0x45c014 FADD	D29, D3, D31

    (861) 0x45c018 FADD	D20, D6, D31

    (861) 0x45c01c CMP	X26, X2

    (861) 0x45c020 B.EQ	45b640

    (861) 0x45c024 LDR	D2, [X17, X0,LSL #3]

    (861) 0x45c028 LDR	D7, [X14, X2,LSL #3]

    (861) 0x45c02c LDR	X28, [X13, X2,LSL #3]

    (861) 0x45c030 FMUL	D3, D2, D7

    (861) 0x45c034 TBZ	X28, #63, 45bf60

    (861) 0x45c038 ORN	X28, XZR, X28

    (861) 0x45c03c ADD	X2, X2, #1

    (861) 0x45c040 FADD	D29, D29, D3

    (861) 0x45c044 FADD	D20, D20, D3

    (861) 0x45c048 LDR	X28, [X23, X28,LSL #3]

    (861) 0x45c04c UBFM	X28, X28, #61, #60

    (861) 0x45c050 LDR	D5, [X20, X28]

    (861) 0x45c054 FADD	D4, D5, D3

    (861) 0x45c058 STR	D4, [X20, X28]

    (861) 0x45c05c LDR	D19, [X17, X0,LSL #3]

    (861) 0x45c060 LDR	D21, [X14, X2,LSL #3]

    (861) 0x45c064 LDR	X28, [X13, X2,LSL #3]

    (861) 0x45c068 FMUL	D22, D19, D21

    (861) 0x45c06c TBZ	X28, #63, 45bf94

    (861) 0x45c070 ORN	X28, XZR, X28

    (861) 0x45c074 FADD	D18, D29, D22

    (861) 0x45c078 FADD	D0, D20, D22

    (861) 0x45c07c LDR	X28, [X23, X28,LSL #3]

    (861) 0x45c080 UBFM	X28, X28, #61, #60

    (861) 0x45c084 LDR	D30, [X20, X28]

    (861) 0x45c088 FADD	D31, D30, D22

    (861) 0x45c08c STR	D31, [X20, X28]

    (861) 0x45c090 ADD	X28, X2, #1

    (861) 0x45c094 LDR	D17, [X17, X0,LSL #3]

    (861) 0x45c098 LDR	D28, [X14, X28,LSL #3]

    (861) 0x45c09c LDR	X28, [X13, X28,LSL #3]

    (861) 0x45c0a0 FMUL	D26, D17, D28

    (861) 0x45c0a4 TBZ	X28, #63, 45bfc8

    (861) 0x45c0a8 ORN	X28, XZR, X28

    (861) 0x45c0ac FADD	D3, D18, D26

    (861) 0x45c0b0 FADD	D6, D0, D26

    (861) 0x45c0b4 LDR	X28, [X23, X28,LSL #3]

    (861) 0x45c0b8 UBFM	X28, X28, #61, #60

    (861) 0x45c0bc LDR	D24, [X20, X28]

    (861) 0x45c0c0 FADD	D2, D24, D26

    (861) 0x45c0c4 STR	D2, [X20, X28]

    (861) 0x45c0c8 ADD	X28, X2, #2

    (861) 0x45c0cc LDR	D7, [X17, X0,LSL #3]

    (861) 0x45c0d0 LDR	D16, [X14, X28,LSL #3]

    (861) 0x45c0d4 LDR	X28, [X13, X28,LSL #3]

    (861) 0x45c0d8 FMUL	D31, D7, D16

    (861) 0x45c0dc TBZ	X28, #63, 45bffc

    (861) 0x45c0e0 ORN	X28, XZR, X28

    (861) 0x45c0e4 LDR	X28, [X23, X28,LSL #3]

    (861) 0x45c0e8 UBFM	X28, X28, #61, #60

    (861) 0x45c0ec LDR	D19, [X20, X28]

    (861) 0x45c0f0 FADD	D29, D19, D31

    (861) 0x45c0f4 STR	D29, [X20, X28]

    (861) 0x45c0f8 B	45c010

  (860) 0x45c0fc ORN	X28, XZR, X28

  (860) 0x45c100 LDR	X28, [X23, X28,LSL #3]

  (860) 0x45c104 UBFM	X28, X28, #61, #60

  (860) 0x45c108 LDR	D25, [X20, X28]

  (860) 0x45c10c FADD	D24, D25, D31

  (860) 0x45c110 STR	D24, [X20, X28]

  (860) 0x45c114 B	45bf48

  (860) 0x45c118 ORN	X28, XZR, X28

  (860) 0x45c11c LDR	X28, [X23, X28,LSL #3]

  (860) 0x45c120 UBFM	X28, X28, #61, #60

  (860) 0x45c124 LDR	D28, [X20, X28]

  (860) 0x45c128 FADD	D17, D28, D27

  (860) 0x45c12c STR	D17, [X20, X28]

  (860) 0x45c130 B	45bf14

(857) 0x45c134 LDR	X2, [SP, #104]

(857) 0x45c138 STP	X26, X15, [SP, #144]

(857) 0x45c13c STP	X23, X28, [SP, #160]

(857) 0x45c140 STR	X9, [SP, #176]

(857) 0x45c144 B	45b43c

  (860) 0x45c148 ORN	X28, XZR, X28

  (860) 0x45c14c LDR	X28, [X23, X28,LSL #3]

  (860) 0x45c150 UBFM	X28, X28, #61, #60

  (860) 0x45c154 LDR	D19, [X20, X28]

  (860) 0x45c158 FADD	D21, D19, D16

  (860) 0x45c15c STR	D21, [X20, X28]

  (860) 0x45c160 B	45bee0

0x45c164 ORR	X0, XZR, X22

0x45c168 STR	X13, [SP, #136]

0x45c16c STP	X8, X2, [SP, #152]

0x45c170 STP	X6, X10, [SP, #168]

0x45c174 STR	X11, [SP, #184]

0x45c178 STR	X9, [SP, #240]

0x45c17c STP	X12, X7, [SP, #320]

0x45c180 B	45afcc

0x45c184 ORR	X0, XZR, X23

0x45c188 MOVZ	X1, #8

0x45c18c STR	X13, [SP, #136]

0x45c190 STP	X3, X8, [SP, #152]

0x45c194 STP	X2, X6, [SP, #168]

0x45c198 STR	X10, [SP, #184]

0x45c19c STR	X11, [SP, #240]

0x45c1a0 STP	X9, X12, [SP, #320]

0x45c1a4 STR	X7, [SP, #360]

0x45c1a8 BL	52b308

0x45c1ac LDR	X13, [SP, #136]

0x45c1b0 ORR	X23, XZR, X0

0x45c1b4 LDP	X3, X8, [SP, #152]

0x45c1b8 LDP	X2, X6, [SP, #168]

0x45c1bc LDP	X9, X12, [SP, #320]

0x45c1c0 LDR	X10, [SP, #184]

0x45c1c4 LDR	X11, [SP, #240]

0x45c1c8 LDR	X7, [SP, #360]

0x45c1cc B	45afa8

0x45c1d0 MOVZ	X1, #8

0x45c1d4 STR	X3, [SP, #136]

0x45c1d8 STP	X8, X2, [SP, #152]

0x45c1dc STP	X6, X10, [SP, #168]

0x45c1e0 STR	X11, [SP, #184]

0x45c1e4 STR	X9, [SP, #240]

0x45c1e8 STP	X12, X7, [SP, #320]

0x45c1ec BL	52b308

0x45c1f0 LDR	X3, [SP, #136]

0x45c1f4 ORR	X13, XZR, X0

0x45c1f8 LDP	X8, X2, [SP, #152]

0x45c1fc LDP	X6, X10, [SP, #168]

0x45c200 LDP	X12, X7, [SP, #320]

0x45c204 LDR	X11, [SP, #184]

0x45c208 LDR	X9, [SP, #240]

0x45c20c B	45afa4

0x45c210 ORR	X0, XZR, X2

0x45c214 MOVZ	X1, #8

0x45c218 STR	X2, [SP, #136]

0x45c21c STP	X3, X8, [SP, #152]

0x45c220 STP	X6, X10, [SP, #168]

0x45c224 STR	X11, [SP, #184]

0x45c228 STR	X9, [SP, #240]

0x45c22c STP	X12, X7, [SP, #320]

0x45c230 BL	52b308

0x45c234 LDR	X2, [SP, #136]

0x45c238 ORR	X26, XZR, X0

0x45c23c LDP	X3, X8, [SP, #152]

0x45c240 LDP	X6, X10, [SP, #168]

0x45c244 LDP	X12, X7, [SP, #320]

0x45c248 LDR	X11, [SP, #184]

0x45c24c LDR	X9, [SP, #240]

0x45c250 B	45af98

0x45c254 HINT	#0

0x45c258 HINT	#0

0x45c25c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.05+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 70% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 53.17 to 41.17 cycles (1.29x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 53.17 to 5.50 cycles (9.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1008 bytes. The binary function is storing 896 bytes.

General properties

nb instructions	229
loop length	916
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	9.33	9.33	9.33	9.33	9.33	9.33	0.00	0.00	0.00	0.00	53.17	52.83	53.00	40.50	40.50
cycles	11.50	11.50	9.33	9.33	9.33	9.33	9.33	9.33	0.00	0.00	0.00	0.00	53.17	52.83	53.00	40.50	40.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	28.25
Overall L1	53.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 53.17 cycles. At this rate:

19% of peak load performance is reached (18.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.85 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45aec8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X1, X11, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X10, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X2, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X20, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X4, X25, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X5, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X6, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X6, X7, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X13, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X13, X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X14, X15, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X15, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X16, X17, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X17, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X18, X21, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X26, [X0, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X2, X23, [X0, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X8, [X0, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X26, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X27, [X0, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X30, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X30, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X4, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X2, 45c210 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45c1d0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X23, 45c184 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45c164 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x129c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45b038 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X15, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X15, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X5, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45b080 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X3, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X14, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X3, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X14, X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X5, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X2, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SDIV X3, X14, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDP X10, X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X13, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X1, X13, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X2, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X13, X14, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X14, X8, X3, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X0, X3, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X4, X13, X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45bac8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X30, X24, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X16, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X5, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X5, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X13, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X17, X30, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 52b3a0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
B 45afcc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X2, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X7, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X2, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X7, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45afa8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X13, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45afa4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45af98 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 53.17 to 5.50 cycles (9.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1008 bytes. The binary function is storing 896 bytes.

General properties

nb instructions	229
loop length	916
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

28.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	11.50	11.50	9.33	9.33	9.33	9.33	9.33	9.33	0.00	0.00	0.00	0.00	53.17	52.83	53.00	40.50	40.50
cycles	11.50	11.50	9.33	9.33	9.33	9.33	9.33	9.33	0.00	0.00	0.00	0.00	53.17	52.83	53.00	40.50	40.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	28.25
Overall L1	53.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 53.17 cycles. At this rate:

19% of peak load performance is reached (18.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.85 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45aec8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X1, X11, [X0, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X10, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X2, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X20, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X4, X25, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X5, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X24, X6, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X6, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X6, X7, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X7, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X12, X13, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X13, X12, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X14, X15, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STP X15, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X16, X17, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X17, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X18, X21, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X21, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X28, X26, [X0, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X2, X23, [X0, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X8, [X0, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X26, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X3, X27, [X0, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X30, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X7, X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X30, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X1, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X4, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X4, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X0, X5, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X0, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X5, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X2, 45c210 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X0, 45c1d0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X13, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X23, 45c184 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x12bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45c164 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x129c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X1, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45b038 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X1, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X15, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X5, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X15, X4, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X5, X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X16, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45b080 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X2, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W1, #255	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X3, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410950 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X14, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X3, X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X14, X15, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X18, X6, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52df60 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52df40 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X5, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X2, X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
SDIV X3, X14, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
LDP X10, X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X18, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X13, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X1, X13, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X2, X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X8, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X13, X14, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X14, X8, X3, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X0, X3, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X4, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X0, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X4, X13, X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X4, X1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 45bac8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xc00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X30, X24, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X16, X25, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X5, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X5, X4,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X13, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X13, X30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X17, X30, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X3, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X0, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 52b3a0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
B 52b3a0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
B 45afcc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X2, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X7, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X2, X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X12, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X10, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X7, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45afa8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X13, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45afa4 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ X1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 52b308 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X3, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X6, X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X12, X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X11, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 45af98 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.10–	1.28	0.21
▼Loop 857 - par_multi_interp.c:1774-1876 - exec–	0.26	0.03
▼Loop 862 - par_multi_interp.c:1811-1837 - exec–	0.74	0.09
○Loop 864 - par_multi_interp.c:1816-1822 - exec	0.00	0.00
○Loop 863 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 866 - par_multi_interp.c:1799-1803 - exec	0.28	0.03
○Loop 868 - par_multi_interp.c:1782-1787 - exec	0.00	0.00
○Loop 867 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 865 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
○Loop 859 - par_multi_interp.c:1873-1874 - exec	0.00	0.00
○Loop 858 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
▼Loop 860 - par_multi_interp.c:1840-1867 - exec–	0.00	0.00
○Loop 861 - par_multi_interp.c:1851-1860 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code