OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.2	Module: exec	Source: par_coarsen.c:2132-2136	Coverage (incl. loops): 0.71% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2132 - 2136

--------------------------------------------------------------------------------

2132: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

2133:    for (i=0; i < S_diag_i[num_variables]; i++)

2134:    {

2135: #pragma omp atomic

2136:       measure_array_temp[S_diag_j[i]]++;

0x429860 STP	X29, X30, [SP, #976]!

0x429864 ADD	X29, SP, #0

0x429868 STP	X19, X20, [SP, #16]

0x42986c ORR	X20, XZR, X0

0x429870 LDR	X0, [X0]

0x429874 LDR	X1, [X20, #16]

0x429878 STR	X21, [SP, #32]

0x42987c LDR	X21, [X0, X1,LSL #3]

0x429880 BL	410d60

0x429884 SBFM	X19, X0, #0, #31

0x429888 BL	410c90

0x42988c SBFM	X4, X0, #0, #31

0x429890 SDIV	X3, X21, X19

0x429894 MSUB	X2, X3, X19, X21

0x429898 CMP	X4, X2

0x42989c B.LT	4299e8

(206) 0x4298a0 MADD	X6, X3, X4, X2

(206) 0x4298a4 ADD	X7, X3, X6

(206) 0x4298a8 CMP	X6, X7

(206) 0x4298ac B.GE	4299d8

(206) 0x4298b0 LDR	X5, [X20, #8]

(206) 0x4298b4 MOVZ	X8, #1

(206) 0x4298b8 LDR	X9, [X20, #24]

(206) 0x4298bc ADD	X0, X5, X6,LSL #3

(206) 0x4298c0 ADD	X10, X5, X7,LSL #3

(206) 0x4298c4 SUB	X11, X10, X0

(206) 0x4298c8 SUB	X12, X11, #8

(206) 0x4298cc UBFM	X13, X12, #3, #63

(206) 0x4298d0 ADD	X14, X13, X8

(206) 0x4298d4 ANDS	X15, X14, #4224

(206) 0x4298d8 B.EQ	429968

(206) 0x4298dc CMP	X15, X8

(206) 0x4298e0 B.EQ	429954

(206) 0x4298e4 CMP	X15, #2

(206) 0x4298e8 B.EQ	429948

(206) 0x4298ec CMP	X15, #3

(206) 0x4298f0 B.EQ	42993c

(206) 0x4298f4 CMP	X15, #4

(206) 0x4298f8 B.EQ	429930

(206) 0x4298fc CMP	X15, #5

(206) 0x429900 B.EQ	429924

(206) 0x429904 CMP	X15, #6

(206) 0x429908 B.EQ	429918

(206) 0x42990c LDR	X16, [X0], #8

(206) 0x429910 ADD	X17, X9, X16,LSL #3

(206) 0x429914 LDADD	X8, X1, [X17]

(206) 0x429918 LDR	X18, [X0], #8

(206) 0x42991c ADD	X30, X9, X18,LSL #3

(206) 0x429920 LDADD	X8, X1, [X30]

(206) 0x429924 LDR	X20, [X0], #8

(206) 0x429928 ADD	X1, X9, X20,LSL #3

(206) 0x42992c LDADD	X8, X1, [X1]

(206) 0x429930 LDR	X21, [X0], #8

(206) 0x429934 ADD	X19, X9, X21,LSL #3

(206) 0x429938 LDADD	X8, X1, [X19]

(206) 0x42993c LDR	X4, [X0], #8

(206) 0x429940 ADD	X3, X9, X4,LSL #3

(206) 0x429944 LDADD	X8, X1, [X3]

(206) 0x429948 LDR	X2, [X0], #8

(206) 0x42994c ADD	X6, X9, X2,LSL #3

(206) 0x429950 LDADD	X8, X1, [X6]

(206) 0x429954 LDR	X7, [X0], #8

(206) 0x429958 ADD	X5, X9, X7,LSL #3

(206) 0x42995c LDADD	X8, X1, [X5]

(206) 0x429960 CMP	X10, X0

(206) 0x429964 B.EQ	4299d8

  (207) 0x429968 ORR	X11, XZR, X0

  (207) 0x42996c LDR	X12, [X11], #8

  (207) 0x429970 ADD	X13, X9, X12,LSL #3

  (207) 0x429974 LDADD	X8, X1, [X13]

  (207) 0x429978 LDR	X14, [X0, #8]

  (207) 0x42997c ADD	X15, X9, X14,LSL #3

  (207) 0x429980 LDADD	X8, X1, [X15]

  (207) 0x429984 LDR	X16, [X11, #8]

  (207) 0x429988 ADD	X17, X9, X16,LSL #3

  (207) 0x42998c LDADD	X8, X1, [X17]

  (207) 0x429990 LDR	X18, [X0, #24]

  (207) 0x429994 ADD	X30, X9, X18,LSL #3

  (207) 0x429998 LDADD	X8, X1, [X30]

  (207) 0x42999c LDR	X20, [X0, #32]

  (207) 0x4299a0 ADD	X1, X9, X20,LSL #3

  (207) 0x4299a4 LDADD	X8, X1, [X1]

  (207) 0x4299a8 LDR	X21, [X0, #40]

  (207) 0x4299ac ADD	X19, X9, X21,LSL #3

  (207) 0x4299b0 LDADD	X8, X1, [X19]

  (207) 0x4299b4 LDR	X4, [X0, #48]

  (207) 0x4299b8 ADD	X3, X9, X4,LSL #3

  (207) 0x4299bc LDADD	X8, X1, [X3]

  (207) 0x4299c0 LDR	X2, [X0, #56]

  (207) 0x4299c4 ADD	X6, X9, X2,LSL #3

  (207) 0x4299c8 LDADD	X8, X1, [X6]

  (207) 0x4299cc ADD	X0, X0, #64

  (207) 0x4299d0 CMP	X10, X0

  (207) 0x4299d4 B.NE	429968

(206) 0x4299d8 LDR	X21, [SP, #32]

(206) 0x4299dc LDP	X19, X20, [SP, #16]

(206) 0x4299e0 LDP	X29, X30, [SP], #48

(206) 0x4299e4 RET

(206) 0x4299e8 ADD	X3, X3, #1

(206) 0x4299ec MOVZ	X2, #0

(206) 0x4299f0 B	4298a0

0x4299f4 HINT	#0

0x4299f8 HINT	#0

0x4299fc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.17+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_coarsen.c:2132-2136
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2132-2136.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 71% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	2.00
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X4, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4299e8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	par_coarsen.c:2132-2136
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2132-2136.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	1.67	1.50	1.67	1.67	2.00	1.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	2.00
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 429860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 410d60 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
BL 410c90 <@plt_start@+0x4d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X4, X0, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SDIV X3, X21, X19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
MSUB X2, X3, X19, X21	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP X4, X2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4299e8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.2–	0.71	0.11
▼Loop 206 - par_coarsen.c:2132-2136 - exec–	0.00	0.00
○Loop 207 - par_coarsen.c:2135-2136 - exec	0.71	0.09

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code