OV - exec - Loop 766

	Loop Id: 766	Module: exec	Source: par_multi_interp.c:1811-1837	Coverage: 0.58%

0x4370f4 LDR	D3, [X24, X13,LSL #3]

0x4370f8 FADD	D1, D1, D3

0x4370fc HINT	#0

0x437100 ADD	X13, X13, #1

0x437104 CMP	X13, X12

0x437108 B.EQ	4372e4

0x43710c LDUR	X15, [X29, #496]

0x437110 LDR	X2, [X15, X13,LSL #3]

0x437114 LDR	X15, [X19, X2,LSL #3]

0x437118 CMP	X15, X11

0x43711c B.NE	43714c

0x437120 ADD	X0, X2, #1

0x437124 LDR	X26, [X14, X2,LSL #3]

0x437128 LDR	X3, [X14, X0,LSL #3]

0x43712c CMP	X3, X26

0x437130 B.LE	437218

0x437134 SUB	W18, W3, W26

0x437138 ADD	X15, X26, #1

0x43713c TBNZ	W18, #0, 437174

0x437140 CMP	X3, X15

0x437144 B.NE	4371a8

0x437148 B	437218

0x43714c LDR	X15, [X16, X2,LSL #3]

0x437150 CMN	X15, #3

0x437154 B.EQ	437100

0x437158 CMP	X1, #1

0x43715c B.EQ	4370f4

0x437160 LDR	X15, [X9, X11,LSL #3]

0x437164 LDR	X18, [X9, X2,LSL #3]

0x437168 CMP	X15, X18

0x43716c B.EQ	4370f4

0x437170 B	437100

0x437174 LDR	X18, [X4, X26,LSL #3]

0x437178 LDR	D0, [X24, X13,LSL #3]

0x43717c LDR	D3, [X23, X26,LSL #3]

0x437180 ORR	X26, XZR, X15

0x437184 FMUL	D0, D0, D3

0x437188 LDR	X18, [X21, X18,LSL #3]

0x43718c LDR	D3, [X23, X18,LSL #3]

0x437190 FADD	D2, D2, D0

0x437194 FADD	D1, D1, D0

0x437198 FADD	D3, D0, D3

0x43719c STR	D3, [X23, X18,LSL #3]

0x4371a0 CMP	X3, X15

0x4371a4 B.EQ	437218

0x4371a8 SUB	X3, X3, X26

0x4371ac ADD	X5, X6, X26,LSL #3

0x4371b0 ADD	X26, X7, X26,LSL #3

0x4371b4 HINT	#0

0x4371b8 HINT	#0

0x4371bc HINT	#0

  (768) 0x4371c0 LDP	X15, X18, [X5, #1016]

  (768) 0x4371c4 LDR	D0, [X24, X13,LSL #3]

  (768) 0x4371c8 LDUR	D3, [X26, #504]

  (768) 0x4371cc SUBS	X3, X3, #2

  (768) 0x4371d0 ADD	X5, X5, #16

  (768) 0x4371d4 FMUL	D0, D0, D3

  (768) 0x4371d8 LDR	X15, [X21, X15,LSL #3]

  (768) 0x4371dc LDR	D3, [X23, X15,LSL #3]

  (768) 0x4371e0 FADD	D2, D2, D0

  (768) 0x4371e4 FADD	D1, D1, D0

  (768) 0x4371e8 FADD	D3, D0, D3

  (768) 0x4371ec STR	D3, [X23, X15,LSL #3]

  (768) 0x4371f0 LDR	X15, [X21, X18,LSL #3]

  (768) 0x4371f4 LDR	D0, [X24, X13,LSL #3]

  (768) 0x4371f8 LDR	D3, [X26], #16

  (768) 0x4371fc FMUL	D0, D0, D3

  (768) 0x437200 LDR	D3, [X23, X15,LSL #3]

  (768) 0x437204 FADD	D2, D2, D0

  (768) 0x437208 FADD	D1, D1, D0

  (768) 0x43720c FADD	D3, D0, D3

  (768) 0x437210 STR	D3, [X23, X15,LSL #3]

  (768) 0x437214 B.NE	4371c0

0x437218 LDR	X3, [X17, X2,LSL #3]

0x43721c LDR	X0, [X17, X0,LSL #3]

0x437220 CMP	X0, X3

0x437224 B.LE	437100

0x437228 SUB	W18, W0, W3

0x43722c ADD	X15, X3, #1

0x437230 TBNZ	W18, #0, 437240

0x437234 CMP	X0, X15

0x437238 B.EQ	437100

0x43723c B	437274

0x437240 LDR	X18, [X27, X3,LSL #3]

0x437244 LDR	D0, [X24, X13,LSL #3]

0x437248 LDR	D3, [X10, X3,LSL #3]

0x43724c ORR	X3, XZR, X15

0x437250 FMUL	D0, D0, D3

0x437254 LDR	X18, [X22, X18,LSL #3]

0x437258 LDR	D3, [X10, X18,LSL #3]

0x43725c FADD	D2, D2, D0

0x437260 FADD	D1, D1, D0

0x437264 FADD	D3, D0, D3

0x437268 STR	D3, [X10, X18,LSL #3]

0x43726c CMP	X0, X15

0x437270 B.EQ	437100

0x437274 SUB	X0, X0, X3

0x437278 ADD	X2, X20, X3,LSL #3

0x43727c ADD	X3, X25, X3,LSL #3

  (767) 0x437280 LDP	X15, X18, [X2, #1016]

  (767) 0x437284 LDR	D0, [X24, X13,LSL #3]

  (767) 0x437288 LDUR	D3, [X3, #504]

  (767) 0x43728c SUBS	X0, X0, #2

  (767) 0x437290 ADD	X2, X2, #16

  (767) 0x437294 FMUL	D0, D0, D3

  (767) 0x437298 LDR	X15, [X22, X15,LSL #3]

  (767) 0x43729c LDR	D3, [X10, X15,LSL #3]

  (767) 0x4372a0 FADD	D2, D2, D0

  (767) 0x4372a4 FADD	D1, D1, D0

  (767) 0x4372a8 FADD	D3, D0, D3

  (767) 0x4372ac STR	D3, [X10, X15,LSL #3]

  (767) 0x4372b0 LDR	X15, [X22, X18,LSL #3]

  (767) 0x4372b4 LDR	D0, [X24, X13,LSL #3]

  (767) 0x4372b8 LDR	D3, [X3], #16

  (767) 0x4372bc FMUL	D0, D0, D3

  (767) 0x4372c0 LDR	D3, [X10, X15,LSL #3]

  (767) 0x4372c4 FADD	D2, D2, D0

  (767) 0x4372c8 FADD	D1, D1, D0

  (767) 0x4372cc FADD	D3, D0, D3

  (767) 0x4372d0 STR	D3, [X10, X15,LSL #3]

  (767) 0x4372d4 B.NE	437280

0x4372d8 B	437100

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1811 - 1837

--------------------------------------------------------------------------------

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.52
CQA speedup if FP arith vectorized	1.58
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.20
Source	par_multi_interp.c:1811-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	5.87
CQA cycles if fully vectorized	4.63
Front-end cycles	9.25
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.17
P5 cycles	4.17
P6 cycles	4.08
P7 cycles	4.08
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	2.75
P11 cycles	2.75
P12 cycles	7.67
P13 cycles	7.67
P14 cycles	7.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	74.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.97
Nb FLOP add-sub	7.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.89
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.52
CQA speedup if FP arith vectorized	1.58
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.20
Source	par_multi_interp.c:1811-1830,par_multi_interp.c:1835-1837
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.25
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	5.87
CQA cycles if fully vectorized	4.63
Front-end cycles	9.25
P0 cycles	8.50
P1 cycles	8.50
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.17
P5 cycles	4.17
P6 cycles	4.08
P7 cycles	4.08
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	2.75
P11 cycles	2.75
P12 cycles	7.67
P13 cycles	7.67
P14 cycles	7.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	78.00
Nb uops	74.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.97
Nb FLOP add-sub	7.00
Nb FLOP mul	2.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.89
Bytes prefetched	0.00
Bytes loaded	168.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.20
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811-1837.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1811-1830,1835-1837.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=29
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 29 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 3.67 cycles (2.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.25 to 4.62 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

7: addition or subtraction
2: multiply

The binary loop is loading 168 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	78
loop length	312
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.50	8.50	4.25	4.25	4.17	4.17	4.08	4.08	2.75	2.75	2.75	2.75	7.67	7.67	7.67	0.00	0.00
cycles	8.50	8.50	4.25	4.25	4.17	4.17	4.08	4.08	2.75	2.75	2.75	2.75	7.67	7.67	7.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.25
Overall L1	9.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

18% of peak load performance is reached (18.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43710c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR D3, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D1, D1, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
HINT #0																					N/A
ADD X13, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4372e4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X15, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X15, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 43714c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X26, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 437218 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W18, W3, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W18, #0, 437174 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4371a8 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 437218 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X15, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4370f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4370f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D3, [X23, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ORR X26, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D0, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X18, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D2, D2, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D1, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D3, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D3, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X3, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 437218 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X3, X3, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X6, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X7, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X3, [X17, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W18, W0, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W18, #0, 437240 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 437274 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x744>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D3, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ORR X3, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D0, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X18, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D2, D2, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D1, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D3, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D3, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X0, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X0, X0, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X20, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X25, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.20
Source file and lines	par_multi_interp.c:1811-1837
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=29
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.25 to 3.67 cycles (2.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.25 to 4.62 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 9 FP arithmetical operations:

7: addition or subtraction
2: multiply

The binary loop is loading 168 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	78
loop length	312
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.50	8.50	4.25	4.25	4.17	4.17	4.08	4.08	2.75	2.75	2.75	2.75	7.67	7.67	7.67	0.00	0.00
cycles	8.50	8.50	4.25	4.25	4.17	4.17	4.08	4.08	2.75	2.75	2.75	2.75	7.67	7.67	7.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.25
Overall L1	9.25

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.25 cycles. At this rate:

18% of peak load performance is reached (18.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43710c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR D3, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D1, D1, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
HINT #0																					N/A
ADD X13, X13, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4372e4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X15, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X15, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X19, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 43714c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X0, X2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X26, [X14, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X3, X26	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 437218 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W18, W3, W26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W18, #0, 437174 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4371a8 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 437218 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X15, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4370f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X15, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X15, X18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4370f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D3, [X23, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ORR X26, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D0, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X18, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D2, D2, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D1, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D3, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D3, [X23, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X3, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 437218 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X3, X3, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X6, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X7, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X3, [X17, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W18, W0, W3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W18, #0, 437240 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 437274 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x744>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X18, [X27, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D3, [X10, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ORR X3, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMUL D0, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X18, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FADD D2, D2, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D1, D1, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D3, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D3, [X10, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X0, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X0, X0, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X20, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X25, X3,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 437100 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code