OV - exec - Loop 762

	Loop Id: 762	Module: exec	Source: par_multi_interp.c:1774-1876 [...]	Coverage: 0.19%

0x436e4c LDUR	X9, [X29, #456]

0x436e50 LDUR	X8, [X29, #376]

0x436e54 ADD	X9, X9, #1

0x436e58 CMP	X9, X8

0x436e5c B.GE	437578

0x436e60 LDP	X8, X10, [X29, #928]

0x436e64 STUR	X9, [X29, #456]

0x436e68 LDR	X11, [X10, X9,LSL #3]

0x436e6c LDR	X9, [X8, X11,LSL #3]

0x436e70 ADD	X8, X11, #1

0x436e74 LDR	X12, [X14, X11,LSL #3]

0x436e78 LDR	X13, [X14, X8,LSL #3]

0x436e7c ADD	X10, X13, X9

0x436e80 SUB	X10, X10, X12

0x436e84 CMP	X9, X10

0x436e88 B.GE	436f28

0x436e8c SUB	W16, W13, W12

0x436e90 ADD	X15, X12, #1

0x436e94 TBZ	W16, #0, 436ec0

0x436e98 LDR	X16, [X28]

0x436e9c LDR	X18, [SP, #176]

0x436ea0 LDR	X16, [X0, X16,LSL #3]

0x436ea4 STR	XZR, [X18, X12,LSL #3]

0x436ea8 LDR	X18, [SP, #56]

0x436eac LDR	X16, [X16, X9,LSL #3]

0x436eb0 ADD	X9, X9, #1

0x436eb4 STR	X12, [X21, X16,LSL #3]

0x436eb8 STR	X16, [X18, X12,LSL #3]

0x436ebc ORR	X12, XZR, X15

0x436ec0 CMP	X13, X15

0x436ec4 B.EQ	436f28

0x436ec8 LDP	X15, X13, [SP, #32]

0x436ecc ADD	X13, X13, X12,LSL #3

0x436ed0 ADD	X16, X15, X12,LSL #3

0x436ed4 HINT	#0

0x436ed8 HINT	#0

0x436edc HINT	#0

  (772) 0x436ee0 LDR	X15, [X28]

  (772) 0x436ee4 ADD	X18, X12, #1

  (772) 0x436ee8 LDR	X15, [X0, X15,LSL #3]

  (772) 0x436eec LDR	X15, [X15, X9,LSL #3]

  (772) 0x436ef0 STR	X12, [X21, X15,LSL #3]

  (772) 0x436ef4 STP	XZR, XZR, [X13, #1016]

  (772) 0x436ef8 STUR	X15, [X16, #504]

  (772) 0x436efc ADD	X13, X13, #16

  (772) 0x436f00 ADD	X12, X12, #2

  (772) 0x436f04 LDR	X15, [X28]

  (772) 0x436f08 LDR	X15, [X0, X15,LSL #3]

  (772) 0x436f0c ADD	X15, X15, X9,LSL #3

  (772) 0x436f10 ADD	X9, X9, #2

  (772) 0x436f14 LDR	X15, [X15, #8]

  (772) 0x436f18 STR	X18, [X21, X15,LSL #3]

  (772) 0x436f1c STR	X15, [X16], #16

  (772) 0x436f20 CMP	X10, X9

  (772) 0x436f24 B.NE	436ee0

0x436f28 LDUR	X9, [X29, #400]

0x436f2c LDR	X13, [X17, X8,LSL #3]

0x436f30 LDR	X12, [X17, X11,LSL #3]

0x436f34 LDR	X9, [X9, X11,LSL #3]

0x436f38 ADD	X10, X13, X9

0x436f3c SUB	X10, X10, X12

0x436f40 CMP	X9, X10

0x436f44 B.GE	436fe8

0x436f48 SUB	W16, W13, W12

0x436f4c ADD	X15, X12, #1

0x436f50 TBZ	W16, #0, 436f7c

0x436f54 LDR	X16, [X28]

0x436f58 LDR	X18, [SP, #168]

0x436f5c LDR	X16, [X1, X16,LSL #3]

0x436f60 STR	XZR, [X18, X12,LSL #3]

0x436f64 LDR	X18, [SP, #48]

0x436f68 LDR	X16, [X16, X9,LSL #3]

0x436f6c ADD	X9, X9, #1

0x436f70 STR	X12, [X22, X16,LSL #3]

0x436f74 STR	X16, [X18, X12,LSL #3]

0x436f78 ORR	X12, XZR, X15

0x436f7c CMP	X13, X15

0x436f80 B.EQ	436fe8

0x436f84 LDP	X15, X13, [SP, #16]

0x436f88 ADD	X13, X13, X12,LSL #3

0x436f8c ADD	X16, X15, X12,LSL #3

0x436f90 HINT	#0

0x436f94 HINT	#0

0x436f98 HINT	#0

0x436f9c HINT	#0

  (771) 0x436fa0 LDR	X15, [X28]

  (771) 0x436fa4 ADD	X18, X12, #1

  (771) 0x436fa8 LDR	X15, [X1, X15,LSL #3]

  (771) 0x436fac LDR	X15, [X15, X9,LSL #3]

  (771) 0x436fb0 STR	X12, [X22, X15,LSL #3]

  (771) 0x436fb4 STP	XZR, XZR, [X13, #1016]

  (771) 0x436fb8 STUR	X15, [X16, #504]

  (771) 0x436fbc ADD	X13, X13, #16

  (771) 0x436fc0 ADD	X12, X12, #2

  (771) 0x436fc4 LDR	X15, [X28]

  (771) 0x436fc8 LDR	X15, [X1, X15,LSL #3]

  (771) 0x436fcc ADD	X15, X15, X9,LSL #3

  (771) 0x436fd0 ADD	X9, X9, #2

  (771) 0x436fd4 LDR	X15, [X15, #8]

  (771) 0x436fd8 STR	X18, [X22, X15,LSL #3]

  (771) 0x436fdc STR	X15, [X16], #16

  (771) 0x436fe0 CMP	X10, X9

  (771) 0x436fe4 B.NE	436fa0

0x436fe8 LDR	X9, [X2, X11,LSL #3]

0x436fec LDR	X10, [X2, X8,LSL #3]

0x436ff0 LDUR	X16, [X29, #480]

0x436ff4 CMP	X9, X10

0x436ff8 B.LT	43704c

0x436ffc LDR	X9, [X5, X11,LSL #3]

0x437000 LDR	X10, [X5, X8,LSL #3]

0x437004 B	43700c

  (769) 0x437008 ADD	X9, X9, #1

  (769) 0x43700c CMP	X9, X10

  (769) 0x437010 B.GE	437080

  (769) 0x437014 LDR	X12, [X6, X9,LSL #3]

  (769) 0x437018 LDR	X15, [X28]

  (769) 0x43701c LDR	X13, [X7, X12,LSL #3]

  (769) 0x437020 SUB	X15, X15, #1

  (769) 0x437024 CMP	X13, X15

  (769) 0x437028 B.NE	437008

  (769) 0x43702c STR	X11, [X16, X12,LSL #3]

  (769) 0x437030 LDR	X10, [X5, X8,LSL #3]

  (769) 0x437034 B	437008

  (770) 0x437040 ADD	X9, X9, #1

  (770) 0x437044 CMP	X9, X10

  (770) 0x437048 B.GE	436ffc

  (770) 0x43704c LDR	X12, [X3, X9,LSL #3]

  (770) 0x437050 LDR	X15, [X28]

  (770) 0x437054 LDR	X13, [X4, X12,LSL #3]

  (770) 0x437058 SUB	X15, X15, #1

  (770) 0x43705c CMP	X13, X15

  (770) 0x437060 B.NE	437040

  (770) 0x437064 STR	X11, [X19, X12,LSL #3]

  (770) 0x437068 LDR	X10, [X2, X8,LSL #3]

  (770) 0x43706c B	437040

0x437080 LDUR	X9, [X29, #328]

0x437084 MOVI	D2, #0

0x437088 LDR	X10, [X9, X11,LSL #3]

0x43708c LDR	X12, [X9, X8,LSL #3]

0x437090 ADD	X13, X10, #1

0x437094 STUR	X10, [X29, #448]

0x437098 CMP	X13, X12

0x43709c B.GE	4372e0

0x4370a0 LDR	X9, [SP, #64]

0x4370a4 MOVI	D1, #0

0x4370a8 LDR	X16, [X9]

0x4370ac LDP	X10, X9, [X29, #944]

0x4370b0 LDR	X1, [X10]

0x4370b4 LDR	X10, [SP, #160]

0x4370b8 LDR	X9, [X9]

0x4370bc LDR	X24, [X10]

0x4370c0 LDR	X10, [SP, #144]

0x4370c4 LDR	X4, [X10]

0x4370c8 LDUR	X10, [X29, #464]

0x4370cc LDR	X23, [X10]

0x4370d0 LDR	X10, [SP, #152]

0x4370d4 ADD	X6, X4, #8

0x4370d8 LDR	X27, [X10]

0x4370dc LDUR	X10, [X29, #472]

0x4370e0 ADD	X7, X23, #8

0x4370e4 LDR	X10, [X10]

0x4370e8 ADD	X20, X27, #8

0x4370ec ADD	X25, X10, #8

0x4370f0 B	43710c

  (766) 0x4370f4 LDR	D3, [X24, X13,LSL #3]

  (766) 0x4370f8 FADD	D1, D1, D3

  (766) 0x4370fc HINT	#0

  (766) 0x437100 ADD	X13, X13, #1

  (766) 0x437104 CMP	X13, X12

  (766) 0x437108 B.EQ	4372e4

  (766) 0x43710c LDUR	X15, [X29, #496]

  (766) 0x437110 LDR	X2, [X15, X13,LSL #3]

  (766) 0x437114 LDR	X15, [X19, X2,LSL #3]

  (766) 0x437118 CMP	X15, X11

  (766) 0x43711c B.NE	43714c

  (766) 0x437120 ADD	X0, X2, #1

  (766) 0x437124 LDR	X26, [X14, X2,LSL #3]

  (766) 0x437128 LDR	X3, [X14, X0,LSL #3]

  (766) 0x43712c CMP	X3, X26

  (766) 0x437130 B.LE	437218

  (766) 0x437134 SUB	W18, W3, W26

  (766) 0x437138 ADD	X15, X26, #1

  (766) 0x43713c TBNZ	W18, #0, 437174

  (766) 0x437140 CMP	X3, X15

  (766) 0x437144 B.NE	4371a8

  (766) 0x437148 B	437218

  (766) 0x43714c LDR	X15, [X16, X2,LSL #3]

  (766) 0x437150 CMN	X15, #3

  (766) 0x437154 B.EQ	437100

  (766) 0x437158 CMP	X1, #1

  (766) 0x43715c B.EQ	4370f4

  (766) 0x437160 LDR	X15, [X9, X11,LSL #3]

  (766) 0x437164 LDR	X18, [X9, X2,LSL #3]

  (766) 0x437168 CMP	X15, X18

  (766) 0x43716c B.EQ	4370f4

  (766) 0x437170 B	437100

  (766) 0x437174 LDR	X18, [X4, X26,LSL #3]

  (766) 0x437178 LDR	D0, [X24, X13,LSL #3]

  (766) 0x43717c LDR	D3, [X23, X26,LSL #3]

  (766) 0x437180 ORR	X26, XZR, X15

  (766) 0x437184 FMUL	D0, D0, D3

  (766) 0x437188 LDR	X18, [X21, X18,LSL #3]

  (766) 0x43718c LDR	D3, [X23, X18,LSL #3]

  (766) 0x437190 FADD	D2, D2, D0

  (766) 0x437194 FADD	D1, D1, D0

  (766) 0x437198 FADD	D3, D0, D3

  (766) 0x43719c STR	D3, [X23, X18,LSL #3]

  (766) 0x4371a0 CMP	X3, X15

  (766) 0x4371a4 B.EQ	437218

  (766) 0x4371a8 SUB	X3, X3, X26

  (766) 0x4371ac ADD	X5, X6, X26,LSL #3

  (766) 0x4371b0 ADD	X26, X7, X26,LSL #3

  (766) 0x4371b4 HINT	#0

  (766) 0x4371b8 HINT	#0

  (766) 0x4371bc HINT	#0

    (768) 0x4371c0 LDP	X15, X18, [X5, #1016]

    (768) 0x4371c4 LDR	D0, [X24, X13,LSL #3]

    (768) 0x4371c8 LDUR	D3, [X26, #504]

    (768) 0x4371cc SUBS	X3, X3, #2

    (768) 0x4371d0 ADD	X5, X5, #16

    (768) 0x4371d4 FMUL	D0, D0, D3

    (768) 0x4371d8 LDR	X15, [X21, X15,LSL #3]

    (768) 0x4371dc LDR	D3, [X23, X15,LSL #3]

    (768) 0x4371e0 FADD	D2, D2, D0

    (768) 0x4371e4 FADD	D1, D1, D0

    (768) 0x4371e8 FADD	D3, D0, D3

    (768) 0x4371ec STR	D3, [X23, X15,LSL #3]

    (768) 0x4371f0 LDR	X15, [X21, X18,LSL #3]

    (768) 0x4371f4 LDR	D0, [X24, X13,LSL #3]

    (768) 0x4371f8 LDR	D3, [X26], #16

    (768) 0x4371fc FMUL	D0, D0, D3

    (768) 0x437200 LDR	D3, [X23, X15,LSL #3]

    (768) 0x437204 FADD	D2, D2, D0

    (768) 0x437208 FADD	D1, D1, D0

    (768) 0x43720c FADD	D3, D0, D3

    (768) 0x437210 STR	D3, [X23, X15,LSL #3]

    (768) 0x437214 B.NE	4371c0

  (766) 0x437218 LDR	X3, [X17, X2,LSL #3]

  (766) 0x43721c LDR	X0, [X17, X0,LSL #3]

  (766) 0x437220 CMP	X0, X3

  (766) 0x437224 B.LE	437100

  (766) 0x437228 SUB	W18, W0, W3

  (766) 0x43722c ADD	X15, X3, #1

  (766) 0x437230 TBNZ	W18, #0, 437240

  (766) 0x437234 CMP	X0, X15

  (766) 0x437238 B.EQ	437100

  (766) 0x43723c B	437274

  (766) 0x437240 LDR	X18, [X27, X3,LSL #3]

  (766) 0x437244 LDR	D0, [X24, X13,LSL #3]

  (766) 0x437248 LDR	D3, [X10, X3,LSL #3]

  (766) 0x43724c ORR	X3, XZR, X15

  (766) 0x437250 FMUL	D0, D0, D3

  (766) 0x437254 LDR	X18, [X22, X18,LSL #3]

  (766) 0x437258 LDR	D3, [X10, X18,LSL #3]

  (766) 0x43725c FADD	D2, D2, D0

  (766) 0x437260 FADD	D1, D1, D0

  (766) 0x437264 FADD	D3, D0, D3

  (766) 0x437268 STR	D3, [X10, X18,LSL #3]

  (766) 0x43726c CMP	X0, X15

  (766) 0x437270 B.EQ	437100

  (766) 0x437274 SUB	X0, X0, X3

  (766) 0x437278 ADD	X2, X20, X3,LSL #3

  (766) 0x43727c ADD	X3, X25, X3,LSL #3

    (767) 0x437280 LDP	X15, X18, [X2, #1016]

    (767) 0x437284 LDR	D0, [X24, X13,LSL #3]

    (767) 0x437288 LDUR	D3, [X3, #504]

    (767) 0x43728c SUBS	X0, X0, #2

    (767) 0x437290 ADD	X2, X2, #16

    (767) 0x437294 FMUL	D0, D0, D3

    (767) 0x437298 LDR	X15, [X22, X15,LSL #3]

    (767) 0x43729c LDR	D3, [X10, X15,LSL #3]

    (767) 0x4372a0 FADD	D2, D2, D0

    (767) 0x4372a4 FADD	D1, D1, D0

    (767) 0x4372a8 FADD	D3, D0, D3

    (767) 0x4372ac STR	D3, [X10, X15,LSL #3]

    (767) 0x4372b0 LDR	X15, [X22, X18,LSL #3]

    (767) 0x4372b4 LDR	D0, [X24, X13,LSL #3]

    (767) 0x4372b8 LDR	D3, [X3], #16

    (767) 0x4372bc FMUL	D0, D0, D3

    (767) 0x4372c0 LDR	D3, [X10, X15,LSL #3]

    (767) 0x4372c4 FADD	D2, D2, D0

    (767) 0x4372c8 FADD	D1, D1, D0

    (767) 0x4372cc FADD	D3, D0, D3

    (767) 0x4372d0 STR	D3, [X10, X15,LSL #3]

    (767) 0x4372d4 B.NE	437280

  (766) 0x4372d8 B	437100

0x4372e0 MOVI	D1, #0

0x4372e4 LDR	X10, [SP, #192]

0x4372e8 LDR	X9, [X10, X11,LSL #3]

0x4372ec LDR	X10, [X10, X8,LSL #3]

0x4372f0 CMP	X9, X10

0x4372f4 B.GE	437448

0x437448 LDR	X9, [SP, #184]

0x43744c LDUR	X10, [X29, #448]

0x437450 LDR	D3, [X9, X10,LSL #3]

0x437454 FMUL	D2, D2, D3

0x437458 FCMP	D2, #0

0x43745c B.EQ	437468

0x437460 FNEG	D0, D1

0x437464 FDIV	D0, D0, D2

0x437468 LDR	X15, [X14, X11,LSL #3]

0x43746c LDR	X9, [X14, X8,LSL #3]

0x437470 LDUR	X0, [X29, #408]

0x437474 SUBS	X10, X9, X15

0x437478 LDP	X2, X1, [X29, #896]

0x43747c LDP	X4, X3, [X29, #872]

0x437480 LDP	X6, X5, [X29, #856]

0x437484 LDUR	X7, [X29, #336]

0x437488 B.LE	4374f4

0x43748c ORR	X12, XZR, X15

0x437490 CMP	X10, #4

0x437494 B.CC	4374d0

0x437498 LDR	X16, [SP, #8]

0x43749c AND	X13, X10, #8062

0x4374a0 ADD	X12, X15, X13

0x4374a4 ADD	X15, X16, X15,LSL #3

0x4374a8 ORR	X16, XZR, X13

  (776) 0x4374ac LDP	Q1, Q2, [X15, #2032]

  (776) 0x4374b0 SUBS	X16, X16, #4

  (776) 0x4374b4 FMUL	V2.2D, V2.2D, V0.D[0]

  (776) 0x4374b8 FMUL	V1.2D, V1.2D, V0.D[0]

  (776) 0x4374bc STP	Q1, Q2, [X15, #2032]

  (776) 0x4374c0 ADD	X15, X15, #32

  (776) 0x4374c4 B.NE	4374ac

0x4374c8 CMP	X10, X13

0x4374cc B.EQ	4374f4

0x4374d0 LDR	X10, [SP, #176]

0x4374d4 SUB	X9, X9, X12

0x4374d8 ADD	X10, X10, X12,LSL #3

0x4374dc HINT	#0

  (775) 0x4374e0 LDR	D1, [X10]

  (775) 0x4374e4 SUBS	X9, X9, #1

  (775) 0x4374e8 FMUL	D1, D0, D1

  (775) 0x4374ec STR	D1, [X10], #8

  (775) 0x4374f0 B.NE	4374e0

0x4374f4 LDR	X12, [X17, X11,LSL #3]

0x4374f8 LDR	X8, [X17, X8,LSL #3]

0x4374fc SUBS	X9, X8, X12

0x437500 B.LE	436e4c

0x437504 ORR	X10, XZR, X12

0x437508 CMP	X9, #4

0x43750c B.CC	437548

0x437510 LDR	X13, [SP]

0x437514 AND	X11, X9, #8062

0x437518 ADD	X10, X12, X11

0x43751c ADD	X12, X13, X12,LSL #3

0x437520 ORR	X13, XZR, X11

  (774) 0x437524 LDP	Q1, Q2, [X12, #2032]

  (774) 0x437528 SUBS	X13, X13, #4

  (774) 0x43752c FMUL	V2.2D, V2.2D, V0.D[0]

  (774) 0x437530 FMUL	V1.2D, V1.2D, V0.D[0]

  (774) 0x437534 STP	Q1, Q2, [X12, #2032]

  (774) 0x437538 ADD	X12, X12, #32

  (774) 0x43753c B.NE	437524

0x437540 CMP	X9, X11

0x437544 B.EQ	436e4c

0x437548 LDR	X9, [SP, #168]

0x43754c SUB	X8, X8, X10

0x437550 ADD	X9, X9, X10,LSL #3

0x437554 HINT	#0

0x437558 HINT	#0

0x43755c HINT	#0

  (773) 0x437560 LDR	D1, [X9]

  (773) 0x437564 SUBS	X8, X8, #1

  (773) 0x437568 FMUL	D1, D0, D1

  (773) 0x43756c STR	D1, [X9], #8

  (773) 0x437570 B.NE	437560

0x437574 B	436e4c

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1774 - 1876

--------------------------------------------------------------------------------

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

[...]

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.52
CQA speedup if FP arith vectorized	1.60
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.20
Source	par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1870-1875
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.33
CQA cycles if no scalar integer	9.67
CQA cycles if FP arith vectorized	15.17
CQA cycles if fully vectorized	21.33
Front-end cycles	18.88
P0 cycles	10.00
P1 cycles	10.00
P2 cycles	8.50
P3 cycles	8.50
P4 cycles	8.50
P5 cycles	8.50
P6 cycles	8.50
P7 cycles	8.50
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	1.75
P11 cycles	1.75
P12 cycles	24.33
P13 cycles	24.33
P14 cycles	24.33
P15 cycles	4.00
P16 cycles	4.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	151.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.08
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.30
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	52.88
Vector-efficiency ratio load	61.54
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.52
CQA speedup if FP arith vectorized	1.60
CQA speedup if fully vectorized	1.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	P12, P13, P14,
Function	hypre_BoomerAMGBuildMultipass.omp_outlined.20
Source	par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1870-1875
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	24.33
CQA cycles if no scalar integer	9.67
CQA cycles if FP arith vectorized	15.17
CQA cycles if fully vectorized	21.33
Front-end cycles	18.88
P0 cycles	10.00
P1 cycles	10.00
P2 cycles	8.50
P3 cycles	8.50
P4 cycles	8.50
P5 cycles	8.50
P6 cycles	8.50
P7 cycles	8.50
P8 cycles	1.75
P9 cycles	1.75
P10 cycles	1.75
P11 cycles	1.75
P12 cycles	24.33
P13 cycles	24.33
P14 cycles	24.33
P15 cycles	4.00
P16 cycles	4.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	162.00
Nb uops	151.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.08
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.30
Bytes prefetched	0.00
Bytes loaded	576.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	52.88
Vector-efficiency ratio load	61.54
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	50.00
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.20
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1840,1865-1876.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1776,1779-1799,1805,1811,1824,1840,1865,1870-1875.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.33 to 9.67 cycles (2.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 52% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 24.33 to 21.33 cycles (1.14x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 576 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	162
loop length	648
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.00	10.00	8.50	8.50	8.50	8.50	8.50	8.50	1.75	1.75	1.75	1.75	24.33	24.33	24.33	4.00	4.00
cycles	10.00	10.00	8.50	8.50	8.50	8.50	8.50	8.50	1.75	1.75	1.75	1.75	24.33	24.33	24.33	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	18.88
Overall L1	24.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.33 cycles. At this rate:

24% of peak load performance is reached (23.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.63 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 437448

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 437578 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X13, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 436f28 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W13, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
TBZ W16, #0, 436ec0 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [X21, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X12, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 436f28 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X13, X13, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X15, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDUR X9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X13, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 436fe8 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W13, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
TBZ W16, #0, 436f7c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X12, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 436fe8 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X13, X13, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X15, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X9, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X2, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X16, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43704c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X5, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 43700c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X10, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4372e0 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X4, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X27, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X23, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X27, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X25, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 43710c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 437448 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMP D2, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 437468 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D0, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D0, D0, D2	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR X15, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X10, X9, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDP X2, X1, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X3, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X5, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X7, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.LE 4374f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x9c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X12, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 4374d0 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x9a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X13, X10, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X15, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X16, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X16, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4374f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x9c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X9, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X12, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X9, X8, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 436e4c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 437548 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0xa18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X11, X9, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X12, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X13, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 436e4c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
B 436e4c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass.omp_outlined.20
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.33 to 9.67 cycles (2.52x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 576 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	162
loop length	648
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.00	10.00	8.50	8.50	8.50	8.50	8.50	8.50	1.75	1.75	1.75	1.75	24.33	24.33	24.33	4.00	4.00
cycles	10.00	10.00	8.50	8.50	8.50	8.50	8.50	8.50	1.75	1.75	1.75	1.75	24.33	24.33	24.33	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	18.88
Overall L1	24.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.33 cycles. At this rate:

24% of peak load performance is reached (23.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.63 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 437448

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 437578 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X11, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X13, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 436f28 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W13, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
TBZ W16, #0, 436ec0 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [X21, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X12, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 436f28 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x3f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X13, X13, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X15, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDUR X9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X13, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X10, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 436fe8 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W13, W12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X12, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
TBZ W16, #0, 436f7c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X1, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X18, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X12, [X22, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [X18, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X12, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X13, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 436fe8 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x4b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X15, X13, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
ADD X13, X13, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X16, X15, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X9, [X2, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X2, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X16, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43704c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X5, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 43700c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x4dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X10, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X13, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4372e0 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X24, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X4, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X27, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X23, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X27, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X25, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 43710c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, X10	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 437448 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x918>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D2, D2, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMP D2, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 437468 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x938>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D0, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FDIV D0, D0, D2	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (50.0%)
LDR X15, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X14, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X10, X9, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDP X2, X1, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X4, X3, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X6, X5, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X7, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.LE 4374f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x9c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X12, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 4374d0 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x9a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
AND X13, X10, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X15, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X15, X16, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X16, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4374f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x9c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X9, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X12, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X17, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X9, X8, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 436e4c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X9, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 437548 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0xa18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
AND X11, X9, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X12, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X13, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 436e4c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X8, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
B 436e4c <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x31c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code