OV - exec - Loop 3434

  (3433) 0x49d540 CMP	X21, X28

  (3433) 0x49d544 B.GE	49d618

  (3433) 0x49d548 LDR	X16, [X8, X21,LSL #3]

  (3433) 0x49d54c LDR	X17, [X19]

  (3433) 0x49d550 CBZ	X17, 49d564

  (3433) 0x49d554 STR	X9, [X20, X21,LSL #3]

  (3433) 0x49d558 STR	XZR, [X10, X9,LSL #3]

  (3433) 0x49d55c STR	X21, [X11, X9,LSL #3]

  (3433) 0x49d560 ADD	X9, X9, #1

  (3433) 0x49d564 LDR	X17, [X12, X21,LSL #3]

  (3433) 0x49d568 ADD	X21, X21, #1

  (3433) 0x49d56c LDR	X3, [X12, X21,LSL #3]

  (3433) 0x49d570 CMP	X17, X3

  (3433) 0x49d574 B.GE	49d540

0x49d578 LDR	X18, [X27]

0x49d57c LDR	X0, [X24]

0x49d580 B	49d594

0x49d588 ADD	X17, X17, #1

0x49d58c CMP	X17, X3

0x49d590 B.GE	49d540

0x49d594 LDR	X1, [X13, X17,LSL #3]

0x49d598 ADD	X1, X15, X1,LSL #3

0x49d59c LDP	X2, X4, [X1]

0x49d5a0 CMP	X2, X4

0x49d5a4 B.GE	49d588

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 272 - 286

--------------------------------------------------------------------------------

272:    for (ic = ns; ic < ne; ic++)

273:    {

274:       row_start = C_i[ic];

275:       if (allsquare)

276:       {

277:          B_marker[ic] = counter;

278:          C_data[counter] = 0;

279:          C_j[counter] = ic;

280:          counter++;

281:       }

282:       for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

283:       {

284: 	 ja = A_j[ia];

285: 	 a_entry = A_data[ia];

286: 	 for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P0, P1,
Function	hypre_CSRMatrixMultiply.omp_outlined
Source	csr_matop.c:282-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.75
Front-end cycles	1.38
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	0.67
P7 cycles	0.67
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.33
P13 cycles	1.33
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P0, P1,
Function	hypre_CSRMatrixMultiply.omp_outlined
Source	csr_matop.c:282-286
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.50
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	1.50
CQA cycles if fully vectorized	0.75
Front-end cycles	1.38
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	0.67
P7 cycles	0.67
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.33
P13 cycles	1.33
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_CSRMatrixMultiply.omp_outlined
Source file and lines	csr_matop.c:272-286
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:272-286.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282-286.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.75 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	0.67	0.67	0.67	0.67	0.67	0.67	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	1.50	1.50	0.67	0.67	0.67	0.67	0.67	0.67	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.38
Overall L1	1.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

27% of peak load performance is reached (26.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 49d588

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X18, [X27]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 49d594 <hypre_CSRMatrixMultiply.omp_outlined+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X17, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 49d540 <hypre_CSRMatrixMultiply.omp_outlined+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X13, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X1, X15, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDP X2, X4, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
CMP X2, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 49d588 <hypre_CSRMatrixMultiply.omp_outlined+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_CSRMatrixMultiply.omp_outlined
Source file and lines	csr_matop.c:272-286
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:272-286.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:282-286.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.50 to 0.75 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	0.67	0.67	0.67	0.67	0.67	0.67	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00
cycles	1.50	1.50	0.67	0.67	0.67	0.67	0.67	0.67	0.00	0.00	0.00	0.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.38
Overall L1	1.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.50 cycles. At this rate:

27% of peak load performance is reached (26.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 49d588

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X18, [X27]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 49d594 <hypre_CSRMatrixMultiply.omp_outlined+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X17, X3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 49d540 <hypre_CSRMatrixMultiply.omp_outlined+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X13, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X1, X15, X1,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDP X2, X4, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
CMP X2, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 49d588 <hypre_CSRMatrixMultiply.omp_outlined+0x4a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code