OV - exec - Loop 2833

	Loop Id: 2833	Module: exec	Source: par_csr_matop.c:865-989 [...]	Coverage: 0.26%

  (2832) 0x484b40 LDUR	X8, [X29, #432]

  (2832) 0x484b44 ORR	X19, XZR, X2

  (2832) 0x484b48 ORR	X22, XZR, X1

  (2832) 0x484b4c CMP	X26, X8

  (2832) 0x484b50 B.GE	484e90

  (2832) 0x484b54 LDUR	X8, [X29, #424]

  (2832) 0x484b58 LDR	X8, [X8]

  (2832) 0x484b5c CBZ	X8, 484b7c

  (2832) 0x484b60 LDUR	X8, [X29, #408]

  (2832) 0x484b64 ADD	X1, X22, #1

  (2832) 0x484b68 STR	X22, [X0, X26,LSL #3]

  (2832) 0x484b6c LDR	D0, [X8]

  (2832) 0x484b70 LDP	X8, X9, [SP, #104]

  (2832) 0x484b74 STR	X26, [X8, X22,LSL #3]

  (2832) 0x484b78 STR	D0, [X9, X22,LSL #3]

  (2832) 0x484b7c LDUR	X8, [X29, #416]

  (2832) 0x484b80 LDR	X8, [X8]

  (2832) 0x484b84 CBZ	X8, 484d00

  (2832) 0x484b88 LDR	X8, [SP, #96]

  (2832) 0x484b8c ADD	X3, X8, X26,LSL #3

  (2832) 0x484b90 LDP	X4, X8, [X3]

  (2832) 0x484b94 CMP	X4, X8

  (2832) 0x484b98 B.GE	484d20

  (2832) 0x484b9c LDP	X9, X8, [SP, #48]

  (2832) 0x484ba0 ORR	X2, XZR, X19

  (2832) 0x484ba4 LDR	X5, [X9]

  (2832) 0x484ba8 LDR	X6, [X8]

  (2832) 0x484bac B	484bd0

    (2836) 0x484bc0 LDR	X8, [X3, #8]

    (2836) 0x484bc4 ADD	X4, X4, #1

    (2836) 0x484bc8 CMP	X4, X8

    (2836) 0x484bcc B.GE	484d04

    (2836) 0x484bd0 LDP	X8, X9, [X29, #984]

    (2836) 0x484bd4 LDR	X30, [X9, X4,LSL #3]

    (2836) 0x484bd8 LDR	D0, [X8, X4,LSL #3]

    (2836) 0x484bdc ADD	X7, X30, #1

    (2836) 0x484be0 LDR	X8, [X13, X30,LSL #3]

    (2836) 0x484be4 LDR	X23, [X13, X7,LSL #3]

    (2836) 0x484be8 CMP	X8, X23

    (2836) 0x484bec B.GE	484c6c

    (2836) 0x484bf0 LDUR	X9, [X29, #440]

    (2836) 0x484bf4 LDP	X10, X11, [X29, #1000]

    (2836) 0x484bf8 LDR	X9, [X9]

    (2836) 0x484bfc LDR	X10, [X10]

    (2836) 0x484c00 LDR	X27, [X11]

    (2836) 0x484c04 B	484c24

      (2838) 0x484c08 LDR	D1, [X9, X8,LSL #3]

      (2838) 0x484c0c LDR	D2, [X10, X11,LSL #3]

      (2838) 0x484c10 FMADD	D1, D0, D1, D2

      (2838) 0x484c14 STR	D1, [X10, X11,LSL #3]

      (2838) 0x484c18 ADD	X8, X8, #1

      (2838) 0x484c1c CMP	X8, X23

      (2838) 0x484c20 B.GE	484c6c

      (2838) 0x484c24 LDR	X11, [X20]

      (2838) 0x484c28 LDR	X12, [X5, X8,LSL #3]

      (2838) 0x484c2c ADD	X24, X12, X11

      (2838) 0x484c30 LDR	X11, [X0, X24,LSL #3]

      (2838) 0x484c34 CMP	X11, X19

      (2838) 0x484c38 B.GE	484c08

      (2838) 0x484c3c STR	X2, [X0, X24,LSL #3]

      (2838) 0x484c40 LDR	D1, [X9, X8,LSL #3]

      (2838) 0x484c44 LDR	X11, [X20]

      (2838) 0x484c48 SUB	X11, X24, X11

      (2838) 0x484c4c STR	X11, [X27, X2,LSL #3]

      (2838) 0x484c50 FMUL	D1, D0, D1

      (2838) 0x484c54 LDR	X23, [X13, X7,LSL #3]

      (2838) 0x484c58 STR	D1, [X10, X2,LSL #3]

      (2838) 0x484c5c ADD	X2, X2, #1

      (2838) 0x484c60 ADD	X8, X8, #1

      (2838) 0x484c64 CMP	X8, X23

      (2838) 0x484c68 B.LT	484c24

    (2836) 0x484c6c LDR	X8, [X14, X30,LSL #3]

    (2836) 0x484c70 LDR	X23, [X14, X7,LSL #3]

    (2836) 0x484c74 CMP	X8, X23

    (2836) 0x484c78 B.GE	484bc0

    (2836) 0x484c7c LDUR	X9, [X29, #448]

    (2836) 0x484c80 LDR	X10, [X25]

    (2836) 0x484c84 LDR	X27, [X21]

    (2836) 0x484c88 LDR	X9, [X9]

    (2836) 0x484c8c B	484cbc

      (2837) 0x484ca0 LDR	D1, [X9, X8,LSL #3]

      (2837) 0x484ca4 LDR	D2, [X10, X11,LSL #3]

      (2837) 0x484ca8 FMADD	D1, D0, D1, D2

      (2837) 0x484cac STR	D1, [X10, X11,LSL #3]

      (2837) 0x484cb0 ADD	X8, X8, #1

      (2837) 0x484cb4 CMP	X8, X23

      (2837) 0x484cb8 B.GE	484bc0

      (2837) 0x484cbc LDR	X24, [X6, X8,LSL #3]

      (2837) 0x484cc0 LDR	X11, [X0, X24,LSL #3]

      (2837) 0x484cc4 CMP	X11, X22

      (2837) 0x484cc8 B.GE	484ca0

      (2837) 0x484ccc LDR	D1, [X9, X8,LSL #3]

      (2837) 0x484cd0 STR	X1, [X0, X24,LSL #3]

      (2837) 0x484cd4 STR	X24, [X27, X1,LSL #3]

      (2837) 0x484cd8 LDR	X23, [X14, X7,LSL #3]

      (2837) 0x484cdc FMUL	D1, D0, D1

      (2837) 0x484ce0 STR	D1, [X10, X1,LSL #3]

      (2837) 0x484ce4 ADD	X1, X1, #1

      (2837) 0x484ce8 ADD	X8, X8, #1

      (2837) 0x484cec CMP	X8, X23

      (2837) 0x484cf0 B.LT	484cbc

    (2836) 0x484cf4 B	484bc0

  (2832) 0x484d00 ORR	X2, XZR, X19

  (2832) 0x484d04 LDR	X3, [X15, X26,LSL #3]

  (2832) 0x484d08 ADD	X26, X26, #1

  (2832) 0x484d0c LDR	X8, [X15, X26,LSL #3]

  (2832) 0x484d10 CMP	X3, X8

  (2832) 0x484d14 B.GE	484b40

0x484d18 B	484d38

  (2832) 0x484d20 ORR	X2, XZR, X19

  (2832) 0x484d24 LDR	X3, [X15, X26,LSL #3]

  (2832) 0x484d28 ADD	X26, X26, #1

  (2832) 0x484d2c LDR	X8, [X15, X26,LSL #3]

  (2832) 0x484d30 CMP	X3, X8

  (2832) 0x484d34 B.GE	484b40

0x484d38 LDP	X9, X8, [SP, #64]

0x484d3c LDR	X4, [X9]

0x484d40 LDR	X5, [X8]

0x484d44 LDP	X9, X8, [SP, #80]

0x484d48 LDR	X6, [X9]

0x484d4c LDR	X7, [X8]

0x484d50 B	484d70

0x484d60 LDR	X8, [X15, X26,LSL #3]

0x484d64 ADD	X3, X3, #1

0x484d68 CMP	X3, X8

0x484d6c B.GE	484b40

0x484d70 LDR	X8, [X16, X3,LSL #3]

0x484d74 LDR	D0, [X17, X3,LSL #3]

0x484d78 ADD	X30, X8, #1

0x484d7c LDR	X9, [X18, X8,LSL #3]

0x484d80 LDR	X27, [X18, X30,LSL #3]

0x484d84 CMP	X9, X27

0x484d88 B.GE	484df4

0x484d8c LDUR	X10, [X29, #464]

0x484d90 LDR	X23, [X25]

0x484d94 LDR	X24, [X21]

0x484d98 LDR	X10, [X10]

0x484d9c B	484dbc

  (2835) 0x484da0 LDR	D1, [X10, X9,LSL #3]

  (2835) 0x484da4 LDR	D2, [X23, X12,LSL #3]

  (2835) 0x484da8 FMADD	D1, D0, D1, D2

  (2835) 0x484dac STR	D1, [X23, X12,LSL #3]

  (2835) 0x484db0 ADD	X9, X9, #1

  (2835) 0x484db4 CMP	X9, X27

  (2835) 0x484db8 B.GE	484df4

  (2835) 0x484dbc LDR	X11, [X4, X9,LSL #3]

  (2835) 0x484dc0 LDR	X12, [X0, X11,LSL #3]

  (2835) 0x484dc4 CMP	X12, X22

  (2835) 0x484dc8 B.GE	484da0

  (2835) 0x484dcc LDR	D1, [X10, X9,LSL #3]

  (2835) 0x484dd0 STR	X1, [X0, X11,LSL #3]

  (2835) 0x484dd4 STR	X11, [X24, X1,LSL #3]

  (2835) 0x484dd8 LDR	X27, [X18, X30,LSL #3]

  (2835) 0x484ddc FMUL	D1, D0, D1

  (2835) 0x484de0 STR	D1, [X23, X1,LSL #3]

  (2835) 0x484de4 ADD	X1, X1, #1

  (2835) 0x484de8 ADD	X9, X9, #1

  (2835) 0x484dec CMP	X9, X27

  (2835) 0x484df0 B.LT	484dbc

0x484df4 LDR	X9, [X28]

0x484df8 CBZ	X9, 484d60

0x484dfc LDR	X8, [X5, X8,LSL #3]

0x484e00 LDR	X23, [X5, X30,LSL #3]

0x484e04 CMP	X8, X23

0x484e08 B.GE	484d60

0x484e0c LDUR	X9, [X29, #456]

0x484e10 LDP	X10, X11, [X29, #1000]

0x484e14 LDR	X9, [X9]

0x484e18 LDR	X10, [X10]

0x484e1c LDR	X27, [X11]

0x484e20 B	484e40

  (2834) 0x484e24 LDR	D1, [X9, X8,LSL #3]

  (2834) 0x484e28 LDR	D2, [X10, X11,LSL #3]

  (2834) 0x484e2c FMADD	D1, D0, D1, D2

  (2834) 0x484e30 STR	D1, [X10, X11,LSL #3]

  (2834) 0x484e34 ADD	X8, X8, #1

  (2834) 0x484e38 CMP	X8, X23

  (2834) 0x484e3c B.GE	484d60

  (2834) 0x484e40 LDR	X12, [X7, X8,LSL #3]

  (2834) 0x484e44 LDR	X11, [X20]

  (2834) 0x484e48 LDR	X12, [X6, X12,LSL #3]

  (2834) 0x484e4c ADD	X24, X12, X11

  (2834) 0x484e50 LDR	X11, [X0, X24,LSL #3]

  (2834) 0x484e54 CMP	X11, X19

  (2834) 0x484e58 B.GE	484e24

  (2834) 0x484e5c STR	X2, [X0, X24,LSL #3]

  (2834) 0x484e60 LDR	D1, [X9, X8,LSL #3]

  (2834) 0x484e64 LDR	X11, [X20]

  (2834) 0x484e68 SUB	X11, X24, X11

  (2834) 0x484e6c STR	X11, [X27, X2,LSL #3]

  (2834) 0x484e70 FMUL	D1, D0, D1

  (2834) 0x484e74 LDR	X23, [X5, X30,LSL #3]

  (2834) 0x484e78 STR	D1, [X10, X2,LSL #3]

  (2834) 0x484e7c ADD	X2, X2, #1

  (2834) 0x484e80 ADD	X8, X8, #1

  (2834) 0x484e84 CMP	X8, X23

  (2834) 0x484e88 B.LT	484e40

0x484e8c B	484d60

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.87
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	P12, P13, P14,
Function	hypre_ParMatmul.omp_outlined.7
Source	par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.67
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	7.67
CQA cycles if fully vectorized	3.83
Front-end cycles	4.63
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	0.92
P3 cycles	0.92
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	7.67
P13 cycles	7.67
P14 cycles	7.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.13
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.87
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks	P12, P13, P14,
Function	hypre_ParMatmul.omp_outlined.7
Source	par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.67
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	7.67
CQA cycles if fully vectorized	3.83
Front-end cycles	4.63
P0 cycles	4.50
P1 cycles	4.50
P2 cycles	0.92
P3 cycles	0.92
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.75
P7 cycles	0.75
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	7.67
P13 cycles	7.67
P14 cycles	7.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.13
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul.omp_outlined.7
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.67 to 2.67 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.67 to 3.83 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 208 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	0.92	0.92	0.83	0.83	0.75	0.75	0.00	0.00	0.00	0.00	7.67	7.67	7.67	0.00	0.00
cycles	4.50	4.50	0.92	0.92	0.83	0.83	0.75	0.75	0.00	0.00	0.00	0.00	7.67	7.67	7.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Overall L1	7.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.67 cycles. At this rate:

28% of peak load performance is reached (27.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 484d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
B 484d38 <hypre_ParMatmul.omp_outlined.7+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X4, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X9, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X6, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 484d70 <hypre_ParMatmul.omp_outlined.7+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X3, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 484b40 <hypre_ParMatmul.omp_outlined.7+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D0, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X30, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X9, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X27, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
CMP X9, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 484df4 <hypre_ParMatmul.omp_outlined.7+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X23, [X25]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X24, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
B 484dbc <hypre_ParMatmul.omp_outlined.7+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CBZ X9, 484d60 <hypre_ParMatmul.omp_outlined.7+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X23, [X5, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X8, X23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 484d60 <hypre_ParMatmul.omp_outlined.7+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X10, X11, [X29, #1000]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X27, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 484e40 <hypre_ParMatmul.omp_outlined.7+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 484d60 <hypre_ParMatmul.omp_outlined.7+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul.omp_outlined.7
Source file and lines	par_csr_matop.c:865-989
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.67 to 2.67 cycles (2.87x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.67 to 3.83 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 208 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	0.92	0.92	0.83	0.83	0.75	0.75	0.00	0.00	0.00	0.00	7.67	7.67	7.67	0.00	0.00
cycles	4.50	4.50	0.92	0.92	0.83	0.83	0.75	0.75	0.00	0.00	0.00	0.00	7.67	7.67	7.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.63
Overall L1	7.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.67 cycles. At this rate:

28% of peak load performance is reached (27.13 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 484d60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
B 484d38 <hypre_ParMatmul.omp_outlined.7+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X4, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X9, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X6, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 484d70 <hypre_ParMatmul.omp_outlined.7+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
CMP X3, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 484b40 <hypre_ParMatmul.omp_outlined.7+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR D0, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X30, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	N/A
LDR X9, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X27, [X18, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
CMP X9, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.GE 484df4 <hypre_ParMatmul.omp_outlined.7+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X23, [X25]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X24, [X21]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
B 484dbc <hypre_ParMatmul.omp_outlined.7+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CBZ X9, 484d60 <hypre_ParMatmul.omp_outlined.7+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X5, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X23, [X5, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
CMP X8, X23	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
B.GE 484d60 <hypre_ParMatmul.omp_outlined.7+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDP X10, X11, [X29, #1000]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.50	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDR X27, [X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
B 484e40 <hypre_ParMatmul.omp_outlined.7+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 484d60 <hypre_ParMatmul.omp_outlined.7+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code