OV - exec - Loop 2807

	Loop Id: 2807	Module: exec	Source: par_csr_matop.c:127-242 [...]	Coverage: 0.03%

0x482b80 STR	X23, [X5, X26,LSL #3]

0x482b84 STR	X20, [X7, X26,LSL #3]

0x482b88 ORR	X20, XZR, X24

0x482b8c ORR	X23, XZR, X6

0x482b90 ORR	X26, XZR, X30

0x482b94 ORR	X19, XZR, X21

0x482b98 CMP	X30, X21

0x482b9c B.EQ	482da0

0x482ba0 LDUR	X8, [X29, #496]

0x482ba4 LDR	X8, [X8]

0x482ba8 CBZ	X8, 482bb4

0x482bac ADD	X6, X23, #1

0x482bb0 STR	X23, [X0, X26,LSL #3]

0x482bb4 LDR	X8, [X15]

0x482bb8 CBZ	X8, 482c80

0x482bbc LDUR	X8, [X29, #488]

0x482bc0 ADD	X13, X8, X26,LSL #3

0x482bc4 LDP	X14, X8, [X13]

0x482bc8 CMP	X14, X8

0x482bcc B.GE	482ca0

0x482bd0 LDR	X8, [SP, #72]

0x482bd4 ORR	X24, XZR, X20

0x482bd8 LDR	X19, [X8]

0x482bdc LDUR	X8, [X29, #448]

0x482be0 LDR	X27, [X8]

0x482be4 B	482bf8

  (2811) 0x482be8 LDR	X8, [X13, #8]

  (2811) 0x482bec ADD	X14, X14, #1

  (2811) 0x482bf0 CMP	X14, X8

  (2811) 0x482bf4 B.GE	482c84

  (2811) 0x482bf8 LDR	X9, [X17, X14,LSL #3]

  (2811) 0x482bfc ADD	X8, X9, #1

  (2811) 0x482c00 LDR	X28, [X18, X9,LSL #3]

  (2811) 0x482c04 LDR	X10, [X18, X8,LSL #3]

  (2811) 0x482c08 B	482c10

    (2813) 0x482c0c ADD	X28, X28, #1

    (2813) 0x482c10 CMP	X28, X10

    (2813) 0x482c14 B.GE	482c40

    (2813) 0x482c18 LDR	X12, [X22]

    (2813) 0x482c1c LDR	X25, [X19, X28,LSL #3]

    (2813) 0x482c20 ADD	X12, X25, X12

    (2813) 0x482c24 LDR	X25, [X0, X12,LSL #3]

    (2813) 0x482c28 CMP	X25, X20

    (2813) 0x482c2c B.GE	482c0c

    (2813) 0x482c30 STR	X24, [X0, X12,LSL #3]

    (2813) 0x482c34 ADD	X24, X24, #1

    (2813) 0x482c38 LDR	X10, [X18, X8,LSL #3]

    (2813) 0x482c3c B	482c0c

  (2811) 0x482c40 LDR	X9, [X1, X9,LSL #3]

  (2811) 0x482c44 LDR	X10, [X1, X8,LSL #3]

  (2811) 0x482c48 B	482c50

    (2812) 0x482c4c ADD	X9, X9, #1

    (2812) 0x482c50 CMP	X9, X10

    (2812) 0x482c54 B.GE	482be8

    (2812) 0x482c58 LDR	X12, [X27, X9,LSL #3]

    (2812) 0x482c5c LDR	X25, [X0, X12,LSL #3]

    (2812) 0x482c60 CMP	X25, X23

    (2812) 0x482c64 B.GE	482c4c

    (2812) 0x482c68 STR	X6, [X0, X12,LSL #3]

    (2812) 0x482c6c ADD	X6, X6, #1

    (2812) 0x482c70 LDR	X10, [X1, X8,LSL #3]

    (2812) 0x482c74 B	482c4c

0x482c80 ORR	X24, XZR, X20

0x482c84 ADD	X30, X26, #1

0x482c88 LDR	X28, [X2, X26,LSL #3]

0x482c8c LDR	X8, [X2, X30,LSL #3]

0x482c90 CMP	X28, X8

0x482c94 B.GE	482b80

0x482ca0 ORR	X24, XZR, X20

0x482ca4 ADD	X30, X26, #1

0x482ca8 LDR	X28, [X2, X26,LSL #3]

0x482cac LDR	X8, [X2, X30,LSL #3]

0x482cb0 CMP	X28, X8

0x482cb4 B.GE	482b80

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P12,
Function	hypre_ParMatmul_RowSizes.omp_outlined
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:170-170,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	2.75
Front-end cycles	4.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	5.50
P13 cycles	5.17
P14 cycles	5.33
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.73
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P12,
Function	hypre_ParMatmul_RowSizes.omp_outlined
Source	par_csr_matop.c:127-127,par_csr_matop.c:135-137,par_csr_matop.c:144-146,par_csr_matop.c:170-170,par_csr_matop.c:187-187,par_csr_matop.c:241-242
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	5.50
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	2.75
Front-end cycles	4.75
P0 cycles	3.50
P1 cycles	3.50
P2 cycles	2.50
P3 cycles	2.50
P4 cycles	2.50
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	5.50
P13 cycles	5.17
P14 cycles	5.33
P15 cycles	1.50
P16 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.73
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_ParMatmul_RowSizes.omp_outlined
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187,241-242.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-146,170,187,241-242.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 2.75 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	38
loop length	152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50
cycles	3.50	3.50	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.75
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

21% of peak load performance is reached (20.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 482b80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR X23, [X5, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X20, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X26, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X30, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 482da0 <hypre_ParMatmul_RowSizes.omp_outlined+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 482bb4 <hypre_ParMatmul_RowSizes.omp_outlined+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X23, [X0, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X15]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 482c80 <hypre_ParMatmul_RowSizes.omp_outlined+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X8, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP X14, X8, [X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X14, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 482ca0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X19, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 482bf8 <hypre_ParMatmul_RowSizes.omp_outlined+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X30, X26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X28, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 482b80 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X30, X26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X28, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 482b80 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_ParMatmul_RowSizes.omp_outlined
Source file and lines	par_csr_matop.c:127-242
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 5.50 to 2.75 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	38
loop length	152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50
cycles	3.50	3.50	2.50	2.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	5.50	5.17	5.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.75
Overall L1	5.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

21% of peak load performance is reached (20.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 482b80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR X23, [X5, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X20, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X26, XZR, X30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X30, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 482da0 <hypre_ParMatmul_RowSizes.omp_outlined+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 482bb4 <hypre_ParMatmul_RowSizes.omp_outlined+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X6, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
STR X23, [X0, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X15]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 482c80 <hypre_ParMatmul_RowSizes.omp_outlined+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X8, X26,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDP X14, X8, [X13]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X14, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 482ca0 <hypre_ParMatmul_RowSizes.omp_outlined+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X24, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X19, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X27, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 482bf8 <hypre_ParMatmul_RowSizes.omp_outlined+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X30, X26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X28, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 482b80 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X30, X26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X28, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X2, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X28, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 482b80 <hypre_ParMatmul_RowSizes.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code