OV - exec - Loop 248

  (250) 0x421528 ADRP	X0,

  (250) 0x42152c ADD	X0, X0, #928

  (250) 0x421530 ORR	W1, WZR, W19

  (250) 0x421534 BL	40f3a0

  (250) 0x421538 LDP	X20, X19, [SP, #96]

  (250) 0x42153c LDP	X22, X21, [SP, #80]

  (250) 0x421540 LDP	X24, X23, [SP, #64]

  (250) 0x421544 LDR	X25, [SP, #48]

  (250) 0x421548 LDP	X29, X30, [SP, #32]

  (250) 0x42154c ADD	SP, SP, #112

  (250) 0x421550 RET

  (250) 0x421554 LDP	X16, X17, [X29, #88]

  (250) 0x421558 LDR	X15, [X29, #80]

  (250) 0x42155c LDR	X10, [X24]

  (250) 0x421560 FMOV	D0, #1.0000000

  (250) 0x421564 MOVN	X18, #0

  (250) 0x421568 MOVZ	W0, #1

  (250) 0x42156c LDR	X11, [X23]

  (250) 0x421570 LDR	X12, [X22]

  (250) 0x421574 LDR	X13, [X21]

  (250) 0x421578 LDR	X14, [X20]

  (250) 0x42157c LDR	X15, [X15]

  (250) 0x421580 LDR	X16, [X16]

  (250) 0x421584 LDR	X17, [X17]

  (250) 0x421588 B	4215ac

  (250) 0x42158c LDR	X2, [X12, X1,LSL #3]

  (250) 0x421590 CMP	X2, #1

  (250) 0x421594 B.LT	4215c0

  (250) 0x421598 STR	X0, [X12, X1,LSL #3]

  (250) 0x42159c ADD	X1, X9, #1

  (250) 0x4215a0 CMP	X9, X8

  (250) 0x4215a4 ORR	X9, XZR, X1

  (250) 0x4215a8 B.EQ	421528

  (250) 0x4215ac LDR	X1, [X10, X9,LSL #3]

  (250) 0x4215b0 LDR	D1, [X11, X1,LSL #3]

  (250) 0x4215b4 FCMP	D1, D0

  (250) 0x4215b8 B.PL	42158c

0x4215bc STR	X18, [X12, X1,LSL #3]

0x4215c0 ADD	X2, X1, #1

0x4215c4 LDR	X3, [X13, X1,LSL #3]

0x4215c8 LDR	X4, [X13, X2,LSL #3]

0x4215cc B	4215e4

  (249) 0x4215e0 ADD	X3, X3, #1

  (249) 0x4215e4 CMP	X3, X4

  (249) 0x4215e8 B.GE	421608

  (249) 0x4215ec LDR	X5, [X14, X3,LSL #3]

  (249) 0x4215f0 LDR	X5, [X12, X5,LSL #3]

  (249) 0x4215f4 CMP	X5, #1

  (249) 0x4215f8 B.LT	4215e0

  (249) 0x4215fc STR	X18, [X12, X1,LSL #3]

  (249) 0x421600 LDR	X4, [X13, X2,LSL #3]

  (249) 0x421604 B	4215e0

0x421608 LDR	X3, [X15, X1,LSL #3]

0x42160c LDR	X4, [X15, X2,LSL #3]

0x421610 B	421624

0x421624 CMP	X3, X4

0x421628 B.GE	42159c

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2435 - 2473

--------------------------------------------------------------------------------

2435: #pragma omp parallel for private(ig, i, jS, j) HYPRE_SMP_SCHEDULE

2436: #endif

2437:      for (ig = 0; ig < graph_size; ig++) {

2438:        i = graph_array[ig];

[...]

2446:        if(measure_array[i]<1.) CF_marker[i]= F_PT;

[...]

2453:        if (CF_marker[i] > 0) CF_marker[i] = C_PT;

[...]

2465: 	 for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2466:          {

2467: 	   /* j is the column number, or the local number of the point influencing i */

2468: 	   j = S_diag_j[jS];

2469: 	   if (CF_marker[j] > 0) /* j is a C-point */

2470: 	     CF_marker[i] = F_PT;

2471: 	 }

2472: 	 /* now the external part */

2473: 	 for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P12,
Function	hypre_BoomerAMGCoarsenPMIS.omp_outlined.21
Source	par_coarsen.c:2446-2446,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.83
CQA cycles if no scalar integer	1.83
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.92
Front-end cycles	1.25
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	0.42
P3 cycles	0.42
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.83
P13 cycles	1.50
P14 cycles	1.67
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.82
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.10
Bottlenecks	P12,
Function	hypre_BoomerAMGCoarsenPMIS.omp_outlined.21
Source	par_coarsen.c:2446-2446,par_coarsen.c:2465-2465,par_coarsen.c:2473-2473
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.83
CQA cycles if no scalar integer	1.83
CQA cycles if FP arith vectorized	1.83
CQA cycles if fully vectorized	0.92
Front-end cycles	1.25
P0 cycles	1.50
P1 cycles	1.50
P2 cycles	0.42
P3 cycles	0.42
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	1.83
P13 cycles	1.50
P14 cycles	1.67
P15 cycles	0.50
P16 cycles	0.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.82
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCoarsenPMIS.omp_outlined.21
Source file and lines	par_coarsen.c:2435-2473
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435-2438,2446,2453,2465-2473.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446,2465,2473.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.83 to 0.92 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	0.42	0.42	0.33	0.33	0.25	0.25	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50
cycles	1.50	1.50	0.42	0.42	0.33	0.33	0.25	0.25	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.25
Overall L1	1.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421624

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR X18, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X3, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4215e4 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X15, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 421624 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 42159c <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGCoarsenPMIS.omp_outlined.21
Source file and lines	par_coarsen.c:2435-2473
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435-2438,2446,2453,2465-2473.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2446,2465,2473.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 2 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.83 to 0.92 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	0.42	0.42	0.33	0.33	0.25	0.25	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50
cycles	1.50	1.50	0.42	0.42	0.33	0.33	0.25	0.25	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.25
Overall L1	1.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.83 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (4.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421624

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR X18, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X2, X1, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
LDR X3, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X13, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4215e4 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X15, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 421624 <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.GE 42159c <hypre_BoomerAMGCoarsenPMIS.omp_outlined.21+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code