OV - exec - Loop 2030

	Loop Id: 2030	Module: exec	Source: par_strength.c:253-472 [...]	Coverage: 0.08%

0x463c84 SUB	X11, X14, X5

0x463c88 ADD	X9, X11, X9

0x463c8c STUR	X9, [X29, #472]

0x463c90 LDUR	X11, [X29, #488]

0x463c94 CMP	X12, X11

0x463c98 B.GE	464774

0x463c9c STR	X10, [X8, X12,LSL #3]

0x463ca0 ORR	X27, XZR, X12

0x463ca4 LDR	X12, [X22]

0x463ca8 CBZ	X12, 463cb0

0x463cac STR	X9, [X18, X27,LSL #3]

0x463cb0 LDR	X19, [X1, X27,LSL #3]

0x463cb4 ADD	X12, X27, #1

0x463cb8 LDR	X14, [X17]

0x463cbc MOVI	D4, #0

0x463cc0 LDR	X28, [X1, X12,LSL #3]

0x463cc4 LDR	D5, [X0, X19,LSL #3]

0x463cc8 ADD	X20, X19, #1

0x463ccc FMOV	D6, D5

0x463cd0 CMP	X14, #2

0x463cd4 B.LT	463d2c

0x463cd8 FCMP	D5, #0

0x463cdc B.PL	463e80

0x463ce0 CMP	X20, X28

0x463ce4 B.GE	464024

0x463ce8 LDR	X21, [X4, X27,LSL #3]

0x463cec SUB	W14, W19, W28

0x463cf0 TBNZ	W14, #0, 464014

0x463cf4 LDUR	X11, [X29, #440]

0x463cf8 FMOV	D6, D5

0x463cfc LDR	X14, [X11, X20,LSL #3]

0x463d00 LDR	X14, [X4, X14,LSL #3]

0x463d04 CMP	X21, X14

0x463d08 B.NE	463d18

0x463d0c LDR	D6, [X0, X20,LSL #3]

0x463d10 FMAXNM	D4, D6, D2

0x463d14 FADD	D6, D5, D6

0x463d18 ADD	X20, X19, #2

0x463d1c SUB	X14, X28, #2

0x463d20 CMP	X14, X19

0x463d24 B.EQ	464024

0x463d28 B	4640a4

0x463d2c FCMP	D5, #0

0x463d30 B.PL	463ee0

0x463d34 CMP	X20, X28

0x463d38 B.GE	463de0

0x463d3c ORN	W11, WZR, W19

0x463d40 FMOV	D6, D5

0x463d44 ADD	W11, W28, W11

0x463d48 ANDS	X14, X11, #4160

0x463d4c B.EQ	463d7c

0x463d50 HINT	#0

0x463d54 HINT	#0

0x463d58 HINT	#0

0x463d5c HINT	#0

  (2038) 0x463d60 LDR	D7, [X0, X20,LSL #3]

  (2038) 0x463d64 ADD	X20, X20, #1

  (2038) 0x463d68 FCMP	D4, D7

  (2038) 0x463d6c FADD	D6, D6, D7

  (2038) 0x463d70 FCSEL	D4, D7, D4, #4

  (2038) 0x463d74 SUBS	X14, X14, #1

  (2038) 0x463d78 B.NE	463d60

0x463d7c SUB	X11, X28, X19

0x463d80 SUB	X11, X11, #2

0x463d84 CMP	X11, #3

0x463d88 B.CC	463de0

0x463d8c LDR	X11, [SP, #88]

0x463d90 SUB	X14, X28, X20

0x463d94 ADD	X5, X11, X20,LSL #3

0x463d98 HINT	#0

0x463d9c HINT	#0

  (2037) 0x463da0 LDP	D7, D16, [X5, #1008]

  (2037) 0x463da4 FCMP	D4, D7

  (2037) 0x463da8 FADD	D6, D6, D7

  (2037) 0x463dac FCSEL	D4, D7, D4, #4

  (2037) 0x463db0 FADD	D6, D6, D16

  (2037) 0x463db4 FCMP	D4, D16

  (2037) 0x463db8 FCSEL	D4, D16, D4, #4

  (2037) 0x463dbc LDP	D7, D16, [X5], #32

  (2037) 0x463dc0 FCMP	D4, D7

  (2037) 0x463dc4 FADD	D6, D6, D7

  (2037) 0x463dc8 FCSEL	D4, D7, D4, #4

  (2037) 0x463dcc FADD	D6, D6, D16

  (2037) 0x463dd0 FCMP	D4, D16

  (2037) 0x463dd4 FCSEL	D4, D16, D4, #4

  (2037) 0x463dd8 SUBS	X14, X14, #4

  (2037) 0x463ddc B.NE	463da0

0x463de0 LDR	X21, [X2, X27,LSL #3]

0x463de4 LDR	X20, [X2, X12,LSL #3]

0x463de8 SUBS	X14, X21, X20

0x463dec B.GE	4642a8

0x463df0 SUB	W11, W20, W21

0x463df4 ORR	X23, XZR, X21

0x463df8 ANDS	X5, X11, #4160

0x463dfc B.EQ	463e1c

  (2036) 0x463e00 LDR	D7, [X3, X23,LSL #3]

  (2036) 0x463e04 ADD	X23, X23, #1

  (2036) 0x463e08 FCMP	D4, D7

  (2036) 0x463e0c FADD	D6, D6, D7

  (2036) 0x463e10 FCSEL	D4, D7, D4, #4

  (2036) 0x463e14 SUBS	X5, X5, #1

  (2036) 0x463e18 B.NE	463e00

0x463e1c CMN	X14, #4

0x463e20 B.HI	4642a8

0x463e24 LDR	X11, [SP, #80]

0x463e28 ADD	X14, X11, X23,LSL #3

  (2035) 0x463e2c LDP	D7, D16, [X14, #1008]

  (2035) 0x463e30 ADD	X23, X23, #4

  (2035) 0x463e34 FCMP	D4, D7

  (2035) 0x463e38 FADD	D6, D6, D7

  (2035) 0x463e3c FCSEL	D4, D7, D4, #4

  (2035) 0x463e40 FADD	D6, D6, D16

  (2035) 0x463e44 FCMP	D4, D16

  (2035) 0x463e48 FCSEL	D4, D16, D4, #4

  (2035) 0x463e4c LDP	D7, D16, [X14], #32

  (2035) 0x463e50 FCMP	D4, D7

  (2035) 0x463e54 FADD	D6, D6, D7

  (2035) 0x463e58 FCSEL	D4, D7, D4, #4

  (2035) 0x463e5c FADD	D6, D6, D16

  (2035) 0x463e60 FCMP	D4, D16

  (2035) 0x463e64 FCSEL	D4, D16, D4, #4

  (2035) 0x463e68 CMP	X20, X23

  (2035) 0x463e6c B.NE	463e2c

0x463e70 B	4642a8

0x463e80 CMP	X20, X28

0x463e84 B.GE	46406c

0x463e88 LDR	X21, [X4, X27,LSL #3]

0x463e8c SUB	W14, W19, W28

0x463e90 TBNZ	W14, #0, 46405c

0x463e94 LDUR	X11, [X29, #440]

0x463e98 FMOV	D6, D5

0x463e9c LDR	X14, [X11, X20,LSL #3]

0x463ea0 LDR	X14, [X4, X14,LSL #3]

0x463ea4 CMP	X21, X14

0x463ea8 B.NE	463ebc

0x463eac LDR	D6, [X0, X20,LSL #3]

0x463eb0 FCMP	D6, #0

0x463eb4 FCSEL	D4, D2, D6, #12

0x463eb8 FADD	D6, D5, D6

0x463ebc ADD	X20, X19, #2

0x463ec0 SUB	X14, X28, #2

0x463ec4 CMP	X14, X19

0x463ec8 B.EQ	46406c

0x463ecc B	4641f4

0x463ee0 CMP	X20, X28

0x463ee4 B.GE	463f80

0x463ee8 ORN	W11, WZR, W19

0x463eec FMOV	D6, D5

0x463ef0 ADD	W11, W28, W11

0x463ef4 ANDS	X14, X11, #4160

0x463ef8 B.EQ	463f1c

0x463efc HINT	#0

  (2034) 0x463f00 LDR	D7, [X0, X20,LSL #3]

  (2034) 0x463f04 ADD	X20, X20, #1

  (2034) 0x463f08 FCMP	D4, D7

  (2034) 0x463f0c FADD	D6, D6, D7

  (2034) 0x463f10 FCSEL	D4, D4, D7, #4

  (2034) 0x463f14 SUBS	X14, X14, #1

  (2034) 0x463f18 B.NE	463f00

0x463f1c SUB	X11, X28, X19

0x463f20 SUB	X11, X11, #2

0x463f24 CMP	X11, #3

0x463f28 B.CC	463f80

0x463f2c LDR	X11, [SP, #88]

0x463f30 SUB	X14, X28, X20

0x463f34 ADD	X5, X11, X20,LSL #3

0x463f38 HINT	#0

0x463f3c HINT	#0

  (2033) 0x463f40 LDP	D7, D16, [X5, #1008]

  (2033) 0x463f44 FCMP	D4, D7

  (2033) 0x463f48 FADD	D6, D6, D7

  (2033) 0x463f4c FCSEL	D4, D4, D7, #4

  (2033) 0x463f50 FADD	D6, D6, D16

  (2033) 0x463f54 FCMP	D4, D16

  (2033) 0x463f58 FCSEL	D4, D4, D16, #4

  (2033) 0x463f5c LDP	D7, D16, [X5], #32

  (2033) 0x463f60 FCMP	D4, D7

  (2033) 0x463f64 FADD	D6, D6, D7

  (2033) 0x463f68 FCSEL	D4, D4, D7, #4

  (2033) 0x463f6c FADD	D6, D6, D16

  (2033) 0x463f70 FCMP	D4, D16

  (2033) 0x463f74 FCSEL	D4, D4, D16, #4

  (2033) 0x463f78 SUBS	X14, X14, #4

  (2033) 0x463f7c B.NE	463f40

0x463f80 LDR	X21, [X2, X27,LSL #3]

0x463f84 LDR	X20, [X2, X12,LSL #3]

0x463f88 SUBS	X14, X21, X20

0x463f8c B.GE	4642a8

0x463f90 SUB	W11, W20, W21

0x463f94 ORR	X23, XZR, X21

0x463f98 ANDS	X5, X11, #4160

0x463f9c B.EQ	463fbc

  (2032) 0x463fa0 LDR	D7, [X3, X23,LSL #3]

  (2032) 0x463fa4 ADD	X23, X23, #1

  (2032) 0x463fa8 FCMP	D4, D7

  (2032) 0x463fac FADD	D6, D6, D7

  (2032) 0x463fb0 FCSEL	D4, D4, D7, #4

  (2032) 0x463fb4 SUBS	X5, X5, #1

  (2032) 0x463fb8 B.NE	463fa0

0x463fbc CMN	X14, #4

0x463fc0 B.HI	4642a8

0x463fc4 LDR	X11, [SP, #80]

0x463fc8 ADD	X14, X11, X23,LSL #3

  (2031) 0x463fcc LDP	D7, D16, [X14, #1008]

  (2031) 0x463fd0 ADD	X23, X23, #4

  (2031) 0x463fd4 FCMP	D4, D7

  (2031) 0x463fd8 FADD	D6, D6, D7

  (2031) 0x463fdc FCSEL	D4, D4, D7, #4

  (2031) 0x463fe0 FADD	D6, D6, D16

  (2031) 0x463fe4 FCMP	D4, D16

  (2031) 0x463fe8 FCSEL	D4, D4, D16, #4

  (2031) 0x463fec LDP	D7, D16, [X14], #32

  (2031) 0x463ff0 FCMP	D4, D7

  (2031) 0x463ff4 FADD	D6, D6, D7

  (2031) 0x463ff8 FCSEL	D4, D4, D7, #4

  (2031) 0x463ffc FADD	D6, D6, D16

  (2031) 0x464000 FCMP	D4, D16

  (2031) 0x464004 FCSEL	D4, D4, D16, #4

  (2031) 0x464008 CMP	X20, X23

  (2031) 0x46400c B.NE	463fcc

0x464010 B	4642a8

0x464014 FMOV	D6, D5

0x464018 SUB	X14, X28, #2

0x46401c CMP	X14, X19

0x464020 B.NE	4640a4

0x464024 LDR	X21, [X2, X27,LSL #3]

0x464028 LDR	X20, [X2, X12,LSL #3]

0x46402c CMP	X20, X21

0x464030 B.LE	4642a8

0x464034 LDUR	X11, [X29, #464]

0x464038 LDR	X23, [X4, X27,LSL #3]

0x46403c SUB	W14, W20, W21

0x464040 LDR	X5, [X11]

0x464044 TBNZ	W14, #0, 464134

0x464048 ORR	X7, XZR, X21

0x46404c ADD	X14, X21, #1

0x464050 CMP	X20, X14

0x464054 B.NE	464168

0x464058 B	4642a8

0x46405c FMOV	D6, D5

0x464060 SUB	X14, X28, #2

0x464064 CMP	X14, X19

0x464068 B.NE	4641f4

0x46406c LDR	X21, [X2, X27,LSL #3]

0x464070 LDR	X20, [X2, X12,LSL #3]

0x464074 CMP	X20, X21

0x464078 B.LE	4642a8

0x46407c LDUR	X11, [X29, #464]

0x464080 LDR	X23, [X4, X27,LSL #3]

0x464084 LDR	X5, [X11]

0x464088 SUB	W11, W20, W21

0x46408c TBNZ	W11, #0, 464274

0x464090 ORR	X7, XZR, X21

0x464094 ADD	X11, X21, #1

0x464098 CMP	X20, X11

0x46409c B.EQ	4642a8

0x4640a4 LDR	X11, [SP, #72]

0x4640a8 SUB	X23, X28, X20

0x4640ac ADD	X14, X11, X20,LSL #3

0x4640b0 LDR	X11, [SP, #64]

0x4640b4 ADD	X20, X11, X20,LSL #3

0x4640b8 B	4640d0

  (2043) 0x4640c0 ADD	X20, X20, #16

  (2043) 0x4640c4 SUBS	X23, X23, #2

  (2043) 0x4640c8 ADD	X14, X14, #16

  (2043) 0x4640cc B.EQ	464024

  (2043) 0x4640d0 LDUR	X5, [X20, #504]

  (2043) 0x4640d4 LDR	X5, [X4, X5,LSL #3]

  (2043) 0x4640d8 CMP	X21, X5

  (2043) 0x4640dc B.EQ	464100

  (2043) 0x4640e0 LDR	X5, [X20]

  (2043) 0x4640e4 LDR	X5, [X4, X5,LSL #3]

  (2043) 0x4640e8 CMP	X21, X5

  (2043) 0x4640ec B.NE	4640c0

  (2043) 0x4640f0 B	464120

  (2043) 0x464100 LDUR	D7, [X14, #504]

  (2043) 0x464104 FCMP	D4, D7

  (2043) 0x464108 FADD	D6, D6, D7

  (2043) 0x46410c FCSEL	D4, D7, D4, #4

  (2043) 0x464110 LDR	X5, [X20]

  (2043) 0x464114 LDR	X5, [X4, X5,LSL #3]

  (2043) 0x464118 CMP	X21, X5

  (2043) 0x46411c B.NE	4640c0

  (2043) 0x464120 LDR	D7, [X14]

  (2043) 0x464124 FCMP	D4, D7

  (2043) 0x464128 FADD	D6, D6, D7

  (2043) 0x46412c FCSEL	D4, D7, D4, #4

  (2043) 0x464130 B	4640c0

0x464134 LDUR	X11, [X29, #432]

0x464138 LDR	X14, [X11, X21,LSL #3]

0x46413c LDR	X14, [X6, X14,LSL #3]

0x464140 CMP	X23, X14

0x464144 B.NE	464158

0x464148 LDR	D7, [X5, X21,LSL #3]

0x46414c FCMP	D4, D7

0x464150 FADD	D6, D6, D7

0x464154 FCSEL	D4, D7, D4, #4

0x464158 ADD	X7, X21, #1

0x46415c ADD	X14, X21, #1

0x464160 CMP	X20, X14

0x464164 B.EQ	4642a8

0x464168 LDR	X11, [SP, #56]

0x46416c ADD	X5, X5, X7,LSL #3

0x464170 SUB	X14, X20, X7

0x464174 ADD	X5, X5, #8

0x464178 ADD	X7, X11, X7,LSL #3

0x46417c B	464190

  (2042) 0x464180 SUBS	X14, X14, #2

  (2042) 0x464184 ADD	X5, X5, #16

  (2042) 0x464188 ADD	X7, X7, #16

  (2042) 0x46418c B.EQ	4642a8

  (2042) 0x464190 LDUR	X11, [X7, #504]

  (2042) 0x464194 LDR	X11, [X6, X11,LSL #3]

  (2042) 0x464198 CMP	X23, X11

  (2042) 0x46419c B.EQ	4641c0

  (2042) 0x4641a0 LDR	X11, [X7]

  (2042) 0x4641a4 LDR	X11, [X6, X11,LSL #3]

  (2042) 0x4641a8 CMP	X23, X11

  (2042) 0x4641ac B.NE	464180

  (2042) 0x4641b0 B	4641e0

  (2042) 0x4641c0 LDUR	D7, [X5, #504]

  (2042) 0x4641c4 FCMP	D4, D7

  (2042) 0x4641c8 FADD	D6, D6, D7

  (2042) 0x4641cc FCSEL	D4, D7, D4, #4

  (2042) 0x4641d0 LDR	X11, [X7]

  (2042) 0x4641d4 LDR	X11, [X6, X11,LSL #3]

  (2042) 0x4641d8 CMP	X23, X11

  (2042) 0x4641dc B.NE	464180

  (2042) 0x4641e0 LDR	D7, [X5]

  (2042) 0x4641e4 FCMP	D4, D7

  (2042) 0x4641e8 FADD	D6, D6, D7

  (2042) 0x4641ec FCSEL	D4, D7, D4, #4

  (2042) 0x4641f0 B	464180

0x4641f4 LDR	X11, [SP, #72]

0x4641f8 SUB	X23, X28, X20

0x4641fc ADD	X14, X11, X20,LSL #3

0x464200 LDR	X11, [SP, #64]

0x464204 ADD	X20, X11, X20,LSL #3

0x464208 B	46421c

  (2041) 0x46420c ADD	X20, X20, #16

  (2041) 0x464210 SUBS	X23, X23, #2

  (2041) 0x464214 ADD	X14, X14, #16

  (2041) 0x464218 B.EQ	46406c

  (2041) 0x46421c LDUR	X11, [X20, #504]

  (2041) 0x464220 LDR	X11, [X4, X11,LSL #3]

  (2041) 0x464224 CMP	X21, X11

  (2041) 0x464228 B.EQ	464240

  (2041) 0x46422c LDR	X11, [X20]

  (2041) 0x464230 LDR	X11, [X4, X11,LSL #3]

  (2041) 0x464234 CMP	X21, X11

  (2041) 0x464238 B.NE	46420c

  (2041) 0x46423c B	464260

  (2041) 0x464240 LDUR	D7, [X14, #504]

  (2041) 0x464244 FCMP	D4, D7

  (2041) 0x464248 FADD	D6, D6, D7

  (2041) 0x46424c FCSEL	D4, D4, D7, #4

  (2041) 0x464250 LDR	X11, [X20]

  (2041) 0x464254 LDR	X11, [X4, X11,LSL #3]

  (2041) 0x464258 CMP	X21, X11

  (2041) 0x46425c B.NE	46420c

  (2041) 0x464260 LDR	D7, [X14]

  (2041) 0x464264 FCMP	D4, D7

  (2041) 0x464268 FADD	D6, D6, D7

  (2041) 0x46426c FCSEL	D4, D4, D7, #4

  (2041) 0x464270 B	46420c

0x464274 LDUR	X11, [X29, #432]

0x464278 LDR	X11, [X11, X21,LSL #3]

0x46427c LDR	X11, [X6, X11,LSL #3]

0x464280 CMP	X23, X11

0x464284 B.NE	464298

0x464288 LDR	D7, [X5, X21,LSL #3]

0x46428c FCMP	D4, D7

0x464290 FADD	D6, D6, D7

0x464294 FCSEL	D4, D4, D7, #4

0x464298 ADD	X7, X21, #1

0x46429c ADD	X11, X21, #1

0x4642a0 CMP	X20, X11

0x4642a4 B.NE	4646e8

0x4642a8 ORN	X11, XZR, X19

0x4642ac ADD	X10, X28, X10

0x4642b0 FCMP	D0, D3

0x4642b4 ADD	X10, X10, X11

0x4642b8 SUB	X11, X20, X21

0x4642bc ADD	X9, X11, X9

0x4642c0 STP	X9, X10, [X29, #984]

0x4642c4 STR	X26, [X24, X19,LSL #3]

0x4642c8 B.PL	464360

0x4642cc FABS	D7, D5

0x4642d0 FABS	D6, D6

0x4642d4 FMUL	D7, D7, D0

0x4642d8 FCMP	D6, D7

0x4642dc B.LE	464360

0x4642e0 LDR	X11, [X1, X27,LSL #3]

0x4642e4 LDR	X5, [X1, X12,LSL #3]

0x4642e8 ADD	X14, X11, #1

0x4642ec CMP	X14, X5

0x4642f0 B.GE	46431c

0x4642f4 HINT	#0

0x4642f8 HINT	#0

0x4642fc HINT	#0

  (2053) 0x464300 STR	X26, [X24, X14,LSL #3]

  (2053) 0x464304 ADD	X14, X14, #1

  (2053) 0x464308 LDR	X5, [X1, X12,LSL #3]

  (2053) 0x46430c CMP	X14, X5

  (2053) 0x464310 B.LT	464300

0x464314 LDR	X11, [X1, X27,LSL #3]

0x464318 ADD	X14, X11, #1

0x46431c SUB	X11, X14, X5

0x464320 ADD	X10, X11, X10

0x464324 STUR	X10, [X29, #480]

0x464328 LDR	X14, [X2, X27,LSL #3]

0x46432c LDR	X5, [X2, X12,LSL #3]

0x464330 CMP	X14, X5

0x464334 B.GE	463c84

0x464338 HINT	#0

0x46433c HINT	#0

  (2052) 0x464340 STR	X26, [X30, X14,LSL #3]

  (2052) 0x464344 ADD	X14, X14, #1

  (2052) 0x464348 LDR	X5, [X2, X12,LSL #3]

  (2052) 0x46434c CMP	X14, X5

  (2052) 0x464350 B.LT	464340

0x464354 LDR	X14, [X2, X27,LSL #3]

0x464358 B	463c84

0x464360 LDR	X14, [X1, X27,LSL #3]

0x464364 LDR	X11, [X17]

0x464368 ADD	X19, X14, #1

0x46436c LDR	X14, [X1, X12,LSL #3]

0x464370 CMP	X11, #2

0x464374 B.LT	464480

0x464378 FCMP	D5, #0

0x46437c B.PL	464544

0x464380 CMP	X19, X14

0x464384 B.GE	4643f0

0x464388 LDR	X14, [X16]

0x46438c LDR	X5, [X15]

0x464390 FMUL	D5, D4, D1

0x464394 B	4643bc

  (2051) 0x4643a0 SUB	X10, X10, #1

  (2051) 0x4643a4 STR	X26, [X24, X19,LSL #3]

  (2051) 0x4643a8 STUR	X10, [X29, #480]

  (2051) 0x4643ac LDR	X11, [X1, X12,LSL #3]

  (2051) 0x4643b0 ADD	X19, X19, #1

  (2051) 0x4643b4 CMP	X19, X11

  (2051) 0x4643b8 B.GE	4643f0

  (2051) 0x4643bc LDR	D6, [X0, X19,LSL #3]

  (2051) 0x4643c0 FCMP	D6, D5

  (2051) 0x4643c4 B.LS	4643a0

  (2051) 0x4643c8 LDR	X7, [X5, X19,LSL #3]

  (2051) 0x4643cc LDR	X11, [X14, X27,LSL #3]

  (2051) 0x4643d0 LDR	X20, [X14, X7,LSL #3]

  (2051) 0x4643d4 CMP	X11, X20

  (2051) 0x4643d8 B.NE	4643a0

  (2051) 0x4643dc STR	X7, [X24, X19,LSL #3]

  (2051) 0x4643e0 LDR	X11, [X1, X12,LSL #3]

  (2051) 0x4643e4 ADD	X19, X19, #1

  (2051) 0x4643e8 CMP	X19, X11

  (2051) 0x4643ec B.LT	4643bc

0x4643f0 LDR	X14, [X2, X27,LSL #3]

0x4643f4 LDR	X11, [X2, X12,LSL #3]

0x4643f8 CMP	X14, X11

0x4643fc B.GE	463c90

0x464400 LDUR	X11, [X29, #448]

0x464404 LDR	X5, [X16]

0x464408 LDR	X19, [X13]

0x46440c FMUL	D4, D4, D1

0x464410 LDR	X20, [X25]

0x464414 LDR	X7, [X11]

0x464418 B	46443c

  (2050) 0x464420 SUB	X9, X9, #1

  (2050) 0x464424 STR	X26, [X20, X14,LSL #3]

  (2050) 0x464428 STUR	X9, [X29, #472]

  (2050) 0x46442c LDR	X11, [X2, X12,LSL #3]

  (2050) 0x464430 ADD	X14, X14, #1

  (2050) 0x464434 CMP	X14, X11

  (2050) 0x464438 B.GE	463c90

  (2050) 0x46443c LDR	D5, [X3, X14,LSL #3]

  (2050) 0x464440 FCMP	D5, D4

  (2050) 0x464444 B.LS	464420

  (2050) 0x464448 LDR	X21, [X19, X14,LSL #3]

  (2050) 0x46444c LDR	X11, [X5, X27,LSL #3]

  (2050) 0x464450 LDR	X23, [X7, X21,LSL #3]

  (2050) 0x464454 CMP	X11, X23

  (2050) 0x464458 B.NE	464420

  (2050) 0x46445c STR	X21, [X20, X14,LSL #3]

  (2050) 0x464460 LDR	X11, [X2, X12,LSL #3]

  (2050) 0x464464 ADD	X14, X14, #1

  (2050) 0x464468 CMP	X14, X11

  (2050) 0x46446c B.LT	46443c

0x464470 B	463c90

0x464480 FCMP	D5, #0

0x464484 B.PL	464634

0x464488 CMP	X19, X14

0x46448c B.GE	4644e0

0x464490 LDR	X14, [X15]

0x464494 FMUL	D5, D4, D1

0x464498 B	4644b8

  (2047) 0x4644a0 LDR	X11, [X14, X19,LSL #3]

  (2047) 0x4644a4 STR	X11, [X24, X19,LSL #3]

  (2047) 0x4644a8 LDR	X11, [X1, X12,LSL #3]

  (2047) 0x4644ac ADD	X19, X19, #1

  (2047) 0x4644b0 CMP	X19, X11

  (2047) 0x4644b4 B.GE	4644e0

  (2047) 0x4644b8 LDR	D6, [X0, X19,LSL #3]

  (2047) 0x4644bc FCMP	D6, D5

  (2047) 0x4644c0 B.HI	4644a0

  (2047) 0x4644c4 SUB	X10, X10, #1

  (2047) 0x4644c8 STR	X26, [X24, X19,LSL #3]

  (2047) 0x4644cc STUR	X10, [X29, #480]

  (2047) 0x4644d0 LDR	X11, [X1, X12,LSL #3]

  (2047) 0x4644d4 ADD	X19, X19, #1

  (2047) 0x4644d8 CMP	X19, X11

  (2047) 0x4644dc B.LT	4644b8

0x4644e0 LDR	X14, [X2, X27,LSL #3]

0x4644e4 LDR	X11, [X2, X12,LSL #3]

0x4644e8 CMP	X14, X11

0x4644ec B.GE	463c90

0x4644f0 LDR	X5, [X25]

0x4644f4 LDR	X7, [X13]

0x4644f8 FMUL	D4, D4, D1

0x4644fc B	464518

  (2046) 0x464500 LDR	X11, [X7, X14,LSL #3]

  (2046) 0x464504 STR	X11, [X5, X14,LSL #3]

  (2046) 0x464508 LDR	X11, [X2, X12,LSL #3]

  (2046) 0x46450c ADD	X14, X14, #1

  (2046) 0x464510 CMP	X14, X11

  (2046) 0x464514 B.GE	463c90

  (2046) 0x464518 LDR	D5, [X3, X14,LSL #3]

  (2046) 0x46451c FCMP	D5, D4

  (2046) 0x464520 B.HI	464500

  (2046) 0x464524 SUB	X9, X9, #1

  (2046) 0x464528 STR	X26, [X5, X14,LSL #3]

  (2046) 0x46452c STUR	X9, [X29, #472]

  (2046) 0x464530 LDR	X11, [X2, X12,LSL #3]

  (2046) 0x464534 ADD	X14, X14, #1

  (2046) 0x464538 CMP	X14, X11

  (2046) 0x46453c B.LT	464518

0x464540 B	463c90

0x464544 CMP	X19, X14

0x464548 B.GE	4645b0

0x46454c LDR	X14, [X16]

0x464550 LDR	X5, [X15]

0x464554 FMUL	D5, D4, D1

0x464558 B	46457c

  (2049) 0x464560 SUB	X10, X10, #1

  (2049) 0x464564 STR	X26, [X24, X19,LSL #3]

  (2049) 0x464568 STUR	X10, [X29, #480]

  (2049) 0x46456c LDR	X11, [X1, X12,LSL #3]

  (2049) 0x464570 ADD	X19, X19, #1

  (2049) 0x464574 CMP	X19, X11

  (2049) 0x464578 B.GE	4645b0

  (2049) 0x46457c LDR	D6, [X0, X19,LSL #3]

  (2049) 0x464580 FCMP	D6, D5

  (2049) 0x464584 B.GE	464560

  (2049) 0x464588 LDR	X7, [X5, X19,LSL #3]

  (2049) 0x46458c LDR	X11, [X14, X27,LSL #3]

  (2049) 0x464590 LDR	X20, [X14, X7,LSL #3]

  (2049) 0x464594 CMP	X11, X20

  (2049) 0x464598 B.NE	464560

  (2049) 0x46459c STR	X7, [X24, X19,LSL #3]

  (2049) 0x4645a0 LDR	X11, [X1, X12,LSL #3]

  (2049) 0x4645a4 ADD	X19, X19, #1

  (2049) 0x4645a8 CMP	X19, X11

  (2049) 0x4645ac B.LT	46457c

0x4645b0 LDR	X14, [X2, X27,LSL #3]

0x4645b4 LDR	X11, [X2, X12,LSL #3]

0x4645b8 CMP	X14, X11

0x4645bc B.GE	463c90

0x4645c0 LDUR	X11, [X29, #448]

0x4645c4 LDR	X5, [X16]

0x4645c8 LDR	X19, [X13]

0x4645cc FMUL	D4, D4, D1

0x4645d0 LDR	X20, [X25]

0x4645d4 LDR	X7, [X11]

0x4645d8 B	4645fc

  (2048) 0x4645e0 SUB	X9, X9, #1

  (2048) 0x4645e4 STR	X26, [X20, X14,LSL #3]

  (2048) 0x4645e8 STUR	X9, [X29, #472]

  (2048) 0x4645ec LDR	X11, [X2, X12,LSL #3]

  (2048) 0x4645f0 ADD	X14, X14, #1

  (2048) 0x4645f4 CMP	X14, X11

  (2048) 0x4645f8 B.GE	463c90

  (2048) 0x4645fc LDR	D5, [X3, X14,LSL #3]

  (2048) 0x464600 FCMP	D5, D4

  (2048) 0x464604 B.GE	4645e0

  (2048) 0x464608 LDR	X21, [X19, X14,LSL #3]

  (2048) 0x46460c LDR	X11, [X5, X27,LSL #3]

  (2048) 0x464610 LDR	X23, [X7, X21,LSL #3]

  (2048) 0x464614 CMP	X11, X23

  (2048) 0x464618 B.NE	4645e0

  (2048) 0x46461c STR	X21, [X20, X14,LSL #3]

  (2048) 0x464620 LDR	X11, [X2, X12,LSL #3]

  (2048) 0x464624 ADD	X14, X14, #1

  (2048) 0x464628 CMP	X14, X11

  (2048) 0x46462c B.LT	4645fc

0x464630 B	463c90

0x464634 FMUL	D4, D4, D1

0x464638 CMP	X19, X14

0x46463c B.GE	464688

0x464640 LDR	X14, [X15]

0x464644 B	464660

  (2045) 0x464648 LDR	X11, [X14, X19,LSL #3]

  (2045) 0x46464c STR	X11, [X24, X19,LSL #3]

  (2045) 0x464650 LDR	X11, [X1, X12,LSL #3]

  (2045) 0x464654 ADD	X19, X19, #1

  (2045) 0x464658 CMP	X19, X11

  (2045) 0x46465c B.GE	464688

  (2045) 0x464660 LDR	D5, [X0, X19,LSL #3]

  (2045) 0x464664 FCMP	D5, D4

  (2045) 0x464668 B.LT	464648

  (2045) 0x46466c SUB	X10, X10, #1

  (2045) 0x464670 STR	X26, [X24, X19,LSL #3]

  (2045) 0x464674 STUR	X10, [X29, #480]

  (2045) 0x464678 LDR	X11, [X1, X12,LSL #3]

  (2045) 0x46467c ADD	X19, X19, #1

  (2045) 0x464680 CMP	X19, X11

  (2045) 0x464684 B.LT	464660

0x464688 LDR	X14, [X2, X27,LSL #3]

0x46468c LDR	X11, [X2, X12,LSL #3]

0x464690 CMP	X14, X11

0x464694 B.GE	463c90

0x464698 LDR	X5, [X25]

0x46469c LDR	X7, [X13]

0x4646a0 B	4646bc

  (2044) 0x4646a4 LDR	X11, [X7, X14,LSL #3]

  (2044) 0x4646a8 STR	X11, [X5, X14,LSL #3]

  (2044) 0x4646ac LDR	X11, [X2, X12,LSL #3]

  (2044) 0x4646b0 ADD	X14, X14, #1

  (2044) 0x4646b4 CMP	X14, X11

  (2044) 0x4646b8 B.GE	463c90

  (2044) 0x4646bc LDR	D5, [X3, X14,LSL #3]

  (2044) 0x4646c0 FCMP	D5, D4

  (2044) 0x4646c4 B.LT	4646a4

  (2044) 0x4646c8 SUB	X9, X9, #1

  (2044) 0x4646cc STR	X26, [X5, X14,LSL #3]

  (2044) 0x4646d0 STUR	X9, [X29, #472]

  (2044) 0x4646d4 LDR	X11, [X2, X12,LSL #3]

  (2044) 0x4646d8 ADD	X14, X14, #1

  (2044) 0x4646dc CMP	X14, X11

  (2044) 0x4646e0 B.LT	4646bc

0x4646e4 B	463c90

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 253 - 472

--------------------------------------------------------------------------------

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

356:       }

357:       else

358:       {

359:          if (num_functions > 1)

360:          {

361:             if (diag < 0)

362:             {

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

370:                   }

371:                   else

372:                   {

373:                      S_temp_diag_j[jA] = A_diag_j[jA];

374:                   }

375:                }

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

383:                   }

384:                   else

385:                   {

386:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

399:                   }

400:                   else

401:                   {

402:                      S_temp_diag_j[jA] = A_diag_j[jA];

403:                   }

404:                }

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

412:                   }

413:                   else

414:                   {

415:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

422:             if (diag < 0)

423:             {

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.21
CQA speedup if FP arith vectorized	1.59
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCreateS.omp_outlined.2
Source	par_strength.c:253-258,par_strength.c:261-261,par_strength.c:266-275,par_strength.c:278-283,par_strength.c:289-294,par_strength.c:297-302,par_strength.c:309-311,par_strength.c:316-316,par_strength.c:324-324,par_strength.c:329-329,par_strength.c:337-338,par_strength.c:341-342,par_strength.c:345-345,par_strength.c:349-351,par_strength.c:355-355,par_strength.c:359-363,par_strength.c:376-376,par_strength.c:392-392,par_strength.c:405-405,par_strength.c:422-424,par_strength.c:436-436,par_strength.c:451-451,par_strength.c:463-463
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	37.50
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	23.53
CQA cycles if fully vectorized	36.50
Front-end cycles	37.50
P0 cycles	36.50
P1 cycles	36.50
P2 cycles	17.08
P3 cycles	17.08
P4 cycles	17.00
P5 cycles	17.00
P6 cycles	16.92
P7 cycles	16.92
P8 cycles	9.00
P9 cycles	8.75
P10 cycles	8.75
P11 cycles	8.50
P12 cycles	30.00
P13 cycles	30.00
P14 cycles	30.00
P15 cycles	3.00
P16 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	314.00
Nb uops	300.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.32
Nb FLOP add-sub	4.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.41
Bytes prefetched	0.00
Bytes loaded	672.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.50
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	58.33
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	2.21
CQA speedup if FP arith vectorized	1.59
CQA speedup if fully vectorized	1.03
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGCreateS.omp_outlined.2
Source	par_strength.c:253-258,par_strength.c:261-261,par_strength.c:266-275,par_strength.c:278-283,par_strength.c:289-294,par_strength.c:297-302,par_strength.c:309-311,par_strength.c:316-316,par_strength.c:324-324,par_strength.c:329-329,par_strength.c:337-338,par_strength.c:341-342,par_strength.c:345-345,par_strength.c:349-351,par_strength.c:355-355,par_strength.c:359-363,par_strength.c:376-376,par_strength.c:392-392,par_strength.c:405-405,par_strength.c:422-424,par_strength.c:436-436,par_strength.c:451-451,par_strength.c:463-463
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	37.50
CQA cycles if no scalar integer	17.00
CQA cycles if FP arith vectorized	23.53
CQA cycles if fully vectorized	36.50
Front-end cycles	37.50
P0 cycles	36.50
P1 cycles	36.50
P2 cycles	17.08
P3 cycles	17.08
P4 cycles	17.00
P5 cycles	17.00
P6 cycles	16.92
P7 cycles	16.92
P8 cycles	9.00
P9 cycles	8.75
P10 cycles	8.75
P11 cycles	8.50
P12 cycles	30.00
P13 cycles	30.00
P14 cycles	30.00
P15 cycles	3.00
P16 cycles	3.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	314.00
Nb uops	300.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.32
Nb FLOP add-sub	4.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.41
Bytes prefetched	0.00
Bytes loaded	672.00
Bytes stored	56.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	50.50
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	58.33
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGCreateS.omp_outlined.2
Source file and lines	par_strength.c:253-472
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:253-283,289-302,309-386,392-415,422-445,451-472.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:253-258,261,266-275,278-283,289-294,297-302,309-311,316,324,329,337-338,341-342,345,349-351,355,359-363,376,392,405,422-424,436,451,463.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.50 to 17.00 cycles (2.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 50% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 37.50 to 36.50 cycles (1.03x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

4: addition or subtraction
8: multiply

The binary loop is loading 672 bytes. The binary loop is storing 56 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	314
loop length	1256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

37.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	36.50	36.50	17.08	17.08	17.00	17.00	16.92	16.92	9.00	8.75	8.75	8.50	30.00	30.00	30.00	3.00	3.00
cycles	36.50	36.50	17.08	17.08	17.00	17.00	16.92	16.92	9.00	8.75	8.75	8.50	30.00	30.00	30.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	37.50
Overall L1	37.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 37.50 cycles. At this rate:

18% of peak load performance is reached (17.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4642a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB X11, X14, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X11, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464774 <hypre_BoomerAMGCreateS.omp_outlined.2+0xc14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X10, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X27, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 463cb0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X19, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D4, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X28, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR D5, [X0, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X20, X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X14, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 463d2c <hypre_BoomerAMGCreateS.omp_outlined.2+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.PL 463e80 <hypre_BoomerAMGCreateS.omp_outlined.2+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464024 <hypre_BoomerAMGCreateS.omp_outlined.2+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W14, W19, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W14, #0, 464014 <hypre_BoomerAMGCreateS.omp_outlined.2+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X14, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 463d18 <hypre_BoomerAMGCreateS.omp_outlined.2+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X0, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMAXNM D4, D6, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D6, D5, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X20, X19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464024 <hypre_BoomerAMGCreateS.omp_outlined.2+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4640a4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.PL 463ee0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463de0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W11, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W11, W28, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X14, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 463d7c <hypre_BoomerAMGCreateS.omp_outlined.2+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
SUB X11, X28, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X11, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 463de0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X28, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X21, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X14, X21, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W11, W20, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X5, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 463e1c <hypre_BoomerAMGCreateS.omp_outlined.2+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X14, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X11, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46406c <hypre_BoomerAMGCreateS.omp_outlined.2+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W14, W19, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W14, #0, 46405c <hypre_BoomerAMGCreateS.omp_outlined.2+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X14, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 463ebc <hypre_BoomerAMGCreateS.omp_outlined.2+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X0, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FCMP D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D4, D2, D6, #12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D6, D5, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X20, X19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 46406c <hypre_BoomerAMGCreateS.omp_outlined.2+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4641f4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463f80 <hypre_BoomerAMGCreateS.omp_outlined.2+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W11, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W11, W28, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X14, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 463f1c <hypre_BoomerAMGCreateS.omp_outlined.2+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
SUB X11, X28, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X11, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 463f80 <hypre_BoomerAMGCreateS.omp_outlined.2+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X28, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X21, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X14, X21, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W11, W20, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X5, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 463fbc <hypre_BoomerAMGCreateS.omp_outlined.2+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X14, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X11, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB X14, X28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4640a4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W14, W20, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
TBNZ W14, #0, 464134 <hypre_BoomerAMGCreateS.omp_outlined.2+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 464168 <hypre_BoomerAMGCreateS.omp_outlined.2+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB X14, X28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4641f4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W20, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W11, #0, 464274 <hypre_BoomerAMGCreateS.omp_outlined.2+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X23, X28, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4640d0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X6, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X23, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 464158 <hypre_BoomerAMGCreateS.omp_outlined.2+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X5, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FCMP D4, D7	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FADD D6, D6, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCSEL D4, D7, D4, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X7, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X20, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X11, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 464190 <hypre_BoomerAMGCreateS.omp_outlined.2+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X23, X28, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 46421c <hypre_BoomerAMGCreateS.omp_outlined.2+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X6, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X23, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 464298 <hypre_BoomerAMGCreateS.omp_outlined.2+0x738>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X5, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FCMP D4, D7	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FADD D6, D6, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCSEL D4, D4, D7, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X7, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4646e8 <hypre_BoomerAMGCreateS.omp_outlined.2+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN X11, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X28, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FCMP D0, D3	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X10, X10, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X20, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X11, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X9, X10, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X26, [X24, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.PL 464360 <hypre_BoomerAMGCreateS.omp_outlined.2+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FABS D7, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FABS D6, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D7, D7, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMP D6, D7	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 464360 <hypre_BoomerAMGCreateS.omp_outlined.2+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46431c <hypre_BoomerAMGCreateS.omp_outlined.2+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X11, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X14, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X11, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463c84 <hypre_BoomerAMGCreateS.omp_outlined.2+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 463c84 <hypre_BoomerAMGCreateS.omp_outlined.2+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X19, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 464480 <hypre_BoomerAMGCreateS.omp_outlined.2+0x920>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.PL 464544 <hypre_BoomerAMGCreateS.omp_outlined.2+0x9e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4643f0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x890>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D5, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 4643bc <hypre_BoomerAMGCreateS.omp_outlined.2+0x85c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D4, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X20, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 46443c <hypre_BoomerAMGCreateS.omp_outlined.2+0x8dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.PL 464634 <hypre_BoomerAMGCreateS.omp_outlined.2+0xad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4644e0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D5, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 4644b8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMUL D4, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 464518 <hypre_BoomerAMGCreateS.omp_outlined.2+0x9b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4645b0 <hypre_BoomerAMGCreateS.omp_outlined.2+0xa50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D5, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 46457c <hypre_BoomerAMGCreateS.omp_outlined.2+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D4, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X20, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4645fc <hypre_BoomerAMGCreateS.omp_outlined.2+0xa9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D4, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
CMP X19, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464688 <hypre_BoomerAMGCreateS.omp_outlined.2+0xb28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 464660 <hypre_BoomerAMGCreateS.omp_outlined.2+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4646bc <hypre_BoomerAMGCreateS.omp_outlined.2+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGCreateS.omp_outlined.2
Source file and lines	par_strength.c:253-472
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12 FP arithmetical operations:

4: addition or subtraction
8: multiply

The binary loop is loading 672 bytes. The binary loop is storing 56 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	314
loop length	1256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

37.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	36.50	36.50	17.08	17.08	17.00	17.00	16.92	16.92	9.00	8.75	8.75	8.50	30.00	30.00	30.00	3.00	3.00
cycles	36.50	36.50	17.08	17.08	17.00	17.00	16.92	16.92	9.00	8.75	8.75	8.50	30.00	30.00	30.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	37.50
Overall L1	37.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 37.50 cycles. At this rate:

18% of peak load performance is reached (17.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4642a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB X11, X14, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X11, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464774 <hypre_BoomerAMGCreateS.omp_outlined.2+0xc14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X10, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X27, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X12, 463cb0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X9, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X19, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X27, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D4, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X28, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR D5, [X0, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X20, X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X14, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 463d2c <hypre_BoomerAMGCreateS.omp_outlined.2+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.PL 463e80 <hypre_BoomerAMGCreateS.omp_outlined.2+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464024 <hypre_BoomerAMGCreateS.omp_outlined.2+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W14, W19, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W14, #0, 464014 <hypre_BoomerAMGCreateS.omp_outlined.2+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X14, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 463d18 <hypre_BoomerAMGCreateS.omp_outlined.2+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X0, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMAXNM D4, D6, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D6, D5, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X20, X19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 464024 <hypre_BoomerAMGCreateS.omp_outlined.2+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4640a4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.PL 463ee0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463de0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W11, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W11, W28, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X14, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 463d7c <hypre_BoomerAMGCreateS.omp_outlined.2+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
SUB X11, X28, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X11, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 463de0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X28, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X21, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X14, X21, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W11, W20, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X5, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 463e1c <hypre_BoomerAMGCreateS.omp_outlined.2+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X14, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X11, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46406c <hypre_BoomerAMGCreateS.omp_outlined.2+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W14, W19, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W14, #0, 46405c <hypre_BoomerAMGCreateS.omp_outlined.2+0x4fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X14, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X4, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X21, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 463ebc <hypre_BoomerAMGCreateS.omp_outlined.2+0x35c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D6, [X0, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FCMP D6, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCSEL D4, D2, D6, #12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D6, D5, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X20, X19, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 46406c <hypre_BoomerAMGCreateS.omp_outlined.2+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4641f4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X20, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463f80 <hypre_BoomerAMGCreateS.omp_outlined.2+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN W11, WZR, W19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD W11, W28, W11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ANDS X14, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 463f1c <hypre_BoomerAMGCreateS.omp_outlined.2+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
SUB X11, X28, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X11, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X11, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 463f80 <hypre_BoomerAMGCreateS.omp_outlined.2+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X14, X28, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X21, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X14, X21, X20	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W11, W20, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ANDS X5, X11, #4160	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 463fbc <hypre_BoomerAMGCreateS.omp_outlined.2+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMN X14, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X11, X23,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB X14, X28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4640a4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB W14, W20, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
TBNZ W14, #0, 464134 <hypre_BoomerAMGCreateS.omp_outlined.2+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 464168 <hypre_BoomerAMGCreateS.omp_outlined.2+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D6, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB X14, X28, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4641f4 <hypre_BoomerAMGCreateS.omp_outlined.2+0x694>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X20, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X23, [X4, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W20, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TBNZ W11, #0, 464274 <hypre_BoomerAMGCreateS.omp_outlined.2+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X7, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X23, X28, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4640d0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x570>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X6, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X23, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 464158 <hypre_BoomerAMGCreateS.omp_outlined.2+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X5, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FCMP D4, D7	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FADD D6, D6, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCSEL D4, D7, D4, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X7, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4642a8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x748>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X5, X5, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X14, X20, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, X5, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X7, X11, X7,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 464190 <hypre_BoomerAMGCreateS.omp_outlined.2+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X23, X28, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X11, X20,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 46421c <hypre_BoomerAMGCreateS.omp_outlined.2+0x6bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X6, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X23, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 464298 <hypre_BoomerAMGCreateS.omp_outlined.2+0x738>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X5, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FCMP D4, D7	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FADD D6, D6, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCSEL D4, D4, D7, #4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X7, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X11, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X20, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4646e8 <hypre_BoomerAMGCreateS.omp_outlined.2+0xb88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORN X11, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X28, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FCMP D0, D3	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X10, X10, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X11, X20, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X11, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X9, X10, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X26, [X24, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.PL 464360 <hypre_BoomerAMGCreateS.omp_outlined.2+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FABS D7, D5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FABS D6, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMUL D7, D7, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
FCMP D6, D7	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.LE 464360 <hypre_BoomerAMGCreateS.omp_outlined.2+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X14, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 46431c <hypre_BoomerAMGCreateS.omp_outlined.2+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X11, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X11, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X11, X14, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X11, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463c84 <hypre_BoomerAMGCreateS.omp_outlined.2+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 463c84 <hypre_BoomerAMGCreateS.omp_outlined.2+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X17]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X19, X14, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X14, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 464480 <hypre_BoomerAMGCreateS.omp_outlined.2+0x920>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.PL 464544 <hypre_BoomerAMGCreateS.omp_outlined.2+0x9e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4643f0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x890>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D5, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 4643bc <hypre_BoomerAMGCreateS.omp_outlined.2+0x85c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D4, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X20, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 46443c <hypre_BoomerAMGCreateS.omp_outlined.2+0x8dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D5, #0	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.PL 464634 <hypre_BoomerAMGCreateS.omp_outlined.2+0xad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4644e0 <hypre_BoomerAMGCreateS.omp_outlined.2+0x980>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D5, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 4644b8 <hypre_BoomerAMGCreateS.omp_outlined.2+0x958>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
FMUL D4, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 464518 <hypre_BoomerAMGCreateS.omp_outlined.2+0x9b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X19, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4645b0 <hypre_BoomerAMGCreateS.omp_outlined.2+0xa50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D5, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 46457c <hypre_BoomerAMGCreateS.omp_outlined.2+0xa1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMUL D4, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X20, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4645fc <hypre_BoomerAMGCreateS.omp_outlined.2+0xa9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMUL D4, D4, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
CMP X19, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464688 <hypre_BoomerAMGCreateS.omp_outlined.2+0xb28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 464660 <hypre_BoomerAMGCreateS.omp_outlined.2+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X2, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X2, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GE 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 4646bc <hypre_BoomerAMGCreateS.omp_outlined.2+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 463c90 <hypre_BoomerAMGCreateS.omp_outlined.2+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code