OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR.omp

	Function: hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15	Module: exec	Source: IJMatrix_parcsr.c:3240-3484 [...]	Coverage (incl. loops): 0.27% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3484

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

3323:       		           not_found = 0;

3324:       		           break;

3325:       	                }

3326:       	             }

3327:       	             if (not_found)

3328:       	             {

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

[...]

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

[...]

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

[...]

3417: 	                }

3418: 	                not_found = 1;

3419: 	             }

3420: 	             else  /* insert into diag */

3421: 	             {

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

[...]

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

0x498780 SUB	SP, SP, #352

0x498784 STP	X29, X30, [SP, #256]

0x498788 STP	X28, X27, [SP, #272]

0x49878c STP	X26, X25, [SP, #288]

0x498790 STP	X24, X23, [SP, #304]

0x498794 STP	X22, X21, [SP, #320]

0x498798 STP	X20, X19, [SP, #336]

0x49879c ADD	X29, SP, #256

0x4987a0 ORR	X28, XZR, X7

0x4987a4 ORR	X21, XZR, X6

0x4987a8 ORR	X24, XZR, X5

0x4987ac STUR	X4, [X29, #432]

0x4987b0 ORR	X23, XZR, X3

0x4987b4 ORR	X26, XZR, X2

0x4987b8 ORR	X25, XZR, X0

0x4987bc BL	4aae30

0x4987c0 ORR	X27, XZR, X0

0x4987c4 BL	4aae50

0x4987c8 LDR	X8, [X26]

0x4987cc ORR	X22, XZR, X0

0x4987d0 SDIV	X10, X8, X27

0x4987d4 ADD	X13, X10, #1

0x4987d8 MSUB	X11, X10, X27, X8

0x4987dc ADD	X8, X0, #1

0x4987e0 MADD	X12, X10, X8, X11

0x4987e4 MADD	X8, X13, X8, XZR

0x4987e8 MADD	X9, X10, X0, X11

0x4987ec MADD	X14, X13, X0, XZR

0x4987f0 CMP	X0, X11

0x4987f4 CSEL	X15, X12, X8, #10

0x4987f8 LDR	X12, [X23]

0x4987fc CSEL	X16, X9, X14, #10

0x498800 ADD	X8, X12, X0,LSL #3

0x498804 STR	XZR, [X8]

0x498808 CMP	X16, X15

0x49880c B.GE	4988b8

0x498810 LDUR	X9, [X29, #432]

0x498814 CMP	X22, X11

0x498818 CSEL	X11, X22, X11, #11

0x49881c MADD	X10, X22, X10, X11

0x498820 LDR	X9, [X9]

0x498824 SUB	X11, X15, X10

0x498828 CMP	X11, #14

0x49882c B.CC	498898

0x498830 ADD	X10, X12, X22,LSL #3

0x498834 ADD	X12, X9, X15,LSL #3

0x498838 ADD	X13, X9, X16,LSL #3

0x49883c ADD	X10, X10, #8

0x498840 CMP	X8, X12

0x498844 CCMP	X13, X10, #2, #3

0x498848 B.CC	498898

0x49884c AND	X12, X11, #8062

0x498850 ADD	X13, X13, #16

0x498854 MOVI	V0.2D, #0

0x498858 MOVI	V1.2D, #0

0x49885c ADD	X10, X16, X12

0x498860 ORR	X14, XZR, X12

(3349) 0x498864 LDP	Q2, Q3, [X13, #2032]

(3349) 0x498868 ADD	X13, X13, #32

(3349) 0x49886c SUBS	X14, X14, #4

(3349) 0x498870 ADD	V1.2D, V1.2D, V3.2D

(3349) 0x498874 ADD	V0.2D, V0.2D, V2.2D

(3349) 0x498878 B.NE	498864

0x49887c ADD	V0.2D, V1.2D, V0.2D

0x498880 ADDP	D0, V0.2D

0x498884 FMOV	X13, D0

0x498888 STR	D0, [X8]

0x49888c CMP	X11, X12

0x498890 B.NE	4988a0

0x498894 B	4988b8

0x498898 ORR	X13, XZR, XZR

0x49889c ORR	X10, XZR, X16

(3348) 0x4988a0 LDR	X11, [X9, X10,LSL #3]

(3348) 0x4988a4 ADD	X10, X10, #1

(3348) 0x4988a8 ADD	X13, X13, X11

(3348) 0x4988ac STR	X13, [X8]

(3348) 0x4988b0 CMP	X10, X15

(3348) 0x4988b4 B.LT	4988a0

0x4988b8 LDR	W25, [X25]

0x4988bc ADRP	X0,

0x4988c0 ADD	X0, X0, #3784

0x4988c4 ORR	X19, XZR, X16

0x4988c8 STUR	X15, [X29, #416]

0x4988cc ORR	W1, WZR, W25

0x4988d0 BL	40f890

0x4988d4 CBNZ	X22, 498920

0x4988d8 LDR	X8, [X24]

0x4988dc CMP	X8, #1

0x4988e0 B.LT	498920

0x4988e4 LDR	X8, [X23]

0x4988e8 ORR	X10, XZR, XZR

0x4988ec LDR	X9, [X8], #8

0x4988f0 HINT	#0

0x4988f4 HINT	#0

0x4988f8 HINT	#0

0x4988fc HINT	#0

(3347) 0x498900 LDR	X11, [X8, X10,LSL #3]

(3347) 0x498904 ADD	X9, X11, X9

(3347) 0x498908 ADD	X11, X10, #1

(3347) 0x49890c STR	X9, [X8, X10,LSL #3]

(3347) 0x498910 ORR	X10, XZR, X11

(3347) 0x498914 LDR	X12, [X24]

(3347) 0x498918 CMP	X11, X12

(3347) 0x49891c B.LT	498900

0x498920 ADRP	X0,

0x498924 ADD	X0, X0, #3808

0x498928 ORR	W1, WZR, W25

0x49892c BL	40f890

0x498930 CBZ	X22, 498958

0x498934 LDR	X8, [X23]

0x498938 ADD	X8, X8, X22,LSL #3

0x49893c LDUR	X24, [X8, #504]

0x498940 LDUR	X23, [X29, #432]

0x498944 LDUR	X7, [X29, #416]

0x498948 ORR	X30, XZR, X19

0x49894c CMP	X19, X7

0x498950 B.LT	498970

0x498954 B	49917c

0x498958 ORR	X24, XZR, XZR

0x49895c LDUR	X23, [X29, #432]

0x498960 LDUR	X7, [X29, #416]

0x498964 ORR	X30, XZR, X19

0x498968 CMP	X19, X7

0x49896c B.GE	49917c

0x498970 LDR	X8, [X29, #256]

0x498974 LDP	X26, X19, [X29, #264]

0x498978 LDR	X11, [X29, #96]

0x49897c MOVN	X27, #0

0x498980 STUR	XZR, [X29, #464]

0x498984 STR	X28, [SP, #88]

0x498988 STR	X8, [SP, #120]

0x49898c LDP	X8, X4, [X29, #240]

0x498990 STP	X26, X21, [X29, #912]

0x498994 STR	X8, [SP, #64]

0x498998 LDR	X8, [X29, #232]

0x49899c STUR	X4, [X29, #392]

0x4989a0 STR	X8, [SP, #56]

0x4989a4 LDR	X8, [X29, #224]

0x4989a8 STR	X8, [SP, #16]

0x4989ac LDR	X8, [X29, #216]

0x4989b0 STR	X8, [SP, #8]

0x4989b4 LDR	X8, [X29, #208]

0x4989b8 STR	X8, [SP, #48]

0x4989bc LDR	X8, [X29, #200]

0x4989c0 STR	X8, [SP, #40]

0x4989c4 LDP	X8, X9, [X29, #184]

0x4989c8 STP	X8, X9, [X29, #984]

0x4989cc LDR	X8, [X29, #176]

0x4989d0 STR	X8, [SP, #32]

0x4989d4 LDR	X8, [X29, #168]

0x4989d8 STR	X8, [SP, #24]

0x4989dc LDP	X8, X10, [X29, #152]

0x4989e0 STR	X8, [SP, #80]

0x4989e4 LDP	X8, X9, [X29, #136]

0x4989e8 STP	X11, X10, [X29, #960]

0x4989ec STUR	X8, [X29, #440]

0x4989f0 LDR	X8, [X29, #128]

0x4989f4 STUR	X9, [X29, #496]

0x4989f8 STR	X8, [SP, #112]

0x4989fc LDR	X8, [X29, #120]

0x498a00 STR	X8, [SP, #104]

0x498a04 LDR	X8, [X29, #112]

0x498a08 STR	X8, [SP, #96]

0x498a0c LDR	X8, [X29, #104]

0x498a10 STR	X8, [SP, #128]

0x498a14 B	498a4c

  (3341) 0x498a18 LDP	X26, X21, [X29, #912]

    (3339) 0x498a1c ORR	X0, XZR, X1

    (3339) 0x498a20 BL	4a91d0

  (3341) 0x498a24 LDUR	X0, [X29, #464]

  (3341) 0x498a28 BL	4a91d0

  (3341) 0x498a2c STUR	XZR, [X29, #464]

    (3340) 0x498a30 LDP	X7, X30, [X29, #928]

    (3340) 0x498a34 LDUR	X4, [X29, #392]

(3331) 0x498a38 LDUR	X10, [X29, #456]

  (3335) 0x498a3c LDUR	X11, [X29, #448]

  (3330) 0x498a40 ADD	X30, X30, #1

  (3330) 0x498a44 CMP	X30, X7

  (3330) 0x498a48 B.GE	49917c

  (3330) 0x498a4c LDR	X8, [X21]

  (3330) 0x498a50 LDR	X9, [X11]

  (3330) 0x498a54 LDR	X25, [X8, X30,LSL #3]

  (3330) 0x498a58 LDR	X8, [X23]

  (3330) 0x498a5c LDR	X20, [X8, X30,LSL #3]

  (3330) 0x498a60 LDR	X8, [X28]

  (3330) 0x498a64 ADD	X8, X8, X9,LSL #3

  (3330) 0x498a68 LDR	X9, [X8]

  (3330) 0x498a6c SUBS	X5, X25, X9

  (3330) 0x498a70 B.LT	498b28

  (3330) 0x498a74 LDR	X8, [X8, #8]

  (3330) 0x498a78 CMP	X25, X8

  (3330) 0x498a7c B.GE	498b28

  (3335) 0x498a80 LDR	X8, [SP, #128]

  (3335) 0x498a84 STUR	X5, [X29, #488]

  (3335) 0x498a88 LDR	X8, [X8]

  (3335) 0x498a8c CBZ	X8, 498c94

    (3340) 0x498a90 LDR	X8, [SP, #96]

    (3340) 0x498a94 STUR	X30, [X29, #424]

    (3340) 0x498a98 LDR	X8, [X8]

    (3340) 0x498a9c LDR	X23, [X8, X5,LSL #3]

    (3340) 0x498aa0 LDR	X8, [SP, #104]

    (3340) 0x498aa4 LDR	X8, [X8]

    (3340) 0x498aa8 LDR	X28, [X8, X5,LSL #3]

    (3340) 0x498aac LDR	X8, [SP, #112]

    (3340) 0x498ab0 LDR	X8, [X8]

    (3340) 0x498ab4 LDR	X16, [X8, X5,LSL #3]

    (3340) 0x498ab8 LDUR	X8, [X29, #440]

    (3340) 0x498abc LDR	X8, [X8]

    (3340) 0x498ac0 LDR	X25, [X8, X5,LSL #3]

    (3340) 0x498ac4 SUB	X8, X16, X25

    (3340) 0x498ac8 SUBS	X26, X20, X8

    (3340) 0x498acc B.LE	498dd4

    (3340) 0x498ad0 MOVZ	W1, #8

    (3340) 0x498ad4 ORR	X0, XZR, X26

    (3340) 0x498ad8 STUR	X16, [X29, #464]

    (3340) 0x498adc BL	4a90d0

    (3340) 0x498ae0 MOVZ	W1, #8

    (3340) 0x498ae4 ORR	X21, XZR, X0

    (3340) 0x498ae8 ORR	X0, XZR, X26

    (3340) 0x498aec BL	4a90d0

    (3340) 0x498af0 LDUR	X16, [X29, #464]

    (3340) 0x498af4 ORR	X1, XZR, X21

    (3340) 0x498af8 LDUR	X21, [X29, #408]

    (3340) 0x498afc LDUR	X5, [X29, #488]

    (3340) 0x498b00 STUR	X0, [X29, #464]

    (3340) 0x498b04 CMP	X20, #0

    (3340) 0x498b08 B.GT	498de8

    (3340) 0x498b0c LDP	X23, X8, [X29, #944]

    (3340) 0x498b10 LDR	X28, [SP, #88]

    (3340) 0x498b14 LDR	X8, [X8]

    (3340) 0x498b18 STR	X25, [X8, X5,LSL #3]

    (3340) 0x498b1c LDUR	X26, [X29, #400]

    (3340) 0x498b20 CBNZ	X1, 498a1c

    (3340) 0x498b24 B	498a30

  (3330) 0x498b28 LDR	X8, [X10]

  (3330) 0x498b2c LDR	X12, [X4]

  (3330) 0x498b30 ADD	X24, X20, X24

  (3330) 0x498b34 CMP	X8, #0

  (3330) 0x498b38 CCMP	X12, #1, #8, #1

  (3330) 0x498b3c B.LT	498a40

  (3330) 0x498b40 CMP	X20, #1

  (3330) 0x498b44 B.LT	498a40

(3331) 0x498b48 LDR	X10, [SP, #120]

(3331) 0x498b4c ORR	X8, XZR, XZR

(3331) 0x498b50 ORR	X9, XZR, XZR

(3331) 0x498b54 LDR	X10, [X10]

(3331) 0x498b58 B	498b74

0x498b5c HINT	#0

  (3332) 0x498b60 LDR	X12, [X4]

  (3332) 0x498b64 ADD	X8, X11, X8

  (3332) 0x498b68 ADD	X9, X9, #2

  (3332) 0x498b6c CMP	X9, X12

  (3332) 0x498b70 B.GE	498a38

  (3332) 0x498b74 ADD	X13, X10, X9,LSL #3

  (3332) 0x498b78 LDP	X13, X11, [X13]

  (3332) 0x498b7c CMP	X13, X25

  (3332) 0x498b80 B.NE	498b64

  (3332) 0x498b84 CMP	X11, #1

  (3332) 0x498b88 B.LT	498b64

  (3332) 0x498b8c LDUR	X14, [X29, #496]

  (3332) 0x498b90 LDR	X13, [X26]

  (3332) 0x498b94 AND	X15, X11, #8063

  (3332) 0x498b98 ORR	X12, XZR, XZR

  (3332) 0x498b9c LDR	X14, [X14]

  (3332) 0x498ba0 ADD	X16, X13, X8,LSL #3

  (3332) 0x498ba4 ADD	X16, X16, #8

  (3332) 0x498ba8 B	498bb8

    (3333) 0x498bac ADD	X12, X12, #1

    (3333) 0x498bb0 CMP	X12, X20

    (3333) 0x498bb4 B.EQ	498b60

    (3333) 0x498bb8 LDR	X17, [X19]

    (3333) 0x498bbc ORR	X18, XZR, X8

    (3333) 0x498bc0 CMP	X11, #1

    (3333) 0x498bc4 B.NE	498c00

    (3333) 0x498bc8 TBZ	W11, #0, 498bac

    (3333) 0x498bcc LDR	X0, [X13, X18,LSL #3]

    (3333) 0x498bd0 LDR	X1, [X14, X12,LSL #3]

    (3333) 0x498bd4 CMP	X0, X1

    (3333) 0x498bd8 B.NE	498bac

    (3333) 0x498bdc STR	X27, [X13, X18,LSL #3]

    (3333) 0x498be0 LDR	X18, [X17, X22,LSL #3]

    (3333) 0x498be4 ADD	X18, X18, #1

    (3333) 0x498be8 STR	X18, [X17, X22,LSL #3]

    (3333) 0x498bec B	498bac

0x498bf0 HINT	#0

0x498bf4 HINT	#0

0x498bf8 HINT	#0

0x498bfc HINT	#0

    (3333) 0x498c00 ORR	X0, XZR, X15

    (3333) 0x498c04 ORR	X1, XZR, X16

    (3333) 0x498c08 ORR	X18, XZR, X8

    (3333) 0x498c0c B	498c30

0x498c10 HINT	#0

0x498c14 HINT	#0

0x498c18 HINT	#0

0x498c1c HINT	#0

      (3334) 0x498c20 ADD	X18, X18, #2

      (3334) 0x498c24 ADD	X1, X1, #16

      (3334) 0x498c28 SUBS	X0, X0, #2

      (3334) 0x498c2c B.EQ	498bc8

      (3334) 0x498c30 LDUR	X2, [X1, #504]

      (3334) 0x498c34 LDR	X3, [X14, X12,LSL #3]

      (3334) 0x498c38 CMP	X2, X3

      (3334) 0x498c3c B.EQ	498c60

      (3334) 0x498c40 LDR	X2, [X1]

      (3334) 0x498c44 LDR	X3, [X14, X12,LSL #3]

      (3334) 0x498c48 CMP	X2, X3

      (3334) 0x498c4c B.NE	498c20

      (3334) 0x498c50 B	498c80

0x498c54 HINT	#0

0x498c58 HINT	#0

0x498c5c HINT	#0

      (3334) 0x498c60 STUR	X27, [X1, #504]

      (3334) 0x498c64 LDR	X2, [X17, X22,LSL #3]

      (3334) 0x498c68 ADD	X2, X2, #1

      (3334) 0x498c6c STR	X2, [X17, X22,LSL #3]

      (3334) 0x498c70 LDR	X2, [X1]

      (3334) 0x498c74 LDR	X3, [X14, X12,LSL #3]

      (3334) 0x498c78 CMP	X2, X3

      (3334) 0x498c7c B.NE	498c20

      (3334) 0x498c80 STR	X27, [X1]

      (3334) 0x498c84 LDR	X2, [X17, X22,LSL #3]

      (3334) 0x498c88 ADD	X2, X2, #1

      (3334) 0x498c8c STR	X2, [X17, X22,LSL #3]

      (3334) 0x498c90 B	498c20

  (3335) 0x498c94 LDR	X8, [X10]

  (3335) 0x498c98 UBFM	X12, X5, #61, #60

  (3335) 0x498c9c LDP	X10, X9, [X8, #56]

  (3335) 0x498ca0 LDR	X8, [X9, X12]

  (3335) 0x498ca4 LDR	X9, [X10, X12]

  (3335) 0x498ca8 CMP	X20, #1

  (3335) 0x498cac B.LT	498f94

  (3335) 0x498cb0 LDP	X11, X13, [SP, #24]

  (3335) 0x498cb4 LDUR	X15, [X29, #496]

  (3335) 0x498cb8 LDP	X16, X18, [SP, #56]

  (3335) 0x498cbc ADD	X14, X12, #8

  (3335) 0x498cc0 ORR	X10, XZR, XZR

  (3335) 0x498cc4 ORR	X21, XZR, X8

  (3335) 0x498cc8 ORR	X26, XZR, X9

  (3335) 0x498ccc LDR	X17, [SP, #80]

  (3335) 0x498cd0 LDP	X0, X1, [SP, #40]

  (3335) 0x498cd4 LDR	X11, [X11]

  (3335) 0x498cd8 LDR	X13, [X13]

  (3335) 0x498cdc LDR	X15, [X15]

  (3335) 0x498ce0 LDR	X16, [X16]

  (3335) 0x498ce4 LDR	X17, [X17]

  (3335) 0x498ce8 LDR	X18, [X18]

  (3335) 0x498cec LDR	X0, [X0]

  (3335) 0x498cf0 LDR	X1, [X1]

  (3335) 0x498cf4 LDR	X12, [X11, X14]

  (3335) 0x498cf8 LDR	X14, [X13, X14]

  (3335) 0x498cfc B	498d1c

    (3336) 0x498d00 LDR	D0, [X17, X24,LSL #3]

    (3336) 0x498d04 STR	D0, [X4]

    (3336) 0x498d08 LDUR	X5, [X29, #488]

    (3336) 0x498d0c ADD	X24, X24, #1

    (3336) 0x498d10 ADD	X10, X10, #1

    (3336) 0x498d14 CMP	X10, X20

    (3336) 0x498d18 B.EQ	499088

    (3336) 0x498d1c LDP	X3, X4, [X29, #984]

    (3336) 0x498d20 LDR	X2, [X15, X24,LSL #3]

    (3336) 0x498d24 LDR	X3, [X3]

    (3336) 0x498d28 LDR	X4, [X4]

    (3336) 0x498d2c CMP	X2, X3

    (3336) 0x498d30 CCMP	X2, X4, #0, #10

    (3336) 0x498d34 B.LE	498d80

    (3336) 0x498d38 LDR	X5, [X13, X5,LSL #3]

    (3336) 0x498d3c SUBS	X3, X8, X5

    (3336) 0x498d40 B.LE	498d64

    (3336) 0x498d44 ADD	X4, X1, X5,LSL #3

    (3336) 0x498d48 ADD	X5, X0, X5,LSL #3

      (3338) 0x498d4c LDR	X6, [X5], #8

      (3338) 0x498d50 CMP	X6, X2

      (3338) 0x498d54 B.EQ	498d00

      (3338) 0x498d58 ADD	X4, X4, #8

      (3338) 0x498d5c SUBS	X3, X3, #1

      (3338) 0x498d60 B.NE	498d4c

    (3336) 0x498d64 CMP	X21, X14

    (3336) 0x498d68 B.GE	499038

    (3336) 0x498d6c LDR	D0, [X17, X24,LSL #3]

    (3336) 0x498d70 STR	X2, [X0, X21,LSL #3]

    (3336) 0x498d74 STR	D0, [X1, X21,LSL #3]

    (3336) 0x498d78 ADD	X21, X21, #1

    (3336) 0x498d7c B	498d08

    (3336) 0x498d80 LDR	X5, [X11, X5,LSL #3]

    (3336) 0x498d84 SUBS	X3, X9, X5

    (3336) 0x498d88 B.LE	498db8

    (3336) 0x498d8c ADD	X4, X18, X5,LSL #3

    (3336) 0x498d90 ADD	X5, X16, X5,LSL #3

    (3336) 0x498d94 HINT	#0

    (3336) 0x498d98 HINT	#0

    (3336) 0x498d9c HINT	#0

      (3337) 0x498da0 LDR	X6, [X5], #8

      (3337) 0x498da4 CMP	X6, X2

      (3337) 0x498da8 B.EQ	498d00

      (3337) 0x498dac ADD	X4, X4, #8

      (3337) 0x498db0 SUBS	X3, X3, #1

      (3337) 0x498db4 B.NE	498da0

    (3336) 0x498db8 CMP	X26, X12

    (3336) 0x498dbc B.GE	4990a8

    (3336) 0x498dc0 LDR	D0, [X17, X24,LSL #3]

    (3336) 0x498dc4 STR	X2, [X16, X26,LSL #3]

    (3336) 0x498dc8 STR	D0, [X18, X26,LSL #3]

    (3336) 0x498dcc ADD	X26, X26, #1

    (3336) 0x498dd0 B	498d08

    (3340) 0x498dd4 LDUR	X0, [X29, #464]

    (3340) 0x498dd8 ORR	X1, XZR, XZR

    (3340) 0x498ddc STUR	X0, [X29, #464]

    (3340) 0x498de0 CMP	X20, #0

    (3340) 0x498de4 B.LE	498b0c

  (3341) 0x498de8 LDUR	X9, [X29, #496]

  (3341) 0x498dec LDR	X10, [SP, #80]

  (3341) 0x498df0 ORR	X21, XZR, XZR

  (3341) 0x498df4 ORR	X8, XZR, XZR

  (3341) 0x498df8 ORR	X26, XZR, X25

  (3341) 0x498dfc LDR	X9, [X9]

  (3341) 0x498e00 LDR	X10, [X10]

  (3341) 0x498e04 B	498e28

  (3341) 0x498e08 LDR	D0, [X10, X24,LSL #3]

  (3341) 0x498e0c STR	X11, [X1, X21,LSL #3]

  (3341) 0x498e10 STR	D0, [X0, X21,LSL #3]

  (3341) 0x498e14 ADD	X21, X21, #1

  (3341) 0x498e18 ADD	X24, X24, #1

  (3341) 0x498e1c ADD	X8, X8, #1

  (3341) 0x498e20 CMP	X8, X20

  (3341) 0x498e24 B.EQ	498e8c

  (3341) 0x498e28 CMP	X25, #1

  (3341) 0x498e2c B.LT	498e58

(3342) 0x498e30 LDR	X11, [X9, X24,LSL #3]

(3342) 0x498e34 ORR	X13, XZR, X25

(3342) 0x498e38 ORR	X14, XZR, X23

(3342) 0x498e3c ORR	X12, XZR, X28

  (3343) 0x498e40 LDR	X15, [X14], #8

  (3343) 0x498e44 CMP	X15, X11

  (3343) 0x498e48 B.EQ	498e80

  (3343) 0x498e4c ADD	X12, X12, #8

  (3343) 0x498e50 SUBS	X13, X13, #1

  (3343) 0x498e54 B.NE	498e40

  (3341) 0x498e58 LDR	X11, [X9, X24,LSL #3]

  (3341) 0x498e5c CMP	X26, X16

  (3341) 0x498e60 B.GE	498e08

  (3341) 0x498e64 LDR	D0, [X10, X24,LSL #3]

  (3341) 0x498e68 STR	X11, [X23, X26,LSL #3]

  (3341) 0x498e6c STR	D0, [X28, X26,LSL #3]

  (3341) 0x498e70 ADD	X26, X26, #1

  (3341) 0x498e74 B	498e18

0x498e78 HINT	#0

0x498e7c HINT	#0

(3342) 0x498e80 LDR	D0, [X10, X24,LSL #3]

(3342) 0x498e84 STR	D0, [X12]

(3342) 0x498e88 B	498e18

  (3341) 0x498e8c LDUR	X8, [X29, #440]

  (3341) 0x498e90 ADD	X23, X26, X21

  (3341) 0x498e94 LDR	X8, [X8]

  (3341) 0x498e98 STR	X23, [X8, X5,LSL #3]

  (3341) 0x498e9c CBZ	X21, 498f80

  (3341) 0x498ea0 LDR	X28, [SP, #96]

  (3341) 0x498ea4 UBFM	X20, X23, #61, #60

  (3341) 0x498ea8 STR	X1, [SP, #72]

  (3341) 0x498eac ORR	X1, XZR, X20

  (3341) 0x498eb0 LDR	X8, [X28]

  (3341) 0x498eb4 LDR	X0, [X8, X5,LSL #3]

  (3341) 0x498eb8 BL	4a9140

  (3341) 0x498ebc LDR	X8, [X28]

  (3341) 0x498ec0 LDUR	X9, [X29, #488]

  (3341) 0x498ec4 LDR	X25, [SP, #104]

  (3341) 0x498ec8 ORR	X1, XZR, X20

  (3341) 0x498ecc STR	X0, [X8, X9,LSL #3]

  (3341) 0x498ed0 LDUR	X9, [X29, #488]

  (3341) 0x498ed4 LDR	X8, [X25]

  (3341) 0x498ed8 LDR	X0, [X8, X9,LSL #3]

  (3341) 0x498edc BL	4a9140

  (3341) 0x498ee0 LDUR	X10, [X29, #488]

  (3341) 0x498ee4 LDR	X8, [X25]

  (3341) 0x498ee8 LDR	X12, [SP, #88]

  (3341) 0x498eec STR	X0, [X8, X10,LSL #3]

  (3341) 0x498ef0 LDR	X8, [SP, #112]

  (3341) 0x498ef4 LDR	X8, [X8]

  (3341) 0x498ef8 STR	X23, [X8, X10,LSL #3]

  (3341) 0x498efc CMP	X21, #1

  (3341) 0x498f00 B.LT	498fa0

  (3341) 0x498f04 LDR	X8, [X28]

  (3341) 0x498f08 LDR	X9, [X25]

  (3341) 0x498f0c LDUR	X23, [X29, #432]

  (3341) 0x498f10 LDUR	X18, [X29, #464]

  (3341) 0x498f14 LDR	X1, [SP, #72]

  (3341) 0x498f18 LDR	X8, [X8, X10,LSL #3]

  (3341) 0x498f1c LDR	X9, [X9, X10,LSL #3]

  (3341) 0x498f20 ORR	X10, XZR, XZR

  (3341) 0x498f24 CMP	X21, #4

  (3341) 0x498f28 B.CS	498fb8

  (3341) 0x498f2c ORR	X28, XZR, X12

  (3341) 0x498f30 ANDS	X12, X21, #4160

  (3341) 0x498f34 B.EQ	4990e8

  (3341) 0x498f38 ADD	X13, X9, X26,LSL #3

  (3341) 0x498f3c ADD	X14, X8, X26,LSL #3

  (3341) 0x498f40 ADD	X15, X18, X10,LSL #3

  (3341) 0x498f44 ADD	X16, X1, X10,LSL #3

  (3341) 0x498f48 ORR	X11, XZR, XZR

    (3345) 0x498f4c LDR	D0, [X15, X11,LSL #3]

    (3345) 0x498f50 LDR	X17, [X16, X11,LSL #3]

    (3345) 0x498f54 STR	X17, [X14, X11,LSL #3]

    (3345) 0x498f58 STR	D0, [X13, X11,LSL #3]

    (3345) 0x498f5c ADD	X11, X11, #1

    (3345) 0x498f60 CMP	X12, X11

    (3345) 0x498f64 B.NE	498f4c

  (3341) 0x498f68 ADD	X26, X26, X11

  (3341) 0x498f6c ADD	X12, X10, X11

  (3341) 0x498f70 SUB	X10, X10, X21

  (3341) 0x498f74 CMN	X10, #4

  (3341) 0x498f78 B.HI	498a18

  (3341) 0x498f7c B	4990f8

  (3341) 0x498f80 LDR	X28, [SP, #88]

  (3341) 0x498f84 LDP	X26, X21, [X29, #912]

  (3341) 0x498f88 LDUR	X23, [X29, #432]

  (3341) 0x498f8c CBNZ	X1, 498a1c

  (3341) 0x498f90 B	498a30

  (3335) 0x498f94 ORR	X26, XZR, X9

  (3335) 0x498f98 ORR	X21, XZR, X8

  (3335) 0x498f9c B	499088

  (3341) 0x498fa0 LDP	X26, X21, [X29, #912]

  (3341) 0x498fa4 LDUR	X23, [X29, #432]

  (3341) 0x498fa8 LDR	X1, [SP, #72]

  (3341) 0x498fac ORR	X28, XZR, X12

  (3341) 0x498fb0 CBNZ	X1, 498a1c

  (3341) 0x498fb4 B	498a30

  (3341) 0x498fb8 SUB	X11, X8, X1

  (3341) 0x498fbc ORR	X28, XZR, X12

  (3341) 0x498fc0 ADD	X11, X11, X26,LSL #3

  (3341) 0x498fc4 CMP	X11, #32

  (3341) 0x498fc8 B.CC	498f30

  (3341) 0x498fcc SUB	X11, X9, X18

  (3341) 0x498fd0 ADD	X11, X11, X26,LSL #3

  (3341) 0x498fd4 CMP	X11, #32

  (3341) 0x498fd8 B.CC	498f30

  (3341) 0x498fdc UBFM	X14, X26, #61, #60

  (3341) 0x498fe0 AND	X10, X21, #7998

  (3341) 0x498fe4 ADD	X11, X1, #16

  (3341) 0x498fe8 ADD	X13, X18, #16

  (3341) 0x498fec ADD	X12, X9, X14

  (3341) 0x498ff0 ADD	X14, X8, X14

  (3341) 0x498ff4 ADD	X26, X26, X10

  (3341) 0x498ff8 ORR	X15, XZR, X10

  (3341) 0x498ffc ADD	X12, X12, #16

  (3341) 0x499000 ADD	X14, X14, #16

    (3346) 0x499004 LDP	Q0, Q1, [X11, #2032]

    (3346) 0x499008 ADD	X11, X11, #32

    (3346) 0x49900c SUBS	X15, X15, #4

    (3346) 0x499010 STP	Q0, Q1, [X14, #2032]

    (3346) 0x499014 LDP	Q0, Q1, [X13, #2032]

    (3346) 0x499018 ADD	X13, X13, #32

    (3346) 0x49901c ADD	X14, X14, #32

    (3346) 0x499020 STP	Q0, Q1, [X12, #2032]

    (3346) 0x499024 ADD	X12, X12, #32

    (3346) 0x499028 B.NE	499004

  (3341) 0x49902c CMP	X21, X10

  (3341) 0x499030 B.EQ	498a18

  (3341) 0x499034 B	498f30

  (3335) 0x499038 ADRP	X0,

  (3335) 0x49903c ADD	X0, X0, #2482

  (3335) 0x499040 MOVZ	W1, #3406

  (3335) 0x499044 MOVZ	W2, #1

  (3335) 0x499048 ORR	X20, XZR, X30

  (3335) 0x49904c ORR	X3, XZR, XZR

  (3335) 0x499050 BL	4ab7e0

  (3335) 0x499054 LDR	X8, [SP, #8]

  (3335) 0x499058 MOVZ	W9, #1

  (3335) 0x49905c ADRP	X0,

  (3335) 0x499060 ADD	X0, X0, #2823

  (3335) 0x499064 LDADD	X9, X8, [X8]

  (3335) 0x499068 LDR	X8, [SP, #16]

  (3335) 0x49906c LDR	X8, [X8]

  (3335) 0x499070 CBZ	X8, 49907c

  (3335) 0x499074 ORR	X1, XZR, X25

  (3335) 0x499078 BL	4a9320

  (3335) 0x49907c LDUR	X7, [X29, #416]

  (3335) 0x499080 LDUR	X5, [X29, #488]

  (3335) 0x499084 ORR	X30, XZR, X20

  (3335) 0x499088 LDUR	X10, [X29, #456]

  (3335) 0x49908c LDUR	X4, [X29, #392]

  (3335) 0x499090 LDR	X8, [X10]

  (3335) 0x499094 LDP	X9, X8, [X8, #56]

  (3335) 0x499098 STR	X26, [X9, X5,LSL #3]

  (3335) 0x49909c STR	X21, [X8, X5,LSL #3]

  (3335) 0x4990a0 LDP	X26, X21, [X29, #912]

  (3335) 0x4990a4 B	498a3c

  (3335) 0x4990a8 ADRP	X0,

  (3335) 0x4990ac ADD	X0, X0, #2482

  (3335) 0x4990b0 MOVZ	W1, #3440

  (3335) 0x4990b4 MOVZ	W2, #1

  (3335) 0x4990b8 ORR	X20, XZR, X30

  (3335) 0x4990bc ORR	X3, XZR, XZR

  (3335) 0x4990c0 BL	4ab7e0

  (3335) 0x4990c4 LDR	X8, [SP, #8]

  (3335) 0x4990c8 MOVZ	W9, #1

  (3335) 0x4990cc ADRP	X0,

  (3335) 0x4990d0 ADD	X0, X0, #2861

  (3335) 0x4990d4 LDADD	X9, X8, [X8]

  (3335) 0x4990d8 LDR	X8, [SP, #16]

  (3335) 0x4990dc LDR	X8, [X8]

  (3335) 0x4990e0 CBNZ	X8, 499074

  (3335) 0x4990e4 B	49907c

  (3341) 0x4990e8 ORR	X12, XZR, X10

  (3341) 0x4990ec SUB	X10, X10, X21

  (3341) 0x4990f0 CMN	X10, #4

  (3341) 0x4990f4 B.HI	498a18

  (3341) 0x4990f8 ADD	X10, X1, X12,LSL #3

  (3341) 0x4990fc ADD	X11, X18, X12,LSL #3

  (3341) 0x499100 ADD	X9, X9, X26,LSL #3

  (3341) 0x499104 ADD	X8, X8, X26,LSL #3

  (3341) 0x499108 SUB	X12, X21, X12

  (3341) 0x49910c ADD	X10, X10, #16

  (3341) 0x499110 ADD	X11, X11, #16

  (3341) 0x499114 ADD	X9, X9, #16

  (3341) 0x499118 ADD	X8, X8, #16

  (3341) 0x49911c HINT	#0

    (3344) 0x499120 LDUR	D0, [X11, #496]

    (3344) 0x499124 LDUR	X13, [X10, #496]

    (3344) 0x499128 SUBS	X12, X12, #4

    (3344) 0x49912c STUR	X13, [X8, #496]

    (3344) 0x499130 LDUR	X13, [X10, #504]

    (3344) 0x499134 STUR	D0, [X9, #496]

    (3344) 0x499138 LDUR	D0, [X11, #504]

    (3344) 0x49913c STUR	X13, [X8, #504]

    (3344) 0x499140 LDR	X13, [X10]

    (3344) 0x499144 STUR	D0, [X9, #504]

    (3344) 0x499148 LDR	D0, [X11]

    (3344) 0x49914c STR	X13, [X8]

    (3344) 0x499150 LDR	X13, [X10, #8]

    (3344) 0x499154 ADD	X10, X10, #32

    (3344) 0x499158 STR	X13, [X8, #8]

    (3344) 0x49915c ADD	X8, X8, #32

    (3344) 0x499160 STR	D0, [X9]

    (3344) 0x499164 LDR	D0, [X11, #8]

    (3344) 0x499168 ADD	X11, X11, #32

    (3344) 0x49916c STR	D0, [X9, #8]

    (3344) 0x499170 ADD	X9, X9, #32

    (3344) 0x499174 B.NE	499120

  (3341) 0x499178 B	498a18

0x49917c LDP	X20, X19, [SP, #336]

0x499180 LDP	X22, X21, [SP, #320]

0x499184 LDP	X24, X23, [SP, #304]

0x499188 LDP	X26, X25, [SP, #288]

0x49918c LDP	X28, X27, [SP, #272]

0x499190 LDP	X29, X30, [SP, #256]

0x499194 ADD	SP, SP, #352

0x499198 RET

0x49919c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3352,3359-3368,3376-3377,3383-3390,3399-3411,3417-3424,3433-3445,3454-3458,3466-3484.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.33 to 1.00 cycles (23.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.33 to 18.92 cycles (1.23x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
7% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.33 to 2.00 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 388 bytes. The binary function is storing 328 bytes.

General properties

nb instructions	169
loop length	676
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.50	8.50	10.50	10.58	10.50	10.50	10.50	10.42	1.50	1.50	1.50	1.50	23.33	23.33	23.33	15.50	15.50
cycles	8.50	8.50	10.50	10.58	10.50	10.50	10.50	10.42	1.50	1.50	1.50	1.50	23.33	23.33	23.33	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.75
Overall L1	23.33

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.33 cycles. At this rate:

17% of peak load performance is reached (16.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 498780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X4, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X10, X8, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD X13, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MSUB X11, X10, X27, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X8, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X10, X8, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X8, X13, X8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X9, X10, X0, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X14, X13, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X0, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X15, X12, X8, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CSEL X16, X9, X14, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X12, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X16, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4988b8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X22, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X11, X22, X11, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X10, X22, X10, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X11, #14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 498898 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X12, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X9, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X9, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X13, X10, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 498898 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X12, X11, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X16, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X14, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADDP D0, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMOV X13, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X11, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4988a0 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4988b8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ee8bc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X15, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 498920 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 498920 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X8], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <4ee920>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3808	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X22, 498958 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X23, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X19, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 498970 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49917c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X23, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X19, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 49917c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVN X27, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X4, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X26, X21, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X4, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X11, X10, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 498a4c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	IJMatrix_parcsr.c:3240-3484
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
7% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.33 to 2.00 cycles (11.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 388 bytes. The binary function is storing 328 bytes.

General properties

nb instructions	169
loop length	676
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	8.50	8.50	10.50	10.58	10.50	10.50	10.50	10.42	1.50	1.50	1.50	1.50	23.33	23.33	23.33	15.50	15.50
cycles	8.50	8.50	10.50	10.58	10.50	10.50	10.50	10.42	1.50	1.50	1.50	1.50	23.33	23.33	23.33	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.75
Overall L1	23.33

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	7%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.33 cycles. At this rate:

17% of peak load performance is reached (16.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
29% of peak store performance is reached (14.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 498780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #256	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X28, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X4, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X27, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X10, X8, X27	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (50.0%)
ADD X13, X10, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MSUB X11, X10, X27, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X8, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X10, X8, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X8, X13, X8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X9, X10, X0, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X14, X13, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X0, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X15, X12, X8, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X12, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CSEL X16, X9, X14, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X8, X12, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X16, X15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4988b8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X22, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X11, X22, X11, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X10, X22, X10, X11	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X11, #14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CC 498898 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X10, X12, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X9, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X9, X16,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X13, X10, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 498898 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X12, X11, #8062	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI V0.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X10, X16, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X14, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD V0.2D, V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ADDP D0, V0.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (100.0%)
FMOV X13, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP X11, X12	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 4988a0 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 4988b8 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X13, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W25, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ee8bc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X15, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ X22, 498920 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 498920 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X8], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <4ee920>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #3808	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X22, 498958 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X8, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X23, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X19, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 498970 <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49917c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X23, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X7, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X19, X7	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 49917c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x9fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X19, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X11, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVN X27, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR XZR, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X4, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X26, X21, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X4, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X11, X10, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 498a4c <hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #352	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR.omp_outlined.15–	0.27	0.05
○Loop 3349 - IJMatrix_parcsr.c:3275-3275 - exec	0.00	0.00
▼Loop 3331 - IJMatrix_parcsr.c:3291-3484 - exec–	0.00	0.00
▼Loop 3335 - IJMatrix_parcsr.c:3296-3458 - exec–	0.03	0.01
▼Loop 3336 - IJMatrix_parcsr.c:3383-3454 - exec–	0.22	0.03
○Loop 3337 - IJMatrix_parcsr.c:3422-3424 - exec	0.00	0.00
○Loop 3338 - IJMatrix_parcsr.c:3388-3390 - exec	0.00	0.00
○Loop 3330 - IJMatrix_parcsr.c:3291-3467 - exec	0.01	0.01
▼Loop 3332 - IJMatrix_parcsr.c:3470-3484 - exec–	0.00	0.00
▼Loop 3333 - IJMatrix_parcsr.c:3475-3484 - exec–	0.00	0.00
○Loop 3334 - IJMatrix_parcsr.c:3478-3484 - exec	0.00	0.00
○Loop 3347 - IJMatrix_parcsr.c:3282-3283 - exec	0.00	0.00
○Loop 3348 - IJMatrix_parcsr.c:3274-3275 - exec	0.00	0.00
▼Loop 3342 - IJMatrix_parcsr.c:3291-3445 - exec–	0.00	0.00
▼Loop 3341 - IJMatrix_parcsr.c:3291-3445 - exec–	0.00	0.00
○Loop 3339 - IJMatrix_parcsr.c:3367-3367 - exec	0.00	0.00
○Loop 3345 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3340 - IJMatrix_parcsr.c:3300-3436 - exec	0.00	0.00
○Loop 3344 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3346 - IJMatrix_parcsr.c:3359-3362 - exec	0.00	0.00
○Loop 3343 - IJMatrix_parcsr.c:3318-3320 - exec	0.00	0.00

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Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code