OV - exec - Function hypre_ParMatmul.omp

	Function: hypre_ParMatmul.omp_outlined.7	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage (incl. loops): 0.91% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x484930 SUB	SP, SP, #320

0x484934 STP	X29, X30, [SP, #224]

0x484938 STP	X28, X27, [SP, #240]

0x48493c STP	X26, X25, [SP, #256]

0x484940 STP	X24, X23, [SP, #272]

0x484944 STP	X22, X21, [SP, #288]

0x484948 STP	X20, X19, [SP, #304]

0x48494c ADD	X29, SP, #224

0x484950 LDP	X8, X9, [X29, #288]

0x484954 STUR	X7, [X29, #424]

0x484958 STUR	X4, [X29, #480]

0x48495c ORR	X19, XZR, X6

0x484960 ORR	X20, XZR, X5

0x484964 ORR	X22, XZR, X3

0x484968 ORR	X26, XZR, X2

0x48496c STUR	X9, [X29, #456]

0x484970 STR	X8, [SP, #88]

0x484974 LDR	X8, [X29, #280]

0x484978 STR	X8, [SP, #80]

0x48497c LDR	X8, [X29, #272]

0x484980 STR	X8, [SP, #72]

0x484984 LDP	X8, X28, [X29, #256]

0x484988 STUR	X8, [X29, #464]

0x48498c LDR	X8, [X29, #248]

0x484990 STR	X8, [SP, #64]

0x484994 LDP	X27, X8, [X29, #232]

0x484998 STUR	X8, [X29, #472]

0x48499c LDP	X8, X24, [X29, #216]

0x4849a0 STR	X8, [SP, #40]

0x4849a4 LDP	X8, X9, [X29, #200]

0x4849a8 STUR	X9, [X29, #448]

0x4849ac STR	X8, [SP, #56]

0x4849b0 LDR	X8, [X29, #192]

0x4849b4 STR	X8, [SP, #32]

0x4849b8 LDP	X8, X9, [X29, #176]

0x4849bc STUR	X8, [X29, #440]

0x4849c0 LDP	X8, X10, [X29, #160]

0x4849c4 STP	X10, X9, [X29, #1000]

0x4849c8 STR	X8, [SP, #48]

0x4849cc LDR	X8, [X29, #152]

0x4849d0 STR	X8, [SP, #24]

0x4849d4 LDR	X8, [X29, #144]

0x4849d8 STR	X8, [SP, #16]

0x4849dc LDR	X8, [X29, #136]

0x4849e0 STR	X8, [SP, #8]

0x4849e4 LDR	X8, [X29, #128]

0x4849e8 STR	X8, [SP, #96]

0x4849ec LDP	X21, X9, [X29, #112]

0x4849f0 LDP	X25, X8, [X29, #96]

0x4849f4 STP	X8, X9, [X29, #920]

0x4849f8 BL	4aae50

0x4849fc ORR	X23, XZR, X0

0x484a00 BL	4aae30

0x484a04 LDR	X8, [X26]

0x484a08 ADD	X10, X23, #1

0x484a0c ORR	X13, XZR, X19

0x484a10 SDIV	X9, X8, X0

0x484a14 MSUB	X8, X9, X0, X8

0x484a18 MADD	X11, X9, X23, X8

0x484a1c CMP	X23, X8

0x484a20 MADD	X8, X9, X10, X8

0x484a24 ADD	X9, X9, #1

0x484a28 MADD	X12, X9, X23, XZR

0x484a2c MADD	X9, X10, X9, XZR

0x484a30 CSEL	X8, X8, X9, #10

0x484a34 CSEL	X26, X11, X12, #10

0x484a38 LDR	X9, [X19]

0x484a3c STUR	X8, [X29, #432]

0x484a40 LDR	X8, [X22]

0x484a44 LDR	X22, [X8, X26,LSL #3]

0x484a48 LDUR	X8, [X29, #480]

0x484a4c LDR	X8, [X8]

0x484a50 LDR	X19, [X8, X26,LSL #3]

0x484a54 LDR	X8, [X20]

0x484a58 ORR	X10, X8, X9

0x484a5c CBNZ	X10, 484a78

0x484a60 LDUR	X9, [X29, #472]

0x484a64 ORR	X0, XZR, XZR

0x484a68 LDUR	X8, [X29, #432]

0x484a6c CMP	X26, X8

0x484a70 B.LT	484adc

0x484a74 B	484e90

0x484a78 STUR	X24, [X29, #480]

0x484a7c LDUR	X24, [X29, #472]

0x484a80 ADD	X0, X9, X8

0x484a84 MOVZ	W1, #8

0x484a88 ORR	X23, XZR, X13

0x484a8c BL	4a90d0

0x484a90 LDR	X8, [X20]

0x484a94 LDR	X9, [X23]

0x484a98 ADD	X8, X9, X8

0x484a9c CMP	X8, #1

0x484aa0 B.LT	484ac8

0x484aa4 MOVN	X9, #0

0x484aa8 ORR	X8, XZR, XZR

(2839) 0x484aac STR	X9, [X0, X8,LSL #3]

(2839) 0x484ab0 ADD	X8, X8, #1

(2839) 0x484ab4 LDR	X10, [X20]

(2839) 0x484ab8 LDR	X11, [X23]

(2839) 0x484abc ADD	X10, X11, X10

(2839) 0x484ac0 CMP	X8, X10

(2839) 0x484ac4 B.LT	484aac

0x484ac8 ORR	X9, XZR, X24

0x484acc LDUR	X24, [X29, #480]

0x484ad0 LDUR	X8, [X29, #432]

0x484ad4 CMP	X26, X8

0x484ad8 B.GE	484e90

0x484adc LDR	X10, [X25]

0x484ae0 LDR	X8, [X21]

0x484ae4 LDR	X16, [X24]

0x484ae8 ORR	X1, XZR, X22

0x484aec LDR	X17, [X27]

0x484af0 LDR	X18, [X9]

0x484af4 STP	X8, X10, [SP, #104]

0x484af8 LDR	X8, [SP, #96]

0x484afc LDR	X8, [X8]

0x484b00 STR	X8, [SP, #96]

0x484b04 LDR	X8, [SP, #8]

0x484b08 LDR	X8, [X8]

0x484b0c STUR	X8, [X29, #480]

0x484b10 LDR	X8, [SP, #16]

0x484b14 LDR	X8, [X8]

0x484b18 STUR	X8, [X29, #472]

0x484b1c LDP	X10, X8, [SP, #24]

0x484b20 LDR	X14, [X8]

0x484b24 LDR	X8, [SP, #40]

0x484b28 LDR	X13, [X10]

0x484b2c LDR	X15, [X8]

0x484b30 B	484b54

0x484b34 HINT	#0

0x484b38 HINT	#0

0x484b3c HINT	#0

  (2832) 0x484b40 LDUR	X8, [X29, #432]

  (2832) 0x484b44 ORR	X19, XZR, X2

  (2832) 0x484b48 ORR	X22, XZR, X1

  (2832) 0x484b4c CMP	X26, X8

  (2832) 0x484b50 B.GE	484e90

  (2832) 0x484b54 LDUR	X8, [X29, #424]

  (2832) 0x484b58 LDR	X8, [X8]

  (2832) 0x484b5c CBZ	X8, 484b7c

  (2832) 0x484b60 LDUR	X8, [X29, #408]

  (2832) 0x484b64 ADD	X1, X22, #1

  (2832) 0x484b68 STR	X22, [X0, X26,LSL #3]

  (2832) 0x484b6c LDR	D0, [X8]

  (2832) 0x484b70 LDP	X8, X9, [SP, #104]

  (2832) 0x484b74 STR	X26, [X8, X22,LSL #3]

  (2832) 0x484b78 STR	D0, [X9, X22,LSL #3]

  (2832) 0x484b7c LDUR	X8, [X29, #416]

  (2832) 0x484b80 LDR	X8, [X8]

  (2832) 0x484b84 CBZ	X8, 484d00

  (2832) 0x484b88 LDR	X8, [SP, #96]

  (2832) 0x484b8c ADD	X3, X8, X26,LSL #3

  (2832) 0x484b90 LDP	X4, X8, [X3]

  (2832) 0x484b94 CMP	X4, X8

  (2832) 0x484b98 B.GE	484d20

  (2832) 0x484b9c LDP	X9, X8, [SP, #48]

  (2832) 0x484ba0 ORR	X2, XZR, X19

  (2832) 0x484ba4 LDR	X5, [X9]

  (2832) 0x484ba8 LDR	X6, [X8]

  (2832) 0x484bac B	484bd0

0x484bb0 HINT	#0

0x484bb4 HINT	#0

0x484bb8 HINT	#0

0x484bbc HINT	#0

    (2836) 0x484bc0 LDR	X8, [X3, #8]

    (2836) 0x484bc4 ADD	X4, X4, #1

    (2836) 0x484bc8 CMP	X4, X8

    (2836) 0x484bcc B.GE	484d04

    (2836) 0x484bd0 LDP	X8, X9, [X29, #984]

    (2836) 0x484bd4 LDR	X30, [X9, X4,LSL #3]

    (2836) 0x484bd8 LDR	D0, [X8, X4,LSL #3]

    (2836) 0x484bdc ADD	X7, X30, #1

    (2836) 0x484be0 LDR	X8, [X13, X30,LSL #3]

    (2836) 0x484be4 LDR	X23, [X13, X7,LSL #3]

    (2836) 0x484be8 CMP	X8, X23

    (2836) 0x484bec B.GE	484c6c

    (2836) 0x484bf0 LDUR	X9, [X29, #440]

    (2836) 0x484bf4 LDP	X10, X11, [X29, #1000]

    (2836) 0x484bf8 LDR	X9, [X9]

    (2836) 0x484bfc LDR	X10, [X10]

    (2836) 0x484c00 LDR	X27, [X11]

    (2836) 0x484c04 B	484c24

      (2838) 0x484c08 LDR	D1, [X9, X8,LSL #3]

      (2838) 0x484c0c LDR	D2, [X10, X11,LSL #3]

      (2838) 0x484c10 FMADD	D1, D0, D1, D2

      (2838) 0x484c14 STR	D1, [X10, X11,LSL #3]

      (2838) 0x484c18 ADD	X8, X8, #1

      (2838) 0x484c1c CMP	X8, X23

      (2838) 0x484c20 B.GE	484c6c

      (2838) 0x484c24 LDR	X11, [X20]

      (2838) 0x484c28 LDR	X12, [X5, X8,LSL #3]

      (2838) 0x484c2c ADD	X24, X12, X11

      (2838) 0x484c30 LDR	X11, [X0, X24,LSL #3]

      (2838) 0x484c34 CMP	X11, X19

      (2838) 0x484c38 B.GE	484c08

      (2838) 0x484c3c STR	X2, [X0, X24,LSL #3]

      (2838) 0x484c40 LDR	D1, [X9, X8,LSL #3]

      (2838) 0x484c44 LDR	X11, [X20]

      (2838) 0x484c48 SUB	X11, X24, X11

      (2838) 0x484c4c STR	X11, [X27, X2,LSL #3]

      (2838) 0x484c50 FMUL	D1, D0, D1

      (2838) 0x484c54 LDR	X23, [X13, X7,LSL #3]

      (2838) 0x484c58 STR	D1, [X10, X2,LSL #3]

      (2838) 0x484c5c ADD	X2, X2, #1

      (2838) 0x484c60 ADD	X8, X8, #1

      (2838) 0x484c64 CMP	X8, X23

      (2838) 0x484c68 B.LT	484c24

    (2836) 0x484c6c LDR	X8, [X14, X30,LSL #3]

    (2836) 0x484c70 LDR	X23, [X14, X7,LSL #3]

    (2836) 0x484c74 CMP	X8, X23

    (2836) 0x484c78 B.GE	484bc0

    (2836) 0x484c7c LDUR	X9, [X29, #448]

    (2836) 0x484c80 LDR	X10, [X25]

    (2836) 0x484c84 LDR	X27, [X21]

    (2836) 0x484c88 LDR	X9, [X9]

    (2836) 0x484c8c B	484cbc

0x484c90 HINT	#0

0x484c94 HINT	#0

0x484c98 HINT	#0

0x484c9c HINT	#0

      (2837) 0x484ca0 LDR	D1, [X9, X8,LSL #3]

      (2837) 0x484ca4 LDR	D2, [X10, X11,LSL #3]

      (2837) 0x484ca8 FMADD	D1, D0, D1, D2

      (2837) 0x484cac STR	D1, [X10, X11,LSL #3]

      (2837) 0x484cb0 ADD	X8, X8, #1

      (2837) 0x484cb4 CMP	X8, X23

      (2837) 0x484cb8 B.GE	484bc0

      (2837) 0x484cbc LDR	X24, [X6, X8,LSL #3]

      (2837) 0x484cc0 LDR	X11, [X0, X24,LSL #3]

      (2837) 0x484cc4 CMP	X11, X22

      (2837) 0x484cc8 B.GE	484ca0

      (2837) 0x484ccc LDR	D1, [X9, X8,LSL #3]

      (2837) 0x484cd0 STR	X1, [X0, X24,LSL #3]

      (2837) 0x484cd4 STR	X24, [X27, X1,LSL #3]

      (2837) 0x484cd8 LDR	X23, [X14, X7,LSL #3]

      (2837) 0x484cdc FMUL	D1, D0, D1

      (2837) 0x484ce0 STR	D1, [X10, X1,LSL #3]

      (2837) 0x484ce4 ADD	X1, X1, #1

      (2837) 0x484ce8 ADD	X8, X8, #1

      (2837) 0x484cec CMP	X8, X23

      (2837) 0x484cf0 B.LT	484cbc

    (2836) 0x484cf4 B	484bc0

0x484cf8 HINT	#0

0x484cfc HINT	#0

  (2832) 0x484d00 ORR	X2, XZR, X19

  (2832) 0x484d04 LDR	X3, [X15, X26,LSL #3]

  (2832) 0x484d08 ADD	X26, X26, #1

  (2832) 0x484d0c LDR	X8, [X15, X26,LSL #3]

  (2832) 0x484d10 CMP	X3, X8

  (2832) 0x484d14 B.GE	484b40

(2833) 0x484d18 B	484d38

0x484d1c HINT	#0

  (2832) 0x484d20 ORR	X2, XZR, X19

  (2832) 0x484d24 LDR	X3, [X15, X26,LSL #3]

  (2832) 0x484d28 ADD	X26, X26, #1

  (2832) 0x484d2c LDR	X8, [X15, X26,LSL #3]

  (2832) 0x484d30 CMP	X3, X8

  (2832) 0x484d34 B.GE	484b40

(2833) 0x484d38 LDP	X9, X8, [SP, #64]

(2833) 0x484d3c LDR	X4, [X9]

(2833) 0x484d40 LDR	X5, [X8]

(2833) 0x484d44 LDP	X9, X8, [SP, #80]

(2833) 0x484d48 LDR	X6, [X9]

(2833) 0x484d4c LDR	X7, [X8]

(2833) 0x484d50 B	484d70

0x484d54 HINT	#0

0x484d58 HINT	#0

0x484d5c HINT	#0

(2833) 0x484d60 LDR	X8, [X15, X26,LSL #3]

(2833) 0x484d64 ADD	X3, X3, #1

(2833) 0x484d68 CMP	X3, X8

(2833) 0x484d6c B.GE	484b40

(2833) 0x484d70 LDR	X8, [X16, X3,LSL #3]

(2833) 0x484d74 LDR	D0, [X17, X3,LSL #3]

(2833) 0x484d78 ADD	X30, X8, #1

(2833) 0x484d7c LDR	X9, [X18, X8,LSL #3]

(2833) 0x484d80 LDR	X27, [X18, X30,LSL #3]

(2833) 0x484d84 CMP	X9, X27

(2833) 0x484d88 B.GE	484df4

(2833) 0x484d8c LDUR	X10, [X29, #464]

(2833) 0x484d90 LDR	X23, [X25]

(2833) 0x484d94 LDR	X24, [X21]

(2833) 0x484d98 LDR	X10, [X10]

(2833) 0x484d9c B	484dbc

  (2835) 0x484da0 LDR	D1, [X10, X9,LSL #3]

  (2835) 0x484da4 LDR	D2, [X23, X12,LSL #3]

  (2835) 0x484da8 FMADD	D1, D0, D1, D2

  (2835) 0x484dac STR	D1, [X23, X12,LSL #3]

  (2835) 0x484db0 ADD	X9, X9, #1

  (2835) 0x484db4 CMP	X9, X27

  (2835) 0x484db8 B.GE	484df4

  (2835) 0x484dbc LDR	X11, [X4, X9,LSL #3]

  (2835) 0x484dc0 LDR	X12, [X0, X11,LSL #3]

  (2835) 0x484dc4 CMP	X12, X22

  (2835) 0x484dc8 B.GE	484da0

  (2835) 0x484dcc LDR	D1, [X10, X9,LSL #3]

  (2835) 0x484dd0 STR	X1, [X0, X11,LSL #3]

  (2835) 0x484dd4 STR	X11, [X24, X1,LSL #3]

  (2835) 0x484dd8 LDR	X27, [X18, X30,LSL #3]

  (2835) 0x484ddc FMUL	D1, D0, D1

  (2835) 0x484de0 STR	D1, [X23, X1,LSL #3]

  (2835) 0x484de4 ADD	X1, X1, #1

  (2835) 0x484de8 ADD	X9, X9, #1

  (2835) 0x484dec CMP	X9, X27

  (2835) 0x484df0 B.LT	484dbc

(2833) 0x484df4 LDR	X9, [X28]

(2833) 0x484df8 CBZ	X9, 484d60

(2833) 0x484dfc LDR	X8, [X5, X8,LSL #3]

(2833) 0x484e00 LDR	X23, [X5, X30,LSL #3]

(2833) 0x484e04 CMP	X8, X23

(2833) 0x484e08 B.GE	484d60

(2833) 0x484e0c LDUR	X9, [X29, #456]

(2833) 0x484e10 LDP	X10, X11, [X29, #1000]

(2833) 0x484e14 LDR	X9, [X9]

(2833) 0x484e18 LDR	X10, [X10]

(2833) 0x484e1c LDR	X27, [X11]

(2833) 0x484e20 B	484e40

  (2834) 0x484e24 LDR	D1, [X9, X8,LSL #3]

  (2834) 0x484e28 LDR	D2, [X10, X11,LSL #3]

  (2834) 0x484e2c FMADD	D1, D0, D1, D2

  (2834) 0x484e30 STR	D1, [X10, X11,LSL #3]

  (2834) 0x484e34 ADD	X8, X8, #1

  (2834) 0x484e38 CMP	X8, X23

  (2834) 0x484e3c B.GE	484d60

  (2834) 0x484e40 LDR	X12, [X7, X8,LSL #3]

  (2834) 0x484e44 LDR	X11, [X20]

  (2834) 0x484e48 LDR	X12, [X6, X12,LSL #3]

  (2834) 0x484e4c ADD	X24, X12, X11

  (2834) 0x484e50 LDR	X11, [X0, X24,LSL #3]

  (2834) 0x484e54 CMP	X11, X19

  (2834) 0x484e58 B.GE	484e24

  (2834) 0x484e5c STR	X2, [X0, X24,LSL #3]

  (2834) 0x484e60 LDR	D1, [X9, X8,LSL #3]

  (2834) 0x484e64 LDR	X11, [X20]

  (2834) 0x484e68 SUB	X11, X24, X11

  (2834) 0x484e6c STR	X11, [X27, X2,LSL #3]

  (2834) 0x484e70 FMUL	D1, D0, D1

  (2834) 0x484e74 LDR	X23, [X5, X30,LSL #3]

  (2834) 0x484e78 STR	D1, [X10, X2,LSL #3]

  (2834) 0x484e7c ADD	X2, X2, #1

  (2834) 0x484e80 ADD	X8, X8, #1

  (2834) 0x484e84 CMP	X8, X23

  (2834) 0x484e88 B.LT	484e40

(2833) 0x484e8c B	484d60

0x484e90 LDP	X20, X19, [SP, #304]

0x484e94 LDP	X22, X21, [SP, #288]

0x484e98 LDP	X24, X23, [SP, #272]

0x484e9c LDP	X26, X25, [SP, #256]

0x484ea0 LDP	X28, X27, [SP, #240]

0x484ea4 LDP	X29, X30, [SP, #224]

0x484ea8 ADD	SP, SP, #320

0x484eac B	4a91d0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 29.17 to 24.00 cycles (1.22x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.17 to 1.50 cycles (19.44x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 560 bytes. The binary function is storing 336 bytes.

General properties

nb instructions	147
loop length	588
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.00	5.00	6.00	6.08	6.00	6.00	6.00	5.92	0.00	0.00	0.00	0.00	29.17	28.83	29.00	16.50	16.50
cycles	5.00	5.00	6.00	6.08	6.00	6.00	6.00	5.92	0.00	0.00	0.00	0.00	29.17	28.83	29.00	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	16.25
Overall L1	29.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.17 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.52 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 484930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X24, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X10, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X9, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X8, X9, X0, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X11, X9, X23, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X23, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
MADD X8, X9, X10, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X9, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X9, X10, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CSEL X8, X8, X9, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X26, X11, X12, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X10, 484a78 <hypre_ParMatmul.omp_outlined.7+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 484adc <hypre_ParMatmul.omp_outlined.7+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 484e90 <hypre_ParMatmul.omp_outlined.7+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X24, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X23, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 484ac8 <hypre_ParMatmul.omp_outlined.7+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 484e90 <hypre_ParMatmul.omp_outlined.7+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X1, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X17, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X8, X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 484b54 <hypre_ParMatmul.omp_outlined.7+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a91d0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 29.17 to 1.50 cycles (19.44x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 560 bytes. The binary function is storing 336 bytes.

General properties

nb instructions	147
loop length	588
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.00	5.00	6.00	6.08	6.00	6.00	6.00	5.92	0.00	0.00	0.00	0.00	29.17	28.83	29.00	16.50	16.50
cycles	5.00	5.00	6.00	6.08	6.00	6.00	6.00	5.92	0.00	0.00	0.00	0.00	29.17	28.83	29.00	16.50	16.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	16.25
Overall L1	29.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 29.17 cycles. At this rate:

20% of peak load performance is reached (19.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.52 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 484930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X4, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X19, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X28, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X24, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X10, X9, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X23, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X13, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SDIV X9, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MSUB X8, X9, X0, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MADD X11, X9, X23, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CMP X23, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
MADD X8, X9, X10, X8	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X9, X23, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X9, X10, X9, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CSEL X8, X8, X9, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X26, X11, X12, #10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X10, X8, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBNZ X10, 484a78 <hypre_ParMatmul.omp_outlined.7+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 484adc <hypre_ParMatmul.omp_outlined.7+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 484e90 <hypre_ParMatmul.omp_outlined.7+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X24, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X23, XZR, X13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X9, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 484ac8 <hypre_ParMatmul.omp_outlined.7+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDUR X24, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X26, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 484e90 <hypre_ParMatmul.omp_outlined.7+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X1, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X17, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X8, X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 484b54 <hypre_ParMatmul.omp_outlined.7+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #320	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a91d0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul.omp_outlined.7–	0.91	0.17
▼Loop 2833 - par_csr_matop.c:865-989 - exec–	0.26	0.04
○Loop 2835 - par_csr_matop.c:946-965 - exec	0.63	0.10
▼Loop 2832 - par_csr_matop.c:865-937 - exec–	0.01	0.01
▼Loop 2836 - par_csr_matop.c:888-928 - exec–	0.00	0.00
○Loop 2838 - par_csr_matop.c:897-915 - exec	0.00	0.00
○Loop 2837 - par_csr_matop.c:917-928 - exec	0.00	0.00
○Loop 2834 - par_csr_matop.c:970-989 - exec	0.00	0.00
○Loop 2839 - par_csr_matop.c:858-859 - exec	0.01	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code