OV - exec - Function hypre_BoomerAMGCreate2ndS.omp

	Function: hypre_BoomerAMGCreate2ndS.omp_outlined.16	Module: exec	Source: par_strength.c:1668-2230 [...]	Coverage (incl. loops): 1.82% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1668 - 2230

--------------------------------------------------------------------------------

1668: #pragma omp parallel private(i1,i2,i3,jj1,jj2,index)

1669: #endif

1670:    {

1671:       HYPRE_Int my_thread_num = hypre_GetThreadNum();

1672:

1673:       HYPRE_Int i1_begin, i1_end;

1674:       hypre_GetSimpleThreadPartition(&i1_begin, &i1_end, num_cols_diag_S);

1675:

1676:       HYPRE_Int *C_temp_diag_j = NULL, *C_temp_offd_j = NULL;

1677:       HYPRE_Int *C_temp_diag_data = NULL, *C_temp_offd_data = NULL;

1678:

1679:       if (num_paths > 1)

1680:       {

1681:          C_temp_diag_j = C_temp_diag_j_array + num_coarse*my_thread_num;

1682:          C_temp_offd_j = C_temp_offd_j_array + num_cols_offd_C*my_thread_num;

1683:

1684:          C_temp_diag_data = C_temp_diag_data_array + num_coarse*my_thread_num;

1685:          C_temp_offd_data = C_temp_offd_data_array + num_cols_offd_C*my_thread_num;

1686:       }

1687:

1688:       HYPRE_Int *S_marker = NULL, *S_marker_offd = NULL;

1689:       if (num_coarse) S_marker = S_marker_array + num_coarse*my_thread_num;

1690:       if (num_cols_offd_C) S_marker_offd = S_marker_offd_array + num_cols_offd_C*my_thread_num;

1691:       for (i1 = 0; i1 < num_coarse; i1++)

1692:       {

1693:          S_marker[i1] = -1;

1694:       }

1695:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1696:       {

1697:          S_marker_offd[i1] = -1;

[...]

1705:       HYPRE_Int num_nonzeros_diag = 0;

1706:       HYPRE_Int num_nonzeros_offd = 0;

1707:

1708:       HYPRE_Int ic_begin = num_coarse_prefix_sum[my_thread_num];

1709:       HYPRE_Int ic_end = num_coarse_prefix_sum[my_thread_num + 1];

1710:       HYPRE_Int ic;

1711:

1712:       if (num_paths == 1)

1713:       {

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1771:              {

1772:                  i2 = S_offd_j[jj1];

1773:                  if (CF_marker_offd[i2] > 0)

1774:                  {

1775:                     index = map_S_to_C[i2];

1776:                     if (S_marker_offd[index] < jj_row_begin_offd)

1777:                     {

1778:                        S_marker_offd[index] = num_nonzeros_offd;

1779:                        num_nonzeros_offd++;

1780:                     }

1781:                  }

1782:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1783:                  {

1784:                     i3 = S_ext_diag_j[jj2];

1785:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

1786:                     {

1787:                        S_marker[i3] = num_nonzeros_diag;

1788:                        num_nonzeros_diag++;

1789:                     }

1790:                  }

1791:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1792:                  {

1793:                     i3 = S_ext_offd_j[jj2];

1794:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1795:                     {

1796:                        S_marker_offd[i3] = num_nonzeros_offd;

1797:                        num_nonzeros_offd++;

[...]

1806:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1812:              HYPRE_Int i1 = coarse_to_fine[ic];

1813:

1814:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

1815:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

1816:

1817:              C_diag_i[ic] = num_nonzeros_diag;

1818:              if (num_cols_offd_C)

1819:              {

1820:                 C_offd_i[ic] = num_nonzeros_offd;

1821:              }

1822:

1823:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1824:              {

1825:                  i2 = S_diag_j[jj1];

1826:                  if (CF_marker[i2] > 0)

1827:                  {

1828:                     index = fine_to_coarse[i2];

1829:                     if (S_marker[index] < jj_row_begin_diag)

1830:                     {

1831:                        S_marker[index] = jj_count_diag;

1832:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

1833:                        jj_count_diag++;

1834:                     }

1835:                     else

1836:                     {

1837:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

1838:                     }

1839:                  }

1840:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1841:                  {

1842:                     i3 = S_diag_j[jj2];

1843:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

1844:                     {

1845:                        index = fine_to_coarse[i3];

1846:                        if (S_marker[index] < jj_row_begin_diag)

1847:                        {

1848:                           S_marker[index] = jj_count_diag;

1849:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1850:                           jj_count_diag++;

1851:                        }

1852:                        else

1853:                        {

1854:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

1855:                        }

1856:                     }

1857:                  }

1858:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1859:                  {

1860:                     i3 = S_offd_j[jj2];

1861:                     if (CF_marker_offd[i3] > 0)

1862:                     {

1863:                        index = map_S_to_C[i3];

1864:                        if (S_marker_offd[index] < jj_row_begin_offd)

1865:                        {

1866:                           S_marker_offd[index] = jj_count_offd;

1867:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1868:                           jj_count_offd++;

1869:                        }

1870:                        else

1871:                        {

1872:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

1873:                        }

1874:                     }

1875:                  }

1876:              }

1877:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1878:              {

1879:                  i2 = S_offd_j[jj1];

1880:                  if (CF_marker_offd[i2] > 0)

1881:                  {

1882:                     index = map_S_to_C[i2];

1883:                     if (S_marker_offd[index] < jj_row_begin_offd)

1884:                     {

1885:                        S_marker_offd[index] = jj_count_offd;

1886:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

1887:                        jj_count_offd++;

1888:                     }

1889:                     else

1890:                     {

1891:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

1892:                     }

1893:                  }

1894:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1895:                  {

1896:                     i3 = S_ext_diag_j[jj2];

1897:                     if (i3 != ic)

1898:                     {

1899:                        if (S_marker[i3] < jj_row_begin_diag)

1900:                        {

1901:                           S_marker[i3] = jj_count_diag;

1902:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1903:                           jj_count_diag++;

1904:                        }

1905:                        else

1906:                        {

1907:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

1908:                        }

1909:                     }

1910:                  }

1911:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1912:                  {

1913:                     i3 = S_ext_offd_j[jj2];

1914:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1915:                     {

1916:                        S_marker_offd[i3] = jj_count_offd;

1917:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1918:                        jj_count_offd++;

1919:                     }

1920:                     else

1921:                     {

1922:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

1923:                     }

1924:                  }

1925:              }

1926:

1927:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

1928:              {

1929:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

1930:                  {

1931:                     ++num_nonzeros_diag;

1932:                  }

1933:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

1934:              }

1935:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

1936:              {

1937:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

1938:                  {

1939:                     ++num_nonzeros_offd;

1940:                  }

1941:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

1942:              }

1943:          } /* for each row */

1944:       } /* num_paths > 1 */

1945:

1946:       hypre_prefix_sum_pair(

1947:          &num_nonzeros_diag, &C_diag_i[num_coarse],

1948:          &num_nonzeros_offd, &C_offd_i[num_coarse],

1949:          prefix_sum_workspace);

1950:

1951:       for (i1 = 0; i1 < num_coarse; i1++)

1952:       {

1953:          S_marker[i1] = -1;

1954:       }

1955:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1956:       {

1957:          S_marker_offd[i1] = -1;

1958:       }

1959:

1960: #ifdef HYPRE_USING_OPENMP

1961: #pragma omp barrier

1962: #pragma omp master

1963: #endif

1964:       {

1965:          if (C_diag_i[num_coarse])

1966:          {

1967:             C_diag_j = hypre_TAlloc(HYPRE_Int, C_diag_i[num_coarse]);

1968:          }

1969:          if (C_offd_i[num_coarse])

1970:          {

1971:             C_offd_j = hypre_TAlloc(HYPRE_Int, C_offd_i[num_coarse]);

1972:          }

1973:       }

1974: #ifdef HYPRE_USING_OPENMP

1975: #pragma omp barrier

1976: #endif

1977:

1978:       for (ic = ic_begin; ic < ic_end - 1; ic++)

1979:       {

1980:          if (C_diag_i[ic+1] == C_diag_i[ic] && C_offd_i[ic+1] == C_offd_i[ic])

1981:             CF_marker[coarse_to_fine[ic]] = 2;

1982:

1983:          C_diag_i[ic] += num_nonzeros_diag;

1984:          C_offd_i[ic] += num_nonzeros_offd;

1985:       }

1986:       if (ic_begin < ic_end)

1987:       {

1988:          C_diag_i[ic] += num_nonzeros_diag;

1989:          C_offd_i[ic] += num_nonzeros_offd;

1990:

1991:          HYPRE_Int next_C_diag_i = prefix_sum_workspace[2*(my_thread_num + 1)];

1992:          HYPRE_Int next_C_offd_i = prefix_sum_workspace[2*(my_thread_num + 1) + 1];

1993:

1994:          if (next_C_diag_i == C_diag_i[ic] && next_C_offd_i == C_offd_i[ic])

1995:             CF_marker[coarse_to_fine[ic]] = 2;

1996:       }

1997:

1998:       if (num_paths == 1)

1999:       {

2000:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2006:              HYPRE_Int i1 = coarse_to_fine[ic];

2007:

2008:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

2009:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

2010:

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

2049:                        }

2050:                     }

2051:                  }

2052:              }

2053:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2054:              {

2055:                  i2 = S_offd_j[jj1];

2056:                  if (CF_marker_offd[i2] > 0)

2057:                  {

2058:                     index = map_S_to_C[i2];

2059:                     if (S_marker_offd[index] < jj_row_begin_offd)

2060:                     {

2061:                        S_marker_offd[index] = num_nonzeros_offd;

2062:                        C_offd_j[num_nonzeros_offd] = index;

2063:                        num_nonzeros_offd++;

2064:                     }

2065:                  }

2066:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2067:                  {

2068:                     i3 = S_ext_diag_j[jj2];

2069:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

2070:                     {

2071:                        S_marker[i3] = num_nonzeros_diag;

2072:                        C_diag_j[num_nonzeros_diag] = i3;

2073:                        num_nonzeros_diag++;

2074:                     }

2075:                  }

2076:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2077:                  {

2078:                     i3 = S_ext_offd_j[jj2];

2079:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2080:                     {

2081:                        S_marker_offd[i3] = num_nonzeros_offd;

2082:                        C_offd_j[num_nonzeros_offd] = i3;

2083:                        num_nonzeros_offd++;

[...]

2093:          jj_count_offd = num_nonzeros_offd;

2094:

2095:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2101:              HYPRE_Int i1 = coarse_to_fine[ic];

2102:

2103:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

2104:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

2105:

2106:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2107:              {

2108:                  i2 = S_diag_j[jj1];

2109:                  if (CF_marker[i2] > 0)

2110:                  {

2111:                     index = fine_to_coarse[i2];

2112:                     if (S_marker[index] < jj_row_begin_diag)

2113:                     {

2114:                        S_marker[index] = jj_count_diag;

2115:                        C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2116:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

2117:                        jj_count_diag++;

2118:                     }

2119:                     else

2120:                     {

2121:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

2122:                     }

2123:                  }

2124:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2125:                  {

2126:                     i3 = S_diag_j[jj2];

2127:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

2128:                     {

2129:                        index = fine_to_coarse[i3];

2130:                        if (S_marker[index] < jj_row_begin_diag)

2131:                        {

2132:                           S_marker[index] = jj_count_diag;

2133:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2134:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2135:                           jj_count_diag++;

2136:                        }

2137:                        else

2138:                        {

2139:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

2140:                        }

2141:                     }

2142:                  }

2143:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2144:                  {

2145:                     i3 = S_offd_j[jj2];

2146:                     if (CF_marker_offd[i3] > 0)

2147:                     {

2148:                        index = map_S_to_C[i3];

2149:                        if (S_marker_offd[index] < jj_row_begin_offd)

2150:                        {

2151:                           S_marker_offd[index] = jj_count_offd;

2152:                           C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2153:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2154:                           jj_count_offd++;

2155:                        }

2156:                        else

2157:                        {

2158:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

2159:                        }

2160:                     }

2161:                  }

2162:              }

2163:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2164:              {

2165:                  i2 = S_offd_j[jj1];

2166:                  if (CF_marker_offd[i2] > 0)

2167:                  {

2168:                     index = map_S_to_C[i2];

2169:                     if (S_marker_offd[index] < jj_row_begin_offd)

2170:                     {

2171:                        S_marker_offd[index] = jj_count_offd;

2172:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2173:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

2174:                        jj_count_offd++;

2175:                     }

2176:                     else

2177:                     {

2178:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

2179:                     }

2180:                  }

2181:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2182:                  {

2183:                     i3 = S_ext_diag_j[jj2];

2184:                     if (i3 != ic)

2185:                     {

2186:                        if (S_marker[i3] < jj_row_begin_diag)

2187:                        {

2188:                           S_marker[i3] = jj_count_diag;

2189:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = i3;

2190:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2191:                           jj_count_diag++;

2192:                        }

2193:                        else

2194:                        {

2195:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

2196:                        }

2197:                     }

2198:                  }

2199:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2200:                  {

2201:                     i3 = S_ext_offd_j[jj2];

2202:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2203:                     {

2204:                        S_marker_offd[i3] = jj_count_offd;

2205:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = i3;

2206:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2207:                        jj_count_offd++;

2208:                     }

2209:                     else

2210:                     {

2211:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

2212:                     }

2213:                  }

2214:              }

2215:

2216:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

2217:              {

2218:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

2219:                  {

2220:                     C_diag_j[num_nonzeros_diag++] = C_temp_diag_j[jj1 - jj_row_begin_diag];

2221:                  }

2222:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

2223:              }

2224:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

2225:              {

2226:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

2227:                  {

2228:                     C_offd_j[num_nonzeros_offd++] = C_temp_offd_j[jj1 - jj_row_begin_offd];

2229:                  }

2230:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

0x467cb0 SUB	SP, SP, #384

0x467cb4 STP	X29, X30, [SP, #288]

0x467cb8 STP	X28, X27, [SP, #304]

0x467cbc STP	X26, X25, [SP, #320]

0x467cc0 STP	X24, X23, [SP, #336]

0x467cc4 STP	X22, X21, [SP, #352]

0x467cc8 STP	X20, X19, [SP, #368]

0x467ccc ADD	X29, SP, #288

0x467cd0 LDP	X27, X22, [X29, #112]

0x467cd4 ORR	X21, XZR, X7

0x467cd8 ORR	X24, XZR, X6

0x467cdc ORR	X20, XZR, X5

0x467ce0 ORR	X25, XZR, X4

0x467ce4 ORR	X19, XZR, X3

0x467ce8 ORR	X26, XZR, X2

0x467cec STR	X0, [SP, #56]

0x467cf0 BL	4aae50

0x467cf4 LDR	X2, [X26]

0x467cf8 ORR	X28, XZR, X0

0x467cfc SUB	X0, X29, #16

0x467d00 SUB	X1, X29, #24

0x467d04 BL	4aae70

0x467d08 LDR	X10, [X20]

0x467d0c LDR	X8, [X19]

0x467d10 LDR	X9, [X21]

0x467d14 ORR	X15, XZR, X20

0x467d18 MADD	X11, X10, X28, XZR

0x467d1c STUR	X21, [X29, #416]

0x467d20 CMP	X8, #1

0x467d24 B.LE	467d54

0x467d28 LDP	X13, X8, [X29, #96]

0x467d2c LDR	X12, [X25]

0x467d30 LDR	X14, [X24]

0x467d34 ADD	X26, X12, X11,LSL #3

0x467d38 LDR	X13, [X13]

0x467d3c LDR	X8, [X8]

0x467d40 MADD	X12, X9, X28, XZR

0x467d44 ADD	X23, X14, X12,LSL #3

0x467d48 ADD	X20, X13, X11,LSL #3

0x467d4c ADD	X21, X8, X12,LSL #3

0x467d50 B	467d68

0x467d54 ORR	X21, XZR, XZR

0x467d58 ORR	X20, XZR, XZR

0x467d5c ORR	X23, XZR, XZR

0x467d60 ORR	X26, XZR, XZR

0x467d64 MADD	X12, X9, X28, XZR

0x467d68 LDR	X13, [X27]

0x467d6c CMP	X10, #0

0x467d70 LDR	X14, [X29, #144]

0x467d74 LDR	X8, [X29, #128]

0x467d78 ADD	X11, X13, X11,LSL #3

0x467d7c CSEL	X24, XZR, X11, #0

0x467d80 LDR	X11, [X22]

0x467d84 CMP	X9, #0

0x467d88 ADD	X11, X11, X12,LSL #3

0x467d8c CSEL	X25, XZR, X11, #0

0x467d90 CMP	X10, #1

0x467d94 B.LT	467dc0

0x467d98 LDUR	X27, [X29, #416]

0x467d9c MOVN	X10, #0

0x467da0 ORR	X9, XZR, XZR

(2159) 0x467da4 STR	X10, [X24, X9,LSL #3]

(2159) 0x467da8 ADD	X9, X9, #1

(2159) 0x467dac LDR	X11, [X15]

(2159) 0x467db0 CMP	X9, X11

(2159) 0x467db4 B.LT	467da4

0x467db8 LDR	X9, [X27]

0x467dbc B	467dc4

0x467dc0 LDUR	X27, [X29, #416]

0x467dc4 LDR	X10, [X29, #256]

0x467dc8 STP	X10, X15, [SP, #96]

0x467dcc LDP	X10, X11, [X29, #240]

0x467dd0 STR	X10, [SP, #48]

0x467dd4 LDR	X10, [X29, #232]

0x467dd8 STUR	X11, [X29, #376]

0x467ddc STR	X10, [SP, #144]

0x467de0 LDR	X10, [X29, #224]

0x467de4 STR	X10, [SP, #40]

0x467de8 LDP	X10, X11, [X29, #208]

0x467dec STUR	X11, [X29, #464]

0x467df0 STUR	X10, [X29, #392]

0x467df4 LDP	X10, X11, [X29, #192]

0x467df8 STUR	X11, [X29, #384]

0x467dfc STR	X10, [SP, #32]

0x467e00 LDP	X10, X11, [X29, #176]

0x467e04 STR	X10, [SP, #88]

0x467e08 LDR	X10, [X29, #168]

0x467e0c STUR	X11, [X29, #456]

0x467e10 STR	X10, [SP, #24]

0x467e14 LDR	X10, [X29, #160]

0x467e18 STR	X10, [SP, #16]

0x467e1c LDR	X10, [X29, #152]

0x467e20 STR	X10, [SP, #120]

0x467e24 LDR	X10, [X29, #136]

0x467e28 STR	X10, [SP, #80]

0x467e2c CMP	X9, #1

0x467e30 B.LT	467e54

0x467e34 MOVN	X10, #0

0x467e38 ORR	X9, XZR, XZR

0x467e3c HINT	#0

(2158) 0x467e40 STR	X10, [X25, X9,LSL #3]

(2158) 0x467e44 ADD	X9, X9, #1

(2158) 0x467e48 LDR	X11, [X27]

(2158) 0x467e4c CMP	X9, X11

(2158) 0x467e50 B.LT	467e40

0x467e54 LDR	X8, [X8]

0x467e58 STP	XZR, XZR, [X29, #984]

0x467e5c ADD	X9, X28, #1

0x467e60 LDR	X10, [X14]

0x467e64 STUR	X19, [X29, #448]

0x467e68 STR	X14, [SP, #112]

0x467e6c STR	X9, [SP, #8]

0x467e70 LDR	X22, [X8, X28,LSL #3]

0x467e74 LDR	X9, [X8, X9,LSL #3]

0x467e78 LDR	X8, [X19]

0x467e7c STUR	X10, [X29, #408]

0x467e80 STUR	X9, [X29, #424]

0x467e84 CMP	X8, #1

0x467e88 B.NE	468180

0x467e8c CMP	X22, X9

0x467e90 B.GE	468730

0x467e94 LDR	X8, [SP, #80]

0x467e98 ORR	X18, XZR, X22

0x467e9c LDR	X8, [X8]

0x467ea0 STUR	X8, [X29, #432]

0x467ea4 LDR	X8, [SP, #120]

0x467ea8 LDR	X8, [X8]

0x467eac STUR	X8, [X29, #400]

0x467eb0 LDP	X9, X8, [SP, #16]

0x467eb4 LDR	X12, [X8]

0x467eb8 LDR	X8, [SP, #88]

0x467ebc LDR	X11, [X9]

0x467ec0 LDR	X13, [X8]

0x467ec4 LDR	X8, [SP, #32]

0x467ec8 LDR	X14, [X8]

0x467ecc LDP	X9, X8, [X29, #896]

0x467ed0 LDR	X15, [X9]

0x467ed4 LDR	X16, [X8]

0x467ed8 LDP	X9, X8, [SP, #40]

0x467edc LDR	X17, [X9]

0x467ee0 LDR	X0, [X8]

0x467ee4 B	467ef8

  (2151) 0x467ee8 LDP	X27, X8, [X29, #928]

  (2151) 0x467eec ADD	X18, X18, #1

  (2151) 0x467ef0 CMP	X18, X8

  (2151) 0x467ef4 B.EQ	468730

  (2151) 0x467ef8 LDUR	X8, [X29, #432]

  (2151) 0x467efc LDP	X2, X1, [X29, #984]

  (2151) 0x467f00 LDR	X10, [X8, X18,LSL #3]

  (2151) 0x467f04 LDUR	X8, [X29, #408]

  (2151) 0x467f08 STR	X1, [X8, X18,LSL #3]

  (2151) 0x467f0c LDR	X9, [X27]

  (2151) 0x467f10 CBZ	X9, 467f20

  (2151) 0x467f14 LDUR	X9, [X29, #472]

  (2151) 0x467f18 LDUR	X8, [X29, #400]

  (2151) 0x467f1c STR	X9, [X8, X18,LSL #3]

  (2151) 0x467f20 ADD	X3, X10, #1

  (2151) 0x467f24 LDR	X4, [X11, X10,LSL #3]

  (2151) 0x467f28 STUR	X10, [X29, #440]

  (2151) 0x467f2c LDR	X9, [X11, X3,LSL #3]

  (2151) 0x467f30 CMP	X4, X9

  (2151) 0x467f34 B.GE	46806c

  (2151) 0x467f38 LDUR	X8, [X29, #456]

  (2151) 0x467f3c LDR	X5, [X8]

  (2151) 0x467f40 LDP	X9, X8, [X29, #896]

  (2151) 0x467f44 LDR	X6, [X9]

  (2151) 0x467f48 LDR	X7, [X8]

  (2151) 0x467f4c B	467f70

0x467f50 HINT	#0

0x467f54 HINT	#0

0x467f58 HINT	#0

0x467f5c HINT	#0

    (2154) 0x467f60 LDR	X8, [X11, X3,LSL #3]

    (2154) 0x467f64 ADD	X4, X4, #1

    (2154) 0x467f68 CMP	X4, X8

    (2154) 0x467f6c B.GE	46806c

    (2154) 0x467f70 LDR	X27, [X12, X4,LSL #3]

    (2154) 0x467f74 LDR	X9, [X13, X27,LSL #3]

    (2154) 0x467f78 CMP	X9, #1

    (2154) 0x467f7c B.LT	467fa0

    (2154) 0x467f80 LDR	X9, [X5, X27,LSL #3]

    (2154) 0x467f84 LDR	X10, [X24, X9,LSL #3]

    (2154) 0x467f88 CMP	X10, X1

    (2154) 0x467f8c B.GE	467fa0

    (2154) 0x467f90 LDUR	X10, [X29, #480]

    (2154) 0x467f94 STR	X10, [X24, X9,LSL #3]

    (2154) 0x467f98 ADD	X9, X10, #1

    (2154) 0x467f9c STUR	X9, [X29, #480]

    (2154) 0x467fa0 ADD	X28, X27, #1

    (2154) 0x467fa4 LDR	X30, [X11, X27,LSL #3]

    (2154) 0x467fa8 LDR	X19, [X11, X28,LSL #3]

    (2154) 0x467fac CMP	X30, X19

    (2154) 0x467fb0 B.GE	46800c

    (2154) 0x467fb4 LDUR	X8, [X29, #456]

    (2154) 0x467fb8 LDR	X10, [X8]

    (2154) 0x467fbc B	467fcc

      (2156) 0x467fc0 ADD	X30, X30, #1

      (2156) 0x467fc4 CMP	X30, X19

      (2156) 0x467fc8 B.GE	46800c

      (2156) 0x467fcc LDR	X9, [X12, X30,LSL #3]

      (2156) 0x467fd0 LDR	X8, [X13, X9,LSL #3]

      (2156) 0x467fd4 CMP	X8, #1

      (2156) 0x467fd8 B.LT	467fc0

      (2156) 0x467fdc LDR	X9, [X10, X9,LSL #3]

      (2156) 0x467fe0 CMP	X9, X18

      (2156) 0x467fe4 B.EQ	467fc0

      (2156) 0x467fe8 LDR	X8, [X24, X9,LSL #3]

      (2156) 0x467fec CMP	X8, X1

      (2156) 0x467ff0 B.GE	467fc0

      (2156) 0x467ff4 LDUR	X8, [X29, #480]

      (2156) 0x467ff8 STR	X8, [X24, X9,LSL #3]

      (2156) 0x467ffc ADD	X8, X8, #1

      (2156) 0x468000 STUR	X8, [X29, #480]

      (2156) 0x468004 LDR	X19, [X11, X28,LSL #3]

      (2156) 0x468008 B	467fc0

    (2154) 0x46800c LDR	X19, [X14, X27,LSL #3]

    (2154) 0x468010 LDR	X10, [X14, X28,LSL #3]

    (2154) 0x468014 CMP	X19, X10

    (2154) 0x468018 B.GE	467f60

    (2154) 0x46801c LDUR	X8, [X29, #464]

    (2154) 0x468020 LDR	X27, [X8]

    (2154) 0x468024 B	468034

      (2155) 0x468028 ADD	X19, X19, #1

      (2155) 0x46802c CMP	X19, X10

      (2155) 0x468030 B.GE	467f60

      (2155) 0x468034 LDR	X9, [X6, X19,LSL #3]

      (2155) 0x468038 LDR	X8, [X7, X9,LSL #3]

      (2155) 0x46803c CMP	X8, #1

      (2155) 0x468040 B.LT	468028

      (2155) 0x468044 LDR	X9, [X27, X9,LSL #3]

      (2155) 0x468048 LDR	X8, [X25, X9,LSL #3]

      (2155) 0x46804c CMP	X8, X2

      (2155) 0x468050 B.GE	468028

      (2155) 0x468054 LDUR	X8, [X29, #472]

      (2155) 0x468058 STR	X8, [X25, X9,LSL #3]

      (2155) 0x46805c ADD	X8, X8, #1

      (2155) 0x468060 STUR	X8, [X29, #472]

      (2155) 0x468064 LDR	X10, [X14, X28,LSL #3]

      (2155) 0x468068 B	468028

  (2151) 0x46806c LDUR	X8, [X29, #440]

  (2151) 0x468070 LDR	X9, [X14, X3,LSL #3]

  (2151) 0x468074 LDR	X8, [X14, X8,LSL #3]

  (2151) 0x468078 CMP	X8, X9

  (2151) 0x46807c B.GE	467ee8

(2152) 0x468080 LDUR	X9, [X29, #464]

(2152) 0x468084 LDR	X4, [X9]

(2152) 0x468088 LDR	X9, [SP, #144]

(2152) 0x46808c LDR	X5, [X9]

(2152) 0x468090 LDUR	X9, [X29, #376]

(2152) 0x468094 LDR	X6, [X9]

(2152) 0x468098 B	4680b0

0x46809c HINT	#0

(2152) 0x4680a0 LDR	X9, [X14, X3,LSL #3]

(2152) 0x4680a4 ADD	X8, X8, #1

(2152) 0x4680a8 CMP	X8, X9

(2152) 0x4680ac B.GE	467ee8

(2152) 0x4680b0 LDR	X27, [X15, X8,LSL #3]

(2152) 0x4680b4 LDR	X9, [X16, X27,LSL #3]

(2152) 0x4680b8 CMP	X9, #1

(2152) 0x4680bc B.LT	4680e0

(2152) 0x4680c0 LDR	X9, [X4, X27,LSL #3]

(2152) 0x4680c4 LDR	X10, [X25, X9,LSL #3]

(2152) 0x4680c8 CMP	X10, X2

(2152) 0x4680cc B.GE	4680e0

(2152) 0x4680d0 LDUR	X10, [X29, #472]

(2152) 0x4680d4 STR	X10, [X25, X9,LSL #3]

(2152) 0x4680d8 ADD	X9, X10, #1

(2152) 0x4680dc STUR	X9, [X29, #472]

(2152) 0x4680e0 ADD	X7, X27, #1

(2152) 0x4680e4 LDR	X10, [X17, X27,LSL #3]

(2152) 0x4680e8 LDR	X19, [X17, X7,LSL #3]

(2152) 0x4680ec B	468104

0x4680f0 HINT	#0

0x4680f4 HINT	#0

0x4680f8 HINT	#0

0x4680fc HINT	#0

  (2153) 0x468100 ADD	X10, X10, #1

  (2153) 0x468104 CMP	X10, X19

  (2153) 0x468108 B.GE	468140

  (2153) 0x46810c LDR	X9, [X5, X10,LSL #3]

  (2153) 0x468110 CMP	X9, X18

  (2153) 0x468114 B.EQ	468100

  (2153) 0x468118 LDR	X28, [X24, X9,LSL #3]

  (2153) 0x46811c CMP	X28, X1

  (2153) 0x468120 B.GE	468100

  (2153) 0x468124 LDUR	X19, [X29, #480]

  (2153) 0x468128 STR	X19, [X24, X9,LSL #3]

  (2153) 0x46812c ADD	X9, X19, #1

  (2153) 0x468130 STUR	X9, [X29, #480]

  (2153) 0x468134 LDR	X19, [X17, X7,LSL #3]

  (2153) 0x468138 B	468100

0x46813c HINT	#0

(2152) 0x468140 LDR	X10, [X0, X27,LSL #3]

(2152) 0x468144 LDR	X19, [X0, X7,LSL #3]

(2152) 0x468148 B	468150

  (2157) 0x46814c ADD	X10, X10, #1

  (2157) 0x468150 CMP	X10, X19

  (2157) 0x468154 B.GE	4680a0

  (2157) 0x468158 LDR	X9, [X6, X10,LSL #3]

  (2157) 0x46815c LDR	X27, [X25, X9,LSL #3]

  (2157) 0x468160 CMP	X27, X2

  (2157) 0x468164 B.GE	46814c

  (2157) 0x468168 LDUR	X19, [X29, #472]

  (2157) 0x46816c STR	X19, [X25, X9,LSL #3]

  (2157) 0x468170 ADD	X9, X19, #1

  (2157) 0x468174 STUR	X9, [X29, #472]

  (2157) 0x468178 LDR	X19, [X0, X7,LSL #3]

  (2157) 0x46817c B	46814c

0x468180 CMP	X22, X9

0x468184 B.GE	468730

0x468188 LDR	X8, [SP, #80]

0x46818c MOVZ	W3, #1

0x468190 ORR	X2, XZR, XZR

0x468194 ORR	X4, XZR, XZR

0x468198 ORR	X5, XZR, X22

0x46819c LDR	X9, [X8]

0x4681a0 LDR	X8, [SP, #120]

0x4681a4 LDR	X8, [X8]

0x4681a8 STP	X8, X9, [SP, #128]

0x4681ac LDP	X9, X8, [SP, #16]

0x4681b0 LDR	X12, [X8]

0x4681b4 LDR	X8, [SP, #88]

0x4681b8 LDR	X11, [X9]

0x4681bc LDR	X13, [X8]

0x4681c0 LDR	X8, [SP, #32]

0x4681c4 LDR	X14, [X8]

0x4681c8 LDP	X10, X8, [X29, #896]

0x4681cc LDR	X9, [X10]

0x4681d0 LDR	X8, [X8]

0x4681d4 STP	X8, X9, [X29, #944]

0x4681d8 ADD	X9, X20, #8

0x4681dc ADD	X8, X21, #8

0x4681e0 STP	X8, X9, [SP, #64]

0x4681e4 LDP	X9, X8, [SP, #40]

0x4681e8 LDR	X0, [X9]

0x4681ec LDR	X6, [X8]

0x4681f0 B	468210

0x4681f4 HINT	#0

0x4681f8 HINT	#0

0x4681fc HINT	#0

    (2141) 0x468200 LDUR	X8, [X29, #424]

    (2141) 0x468204 ADD	X5, X5, #1

    (2141) 0x468208 CMP	X5, X8

    (2141) 0x46820c B.EQ	468730

    (2141) 0x468210 LDR	X8, [SP, #136]

    (2141) 0x468214 LDUR	X9, [X29, #408]

    (2141) 0x468218 ORR	X7, XZR, X4

    (2141) 0x46821c ORR	X30, XZR, X2

    (2141) 0x468220 LDR	X15, [X8, X5,LSL #3]

    (2141) 0x468224 LDUR	X8, [X29, #480]

    (2141) 0x468228 STR	X8, [X9, X5,LSL #3]

    (2141) 0x46822c LDR	X8, [X27]

    (2141) 0x468230 CBZ	X8, 468240

    (2141) 0x468234 LDUR	X8, [X29, #472]

    (2141) 0x468238 LDR	X9, [SP, #128]

    (2141) 0x46823c STR	X8, [X9, X5,LSL #3]

    (2141) 0x468240 ADD	X17, X15, #1

    (2141) 0x468244 LDR	X10, [X11, X15,LSL #3]

    (2141) 0x468248 STUR	X15, [X29, #400]

    (2141) 0x46824c ORR	X4, XZR, X7

    (2141) 0x468250 ORR	X2, XZR, X30

    (2141) 0x468254 LDR	X8, [X11, X17,LSL #3]

    (2141) 0x468258 CMP	X10, X8

    (2141) 0x46825c B.GE	4683e0

    (2141) 0x468260 LDUR	X8, [X29, #456]

    (2141) 0x468264 ORR	X2, XZR, X30

    (2141) 0x468268 ORR	X4, XZR, X7

    (2141) 0x46826c LDR	X9, [X8]

    (2141) 0x468270 LDP	X8, X15, [X29, #896]

    (2141) 0x468274 LDR	X8, [X8]

    (2141) 0x468278 LDR	X1, [X15]

    (2141) 0x46827c B	468290

      (2147) 0x468280 LDR	X15, [X11, X17,LSL #3]

      (2147) 0x468284 ADD	X10, X10, #1

      (2147) 0x468288 CMP	X10, X15

      (2147) 0x46828c B.GE	4683e0

      (2147) 0x468290 LDR	X27, [X12, X10,LSL #3]

      (2147) 0x468294 LDR	X15, [X13, X27,LSL #3]

      (2147) 0x468298 CMP	X15, #1

      (2147) 0x46829c B.LT	4682c4

      (2147) 0x4682a0 LDR	X15, [X9, X27,LSL #3]

      (2147) 0x4682a4 LDR	X16, [X24, X15,LSL #3]

      (2147) 0x4682a8 SUBS	X18, X16, X30

      (2147) 0x4682ac B.GE	4682e0

      (2147) 0x4682b0 STR	X2, [X24, X15,LSL #3]

      (2147) 0x4682b4 SUB	X15, X2, X30

      (2147) 0x4682b8 MOVZ	W16, #2

      (2147) 0x4682bc ADD	X2, X2, #1

      (2147) 0x4682c0 STR	X16, [X20, X15,LSL #3]

      (2147) 0x4682c4 ADD	X28, X27, #1

      (2147) 0x4682c8 LDR	X18, [X11, X27,LSL #3]

      (2147) 0x4682cc LDR	X15, [X11, X28,LSL #3]

      (2147) 0x4682d0 CMP	X18, X15

      (2147) 0x4682d4 B.LT	468300

      (2147) 0x4682d8 B	46836c

0x4682dc HINT	#0

      (2147) 0x4682e0 LDR	X15, [X20, X18,LSL #3]

      (2147) 0x4682e4 ADD	X15, X15, #2

      (2147) 0x4682e8 STR	X15, [X20, X18,LSL #3]

      (2147) 0x4682ec ADD	X28, X27, #1

      (2147) 0x4682f0 LDR	X18, [X11, X27,LSL #3]

      (2147) 0x4682f4 LDR	X15, [X11, X28,LSL #3]

      (2147) 0x4682f8 CMP	X18, X15

      (2147) 0x4682fc B.GE	46836c

      (2147) 0x468300 LDUR	X15, [X29, #456]

      (2147) 0x468304 LDR	X19, [X15]

      (2147) 0x468308 B	468330

        (2149) 0x46830c LDR	X15, [X20, X16,LSL #3]

        (2149) 0x468310 ADD	X15, X15, #1

        (2149) 0x468314 STR	X15, [X20, X16,LSL #3]

        (2149) 0x468318 HINT	#0

        (2149) 0x46831c HINT	#0

        (2149) 0x468320 LDR	X15, [X11, X28,LSL #3]

        (2149) 0x468324 ADD	X18, X18, #1

        (2149) 0x468328 CMP	X18, X15

        (2149) 0x46832c B.GE	46836c

        (2149) 0x468330 LDR	X15, [X12, X18,LSL #3]

        (2149) 0x468334 LDR	X16, [X13, X15,LSL #3]

        (2149) 0x468338 CMP	X16, #1

        (2149) 0x46833c B.LT	468320

        (2149) 0x468340 LDR	X15, [X19, X15,LSL #3]

        (2149) 0x468344 CMP	X15, X5

        (2149) 0x468348 B.EQ	468320

        (2149) 0x46834c LDR	X16, [X24, X15,LSL #3]

        (2149) 0x468350 SUBS	X16, X16, X30

        (2149) 0x468354 B.GE	46830c

        (2149) 0x468358 STR	X2, [X24, X15,LSL #3]

        (2149) 0x46835c SUB	X15, X2, X30

        (2149) 0x468360 ADD	X2, X2, #1

        (2149) 0x468364 STR	X3, [X20, X15,LSL #3]

        (2149) 0x468368 B	468320

      (2147) 0x46836c LDR	X18, [X14, X27,LSL #3]

      (2147) 0x468370 LDR	X15, [X14, X28,LSL #3]

      (2147) 0x468374 CMP	X18, X15

      (2147) 0x468378 B.GE	468280

      (2147) 0x46837c LDUR	X15, [X29, #464]

      (2147) 0x468380 LDR	X19, [X15]

      (2147) 0x468384 B	4683a4

        (2148) 0x468388 LDR	X15, [X21, X16,LSL #3]

        (2148) 0x46838c ADD	X15, X15, #1

        (2148) 0x468390 STR	X15, [X21, X16,LSL #3]

        (2148) 0x468394 LDR	X15, [X14, X28,LSL #3]

        (2148) 0x468398 ADD	X18, X18, #1

        (2148) 0x46839c CMP	X18, X15

        (2148) 0x4683a0 B.GE	468280

        (2148) 0x4683a4 LDR	X15, [X8, X18,LSL #3]

        (2148) 0x4683a8 LDR	X16, [X1, X15,LSL #3]

        (2148) 0x4683ac CMP	X16, #1

        (2148) 0x4683b0 B.LT	468394

        (2148) 0x4683b4 LDR	X15, [X19, X15,LSL #3]

        (2148) 0x4683b8 LDR	X16, [X25, X15,LSL #3]

        (2148) 0x4683bc SUBS	X16, X16, X7

        (2148) 0x4683c0 B.GE	468388

        (2148) 0x4683c4 STR	X4, [X25, X15,LSL #3]

        (2148) 0x4683c8 SUB	X15, X4, X7

        (2148) 0x4683cc ADD	X4, X4, #1

        (2148) 0x4683d0 STR	X3, [X21, X15,LSL #3]

        (2148) 0x4683d4 B	468394

0x4683d8 HINT	#0

0x4683dc HINT	#0

    (2141) 0x4683e0 LDUR	X8, [X29, #400]

    (2141) 0x4683e4 LDR	X9, [X14, X17,LSL #3]

    (2141) 0x4683e8 LDR	X8, [X14, X8,LSL #3]

    (2141) 0x4683ec CMP	X8, X9

    (2141) 0x4683f0 B.GE	468580

    (2141) 0x4683f4 LDUR	X9, [X29, #464]

    (2141) 0x4683f8 LDR	X10, [SP, #144]

    (2141) 0x4683fc LDUR	X15, [X29, #376]

    (2141) 0x468400 LDR	X9, [X9]

    (2141) 0x468404 LDR	X10, [X10]

    (2141) 0x468408 LDR	X18, [X15]

    (2141) 0x46840c B	468430

0x468410 HINT	#0

0x468414 HINT	#0

0x468418 HINT	#0

0x46841c HINT	#0

      (2144) 0x468420 LDR	X15, [X14, X17,LSL #3]

      (2144) 0x468424 ADD	X8, X8, #1

      (2144) 0x468428 CMP	X8, X15

      (2144) 0x46842c B.GE	468580

      (2144) 0x468430 LDUR	X15, [X29, #440]

      (2144) 0x468434 LDR	X27, [X15, X8,LSL #3]

      (2144) 0x468438 LDUR	X15, [X29, #432]

      (2144) 0x46843c LDR	X15, [X15, X27,LSL #3]

      (2144) 0x468440 CMP	X15, #1

      (2144) 0x468444 B.LT	46846c

      (2144) 0x468448 LDR	X15, [X9, X27,LSL #3]

      (2144) 0x46844c LDR	X16, [X25, X15,LSL #3]

      (2144) 0x468450 SUBS	X16, X16, X7

      (2144) 0x468454 B.GE	468484

      (2144) 0x468458 STR	X4, [X25, X15,LSL #3]

      (2144) 0x46845c SUB	X15, X4, X7

      (2144) 0x468460 MOVZ	W16, #2

      (2144) 0x468464 ADD	X4, X4, #1

      (2144) 0x468468 STR	X16, [X21, X15,LSL #3]

      (2144) 0x46846c LDR	X19, [X0, X27,LSL #3]

      (2144) 0x468470 ADD	X1, X27, #1

      (2144) 0x468474 LDR	X15, [X0, X1,LSL #3]

      (2144) 0x468478 CMP	X19, X15

      (2144) 0x46847c B.LT	4684c4

      (2144) 0x468480 B	4684fc

      (2144) 0x468484 LDR	X15, [X21, X16,LSL #3]

      (2144) 0x468488 ADD	X15, X15, #2

      (2144) 0x46848c STR	X15, [X21, X16,LSL #3]

      (2144) 0x468490 LDR	X19, [X0, X27,LSL #3]

      (2144) 0x468494 ADD	X1, X27, #1

      (2144) 0x468498 LDR	X15, [X0, X1,LSL #3]

      (2144) 0x46849c CMP	X19, X15

      (2144) 0x4684a0 B.LT	4684c4

      (2144) 0x4684a4 B	4684fc

        (2146) 0x4684a8 LDR	X15, [X20, X16,LSL #3]

        (2146) 0x4684ac ADD	X15, X15, #1

        (2146) 0x4684b0 STR	X15, [X20, X16,LSL #3]

        (2146) 0x4684b4 ADD	X19, X19, #1

        (2146) 0x4684b8 LDR	X15, [X0, X1,LSL #3]

        (2146) 0x4684bc CMP	X19, X15

        (2146) 0x4684c0 B.GE	4684fc

        (2146) 0x4684c4 LDR	X15, [X10, X19,LSL #3]

        (2146) 0x4684c8 CMP	X15, X5

        (2146) 0x4684cc B.EQ	4684b4

        (2146) 0x4684d0 LDR	X16, [X24, X15,LSL #3]

        (2146) 0x4684d4 SUBS	X16, X16, X30

        (2146) 0x4684d8 B.GE	4684a8

        (2146) 0x4684dc STR	X2, [X24, X15,LSL #3]

        (2146) 0x4684e0 SUB	X15, X2, X30

        (2146) 0x4684e4 ADD	X2, X2, #1

        (2146) 0x4684e8 ADD	X19, X19, #1

        (2146) 0x4684ec STR	X3, [X20, X15,LSL #3]

        (2146) 0x4684f0 LDR	X15, [X0, X1,LSL #3]

        (2146) 0x4684f4 CMP	X19, X15

        (2146) 0x4684f8 B.LT	4684c4

      (2144) 0x4684fc LDR	X19, [X6, X27,LSL #3]

      (2144) 0x468500 LDR	X15, [X6, X1,LSL #3]

      (2144) 0x468504 CMP	X19, X15

      (2144) 0x468508 B.LT	468540

      (2144) 0x46850c B	468420

0x468510 HINT	#0

0x468514 HINT	#0

0x468518 HINT	#0

0x46851c HINT	#0

        (2145) 0x468520 STR	X4, [X25, X15,LSL #3]

        (2145) 0x468524 SUB	X15, X4, X7

        (2145) 0x468528 ADD	X4, X4, #1

        (2145) 0x46852c ADD	X19, X19, #1

        (2145) 0x468530 STR	X3, [X21, X15,LSL #3]

        (2145) 0x468534 LDR	X15, [X6, X1,LSL #3]

        (2145) 0x468538 CMP	X19, X15

        (2145) 0x46853c B.GE	468420

        (2145) 0x468540 LDR	X15, [X18, X19,LSL #3]

        (2145) 0x468544 LDR	X16, [X25, X15,LSL #3]

        (2145) 0x468548 SUBS	X16, X16, X7

        (2145) 0x46854c B.LT	468520

        (2145) 0x468550 LDR	X15, [X21, X16,LSL #3]

        (2145) 0x468554 ADD	X19, X19, #1

        (2145) 0x468558 ADD	X15, X15, #1

        (2145) 0x46855c STR	X15, [X21, X16,LSL #3]

        (2145) 0x468560 LDR	X15, [X6, X1,LSL #3]

        (2145) 0x468564 CMP	X19, X15

        (2145) 0x468568 B.LT	468540

      (2144) 0x46856c B	468420

0x468570 HINT	#0

0x468574 HINT	#0

0x468578 HINT	#0

0x46857c HINT	#0

    (2141) 0x468580 LDUR	X16, [X29, #448]

    (2141) 0x468584 LDUR	X27, [X29, #416]

    (2141) 0x468588 CMP	X2, X30

    (2141) 0x46858c B.LE	4685cc

    (2141) 0x468590 SUB	W8, W2, W30

    (2141) 0x468594 ORR	X9, XZR, X30

    (2141) 0x468598 TBZ	W8, #0, 4685c0

    (2141) 0x46859c LDR	X8, [X20]

    (2141) 0x4685a0 LDR	X9, [X16]

    (2141) 0x4685a4 CMP	X8, X9

    (2141) 0x4685a8 B.LT	4685b8

    (2141) 0x4685ac LDUR	X8, [X29, #480]

    (2141) 0x4685b0 ADD	X8, X8, #1

    (2141) 0x4685b4 STUR	X8, [X29, #480]

    (2141) 0x4685b8 ADD	X9, X30, #1

    (2141) 0x4685bc STR	XZR, [X20]

    (2141) 0x4685c0 ADD	X8, X30, #1

    (2141) 0x4685c4 CMP	X2, X8

    (2141) 0x4685c8 B.NE	4686a0

    (2141) 0x4685cc CMP	X4, X7

    (2141) 0x4685d0 B.LE	468200

    (2141) 0x4685d4 SUB	W8, W4, W7

    (2141) 0x4685d8 ORR	X9, XZR, X7

    (2141) 0x4685dc TBZ	W8, #0, 468604

    (2141) 0x4685e0 LDR	X8, [X21]

    (2141) 0x4685e4 LDR	X9, [X16]

    (2141) 0x4685e8 CMP	X8, X9

    (2141) 0x4685ec B.LT	4685fc

    (2141) 0x4685f0 LDUR	X8, [X29, #472]

    (2141) 0x4685f4 ADD	X8, X8, #1

    (2141) 0x4685f8 STUR	X8, [X29, #472]

    (2141) 0x4685fc ADD	X9, X7, #1

    (2141) 0x468600 STR	XZR, [X21]

    (2141) 0x468604 ADD	X8, X7, #1

    (2141) 0x468608 CMP	X4, X8

    (2141) 0x46860c B.EQ	468200

    (2141) 0x468610 LDR	X10, [SP, #64]

    (2141) 0x468614 SUB	X8, X4, X9

    (2141) 0x468618 SUB	X10, X10, X7,LSL #3

    (2141) 0x46861c ADD	X9, X10, X9,LSL #3

    (2141) 0x468620 B	468630

      (2150) 0x468624 STR	XZR, [X9], #16

      (2150) 0x468628 SUBS	X8, X8, #2

      (2150) 0x46862c B.EQ	468200

      (2150) 0x468630 LDUR	X10, [X9, #504]

      (2150) 0x468634 LDR	X15, [X16]

      (2150) 0x468638 CMP	X10, X15

      (2150) 0x46863c B.GE	468660

      (2150) 0x468640 STUR	XZR, [X9, #504]

      (2150) 0x468644 LDR	X10, [X9]

      (2150) 0x468648 LDR	X15, [X16]

      (2150) 0x46864c CMP	X10, X15

      (2150) 0x468650 B.LT	468624

      (2150) 0x468654 B	468680

0x468658 HINT	#0

0x46865c HINT	#0

      (2150) 0x468660 LDUR	X10, [X29, #472]

      (2150) 0x468664 ADD	X10, X10, #1

      (2150) 0x468668 STUR	X10, [X29, #472]

      (2150) 0x46866c STUR	XZR, [X9, #504]

      (2150) 0x468670 LDR	X10, [X9]

      (2150) 0x468674 LDR	X15, [X16]

      (2150) 0x468678 CMP	X10, X15

      (2150) 0x46867c B.LT	468624

      (2150) 0x468680 LDUR	X10, [X29, #472]

      (2150) 0x468684 ADD	X10, X10, #1

      (2150) 0x468688 STUR	X10, [X29, #472]

      (2150) 0x46868c B	468624

0x468690 HINT	#0

0x468694 HINT	#0

0x468698 HINT	#0

0x46869c HINT	#0

  (2143) 0x4686a0 LDR	X10, [SP, #72]

  (2143) 0x4686a4 SUB	X8, X2, X9

  (2143) 0x4686a8 SUB	X10, X10, X30,LSL #3

  (2143) 0x4686ac ADD	X9, X10, X9,LSL #3

  (2143) 0x4686b0 B	4686cc

0x4686b4 HINT	#0

0x4686b8 HINT	#0

0x4686bc HINT	#0

  (2143) 0x4686c0 STR	XZR, [X9], #16

  (2143) 0x4686c4 SUBS	X8, X8, #2

  (2143) 0x4686c8 B.EQ	4685cc

  (2143) 0x4686cc LDUR	X10, [X9, #504]

  (2143) 0x4686d0 LDR	X15, [X16]

  (2143) 0x4686d4 CMP	X10, X15

  (2143) 0x4686d8 B.GE	468700

  (2143) 0x4686dc STUR	XZR, [X9, #504]

  (2143) 0x4686e0 LDR	X10, [X9]

  (2143) 0x4686e4 LDR	X15, [X16]

  (2143) 0x4686e8 CMP	X10, X15

  (2143) 0x4686ec B.LT	4686c0

  (2143) 0x4686f0 B	468720

0x4686f4 HINT	#0

0x4686f8 HINT	#0

0x4686fc HINT	#0

(2142) 0x468700 LDUR	X10, [X29, #480]

(2142) 0x468704 ADD	X10, X10, #1

(2142) 0x468708 STUR	X10, [X29, #480]

(2142) 0x46870c STUR	XZR, [X9, #504]

(2142) 0x468710 LDR	X10, [X9]

(2142) 0x468714 LDR	X15, [X16]

(2142) 0x468718 CMP	X10, X15

(2142) 0x46871c B.LT	4686c0

  (2143) 0x468720 LDUR	X10, [X29, #480]

  (2143) 0x468724 ADD	X10, X10, #1

  (2143) 0x468728 STUR	X10, [X29, #480]

  (2143) 0x46872c B	4686c0

0x468730 LDP	X10, X19, [SP, #96]

0x468734 LDR	X9, [SP, #120]

0x468738 SUB	X0, X29, #32

0x46873c SUB	X2, X29, #40

0x468740 LDR	X8, [X19]

0x468744 LDR	X9, [X9]

0x468748 LDR	X4, [X10]

0x46874c LDUR	X10, [X29, #408]

0x468750 ADD	X1, X10, X8,LSL #3

0x468754 ADD	X3, X9, X8,LSL #3

0x468758 BL	4aba90

0x46875c LDR	X8, [X19]

0x468760 CMP	X8, #1

0x468764 B.LT	468794

0x468768 MOVN	X9, #0

0x46876c ORR	X11, XZR, X19

0x468770 ORR	X8, XZR, XZR

0x468774 HINT	#0

0x468778 HINT	#0

0x46877c HINT	#0

(2140) 0x468780 STR	X9, [X24, X8,LSL #3]

(2140) 0x468784 ADD	X8, X8, #1

(2140) 0x468788 LDR	X10, [X11]

(2140) 0x46878c CMP	X8, X10

(2140) 0x468790 B.LT	468780

0x468794 LDP	X8, X9, [X29, #264]

0x468798 STUR	X8, [X29, #440]

0x46879c LDR	X8, [X27]

0x4687a0 STUR	X9, [X29, #408]

0x4687a4 CMP	X8, #1

0x4687a8 B.LT	4687d4

0x4687ac MOVN	X9, #0

0x4687b0 ORR	X8, XZR, XZR

0x4687b4 HINT	#0

0x4687b8 HINT	#0

0x4687bc HINT	#0

(2139) 0x4687c0 STR	X9, [X25, X8,LSL #3]

(2139) 0x4687c4 ADD	X8, X8, #1

(2139) 0x4687c8 LDR	X10, [X27]

(2139) 0x4687cc CMP	X8, X10

(2139) 0x4687d0 B.LT	4687c0

0x4687d4 LDR	X8, [SP, #56]

0x4687d8 ADRP	X0,

0x4687dc ADD	X0, X0, #592

0x4687e0 LDR	W27, [X8]

0x4687e4 ORR	W1, WZR, W27

0x4687e8 BL	40f890

0x4687ec ADRP	X0,

0x4687f0 ADD	X0, X0, #616

0x4687f4 ORR	W1, WZR, W27

0x4687f8 BL	40f450

0x4687fc CBZ	W0, 46885c

0x468800 LDP	X10, X8, [SP, #104]

0x468804 LDR	X9, [X8]

0x468808 LDR	X8, [X10]

0x46880c LDR	X9, [X9, X8,LSL #3]

0x468810 CBZ	X9, 46882c

0x468814 UBFM	X0, X9, #61, #60

0x468818 ORR	X19, XZR, X10

0x46881c BL	4a9060

0x468820 LDUR	X8, [X29, #440]

0x468824 STR	X0, [X8]

0x468828 LDR	X8, [X19]

0x46882c LDR	X9, [SP, #120]

0x468830 LDR	X9, [X9]

0x468834 LDR	X8, [X9, X8,LSL #3]

0x468838 CBZ	X8, 46884c

0x46883c UBFM	X0, X8, #61, #60

0x468840 BL	4a9060

0x468844 LDUR	X8, [X29, #408]

0x468848 STR	X0, [X8]

0x46884c ADRP	X0,

0x468850 ADD	X0, X0, #616

0x468854 ORR	W1, WZR, W27

0x468858 BL	40f920

0x46885c ADRP	X0,

0x468860 ADD	X0, X0, #640

0x468864 ORR	W1, WZR, W27

0x468868 BL	40f890

0x46886c LDUR	X0, [X29, #424]

0x468870 LDR	X1, [SP, #112]

0x468874 LDUR	X30, [X29, #408]

0x468878 ORR	X9, XZR, X22

0x46887c SUB	X8, X0, #1

0x468880 CMP	X22, X8

0x468884 B.GE	468918

0x468888 LDR	X9, [SP, #120]

0x46888c LDR	X13, [X1]

0x468890 MOVZ	W14, #2

0x468894 LDR	X12, [X9]

0x468898 LDP	X10, X9, [SP, #80]

0x46889c ADD	X13, X13, X22,LSL #3

0x4688a0 LDR	X11, [X10]

0x4688a4 LDR	X9, [X9]

0x4688a8 ORN	X10, XZR, X22

0x4688ac ADD	X12, X12, X22,LSL #3

0x4688b0 ADD	X10, X10, X0

0x4688b4 ADD	X11, X11, X22,LSL #3

0x4688b8 B	4688e8

0x4688bc HINT	#0

(2138) 0x4688c0 LDUR	X16, [X29, #480]

(2138) 0x4688c4 SUBS	X10, X10, #1

(2138) 0x4688c8 ADD	X11, X11, #8

(2138) 0x4688cc ADD	X15, X15, X16

(2138) 0x4688d0 STR	X15, [X13], #8

(2138) 0x4688d4 LDUR	X15, [X29, #472]

(2138) 0x4688d8 LDR	X16, [X12]

(2138) 0x4688dc ADD	X15, X16, X15

(2138) 0x4688e0 STR	X15, [X12], #8

(2138) 0x4688e4 B.EQ	468914

(2138) 0x4688e8 LDP	X15, X16, [X13]

(2138) 0x4688ec CMP	X16, X15

(2138) 0x4688f0 B.NE	4688c0

(2138) 0x4688f4 LDP	X18, X17, [X12]

(2138) 0x4688f8 ORR	X15, XZR, X16

(2138) 0x4688fc CMP	X17, X18

(2138) 0x468900 B.NE	4688c0

(2138) 0x468904 LDR	X15, [X11]

(2138) 0x468908 STR	X14, [X9, X15,LSL #3]

(2138) 0x46890c LDR	X15, [X13]

(2138) 0x468910 B	4688c0

0x468914 ORR	X9, XZR, X8

0x468918 CMP	X22, X0

0x46891c B.GE	4692c4

0x468920 LDR	X11, [X1]

0x468924 LDUR	X8, [X29, #480]

0x468928 LDR	X13, [SP, #8]

0x46892c LDR	X10, [X11, X9,LSL #3]

0x468930 ADD	X8, X10, X8

0x468934 LDR	X10, [SP, #120]

0x468938 STR	X8, [X11, X9,LSL #3]

0x46893c LDUR	X8, [X29, #472]

0x468940 LDR	X10, [X10]

0x468944 LDR	X12, [X10, X9,LSL #3]

0x468948 ADD	X8, X12, X8

0x46894c UBFM	X12, X13, #60, #59

0x468950 STR	X8, [X10, X9,LSL #3]

0x468954 LDR	X10, [SP, #96]

0x468958 LDR	X11, [X11, X9,LSL #3]

0x46895c LDR	X10, [X10]

0x468960 LDR	X12, [X10, X12]

0x468964 CMP	X12, X11

0x468968 B.NE	468998

0x46896c UBFM	X11, X13, #63, #62

0x468970 ADD	X10, X10, X11,LSL #3

0x468974 LDR	X10, [X10, #8]

0x468978 CMP	X10, X8

0x46897c B.NE	468998

0x468980 LDP	X10, X8, [SP, #80]

0x468984 LDR	X10, [X10]

0x468988 LDR	X8, [X8]

0x46898c LDR	X9, [X10, X9,LSL #3]

0x468990 MOVZ	W10, #2

0x468994 STR	X10, [X8, X9,LSL #3]

0x468998 LDUR	X8, [X29, #448]

0x46899c LDR	X8, [X8]

0x4689a0 CMP	X8, #1

0x4689a4 B.NE	468cc0

0x4689a8 CMP	X22, X0

0x4689ac B.GE	4692c4

0x4689b0 LDP	X8, X11, [SP, #80]

0x4689b4 LDP	X9, X10, [SP, #16]

0x4689b8 LDP	X12, X15, [SP, #32]

0x4689bc LDP	X13, X14, [X29, #896]

0x4689c0 LDR	X16, [SP, #48]

0x4689c4 LDR	X8, [X8]

0x4689c8 LDR	X9, [X9]

0x4689cc LDR	X10, [X10]

0x4689d0 LDR	X11, [X11]

0x4689d4 LDR	X12, [X12]

0x4689d8 LDR	X13, [X13]

0x4689dc LDR	X14, [X14]

0x4689e0 LDR	X15, [X15]

0x4689e4 LDR	X16, [X16]

0x4689e8 B	4689fc

  (2131) 0x4689ec LDUR	X17, [X29, #424]

  (2131) 0x4689f0 ADD	X22, X22, #1

  (2131) 0x4689f4 CMP	X22, X17

  (2131) 0x4689f8 B.EQ	4692c4

  (2131) 0x4689fc LDR	X1, [X8, X22,LSL #3]

  (2131) 0x468a00 LDP	X18, X17, [X29, #984]

  (2131) 0x468a04 ADD	X0, X1, #1

  (2131) 0x468a08 LDR	X2, [X9, X1,LSL #3]

  (2131) 0x468a0c LDR	X3, [X9, X0,LSL #3]

  (2131) 0x468a10 CMP	X2, X3

  (2131) 0x468a14 B.GE	468b8c

  (2131) 0x468a18 LDUR	X3, [X29, #456]

  (2131) 0x468a1c LDUR	X4, [X29, #440]

  (2131) 0x468a20 LDP	X5, X6, [X29, #896]

  (2131) 0x468a24 LDR	X3, [X3]

  (2131) 0x468a28 LDR	X4, [X4]

  (2131) 0x468a2c LDR	X5, [X5]

  (2131) 0x468a30 LDR	X6, [X6]

  (2131) 0x468a34 B	468a50

0x468a38 HINT	#0

0x468a3c HINT	#0

    (2135) 0x468a40 LDR	X7, [X9, X0,LSL #3]

    (2135) 0x468a44 ADD	X2, X2, #1

    (2135) 0x468a48 CMP	X2, X7

    (2135) 0x468a4c B.GE	468b8c

    (2135) 0x468a50 LDR	X19, [X10, X2,LSL #3]

    (2135) 0x468a54 LDR	X7, [X11, X19,LSL #3]

    (2135) 0x468a58 CMP	X7, #1

    (2135) 0x468a5c B.LT	468a88

    (2135) 0x468a60 LDR	X7, [X3, X19,LSL #3]

    (2135) 0x468a64 LDR	X20, [X24, X7,LSL #3]

    (2135) 0x468a68 CMP	X20, X17

    (2135) 0x468a6c B.GE	468a88

    (2135) 0x468a70 LDUR	X20, [X29, #480]

    (2135) 0x468a74 STR	X20, [X24, X7,LSL #3]

    (2135) 0x468a78 STR	X7, [X4, X20,LSL #3]

    (2135) 0x468a7c LDUR	X7, [X29, #480]

    (2135) 0x468a80 ADD	X7, X7, #1

    (2135) 0x468a84 STUR	X7, [X29, #480]

    (2135) 0x468a88 ADD	X7, X19, #1

    (2135) 0x468a8c LDR	X20, [X9, X19,LSL #3]

    (2135) 0x468a90 LDR	X23, [X9, X7,LSL #3]

    (2135) 0x468a94 CMP	X20, X23

    (2135) 0x468a98 B.GE	468b20

    (2135) 0x468a9c LDUR	X21, [X29, #456]

    (2135) 0x468aa0 LDUR	X26, [X29, #440]

    (2135) 0x468aa4 LDR	X21, [X21]

    (2135) 0x468aa8 LDR	X26, [X26]

    (2135) 0x468aac B	468acc

0x468ab0 HINT	#0

0x468ab4 HINT	#0

0x468ab8 HINT	#0

0x468abc HINT	#0

      (2137) 0x468ac0 ADD	X20, X20, #1

      (2137) 0x468ac4 CMP	X20, X23

      (2137) 0x468ac8 B.GE	468b20

      (2137) 0x468acc LDR	X27, [X10, X20,LSL #3]

      (2137) 0x468ad0 LDR	X28, [X11, X27,LSL #3]

      (2137) 0x468ad4 CMP	X28, #1

      (2137) 0x468ad8 B.LT	468ac0

      (2137) 0x468adc LDR	X27, [X21, X27,LSL #3]

      (2137) 0x468ae0 CMP	X27, X22

      (2137) 0x468ae4 B.EQ	468ac0

      (2137) 0x468ae8 LDR	X28, [X24, X27,LSL #3]

      (2137) 0x468aec CMP	X28, X17

      (2137) 0x468af0 B.GE	468ac0

      (2137) 0x468af4 LDUR	X23, [X29, #480]

      (2137) 0x468af8 STR	X23, [X24, X27,LSL #3]

      (2137) 0x468afc STR	X27, [X26, X23,LSL #3]

      (2137) 0x468b00 LDUR	X23, [X29, #480]

      (2137) 0x468b04 ADD	X23, X23, #1

      (2137) 0x468b08 STUR	X23, [X29, #480]

      (2137) 0x468b0c LDR	X23, [X9, X7,LSL #3]

      (2137) 0x468b10 B	468ac0

0x468b14 HINT	#0

0x468b18 HINT	#0

0x468b1c HINT	#0

    (2135) 0x468b20 LDR	X19, [X12, X19,LSL #3]

    (2135) 0x468b24 LDR	X21, [X12, X7,LSL #3]

    (2135) 0x468b28 CMP	X19, X21

    (2135) 0x468b2c B.GE	468a40

    (2135) 0x468b30 LDUR	X20, [X29, #464]

    (2135) 0x468b34 LDR	X23, [X30]

    (2135) 0x468b38 LDR	X20, [X20]

    (2135) 0x468b3c B	468b4c

      (2136) 0x468b40 ADD	X19, X19, #1

      (2136) 0x468b44 CMP	X19, X21

      (2136) 0x468b48 B.GE	468a40

      (2136) 0x468b4c LDR	X26, [X5, X19,LSL #3]

      (2136) 0x468b50 LDR	X27, [X6, X26,LSL #3]

      (2136) 0x468b54 CMP	X27, #1

      (2136) 0x468b58 B.LT	468b40

      (2136) 0x468b5c LDR	X26, [X20, X26,LSL #3]

      (2136) 0x468b60 LDR	X27, [X25, X26,LSL #3]

      (2136) 0x468b64 CMP	X27, X18

      (2136) 0x468b68 B.GE	468b40

      (2136) 0x468b6c LDUR	X21, [X29, #472]

      (2136) 0x468b70 STR	X21, [X25, X26,LSL #3]

      (2136) 0x468b74 STR	X26, [X23, X21,LSL #3]

      (2136) 0x468b78 LDUR	X21, [X29, #472]

      (2136) 0x468b7c ADD	X21, X21, #1

      (2136) 0x468b80 STUR	X21, [X29, #472]

      (2136) 0x468b84 LDR	X21, [X12, X7,LSL #3]

      (2136) 0x468b88 B	468b40

  (2131) 0x468b8c LDR	X1, [X12, X1,LSL #3]

  (2131) 0x468b90 LDR	X2, [X12, X0,LSL #3]

  (2131) 0x468b94 CMP	X1, X2

  (2131) 0x468b98 B.GE	4689ec

(2132) 0x468b9c LDUR	X2, [X29, #464]

(2132) 0x468ba0 LDR	X4, [SP, #144]

(2132) 0x468ba4 LDUR	X5, [X29, #376]

(2132) 0x468ba8 LDR	X3, [X30]

(2132) 0x468bac LDR	X2, [X2]

(2132) 0x468bb0 LDR	X4, [X4]

(2132) 0x468bb4 LDR	X5, [X5]

(2132) 0x468bb8 B	468bd0

0x468bbc HINT	#0

(2132) 0x468bc0 LDR	X6, [X12, X0,LSL #3]

(2132) 0x468bc4 ADD	X1, X1, #1

(2132) 0x468bc8 CMP	X1, X6

(2132) 0x468bcc B.GE	4689ec

(2132) 0x468bd0 LDR	X7, [X13, X1,LSL #3]

(2132) 0x468bd4 LDR	X6, [X14, X7,LSL #3]

(2132) 0x468bd8 CMP	X6, #1

(2132) 0x468bdc B.LT	468c08

(2132) 0x468be0 LDR	X6, [X2, X7,LSL #3]

(2132) 0x468be4 LDR	X19, [X25, X6,LSL #3]

(2132) 0x468be8 CMP	X19, X18

(2132) 0x468bec B.GE	468c08

(2132) 0x468bf0 LDUR	X19, [X29, #472]

(2132) 0x468bf4 STR	X19, [X25, X6,LSL #3]

(2132) 0x468bf8 STR	X6, [X3, X19,LSL #3]

(2132) 0x468bfc LDUR	X6, [X29, #472]

(2132) 0x468c00 ADD	X6, X6, #1

(2132) 0x468c04 STUR	X6, [X29, #472]

(2132) 0x468c08 ADD	X6, X7, #1

(2132) 0x468c0c LDR	X19, [X15, X7,LSL #3]

(2132) 0x468c10 LDR	X21, [X15, X6,LSL #3]

(2132) 0x468c14 CMP	X19, X21

(2132) 0x468c18 B.GE	468c6c

(2132) 0x468c1c LDUR	X20, [X29, #440]

(2132) 0x468c20 LDR	X20, [X20]

(2132) 0x468c24 B	468c34

  (2134) 0x468c28 ADD	X19, X19, #1

  (2134) 0x468c2c CMP	X19, X21

  (2134) 0x468c30 B.GE	468c6c

  (2134) 0x468c34 LDR	X23, [X4, X19,LSL #3]

  (2134) 0x468c38 CMP	X23, X22

  (2134) 0x468c3c B.EQ	468c28

  (2134) 0x468c40 LDR	X26, [X24, X23,LSL #3]

  (2134) 0x468c44 CMP	X26, X17

  (2134) 0x468c48 B.GE	468c28

  (2134) 0x468c4c LDUR	X21, [X29, #480]

  (2134) 0x468c50 STR	X21, [X24, X23,LSL #3]

  (2134) 0x468c54 STR	X23, [X20, X21,LSL #3]

  (2134) 0x468c58 LDUR	X21, [X29, #480]

  (2134) 0x468c5c ADD	X21, X21, #1

  (2134) 0x468c60 STUR	X21, [X29, #480]

  (2134) 0x468c64 LDR	X21, [X15, X6,LSL #3]

  (2134) 0x468c68 B	468c28

(2132) 0x468c6c LDR	X7, [X16, X7,LSL #3]

(2132) 0x468c70 LDR	X20, [X16, X6,LSL #3]

(2132) 0x468c74 CMP	X7, X20

(2132) 0x468c78 B.GE	468bc0

(2132) 0x468c7c LDR	X19, [X30]

(2132) 0x468c80 B	468c90

  (2133) 0x468c84 ADD	X7, X7, #1

  (2133) 0x468c88 CMP	X7, X20

  (2133) 0x468c8c B.GE	468bc0

  (2133) 0x468c90 LDR	X21, [X5, X7,LSL #3]

  (2133) 0x468c94 LDR	X23, [X25, X21,LSL #3]

  (2133) 0x468c98 CMP	X23, X18

  (2133) 0x468c9c B.GE	468c84

  (2133) 0x468ca0 LDUR	X20, [X29, #472]

  (2133) 0x468ca4 STR	X20, [X25, X21,LSL #3]

  (2133) 0x468ca8 STR	X21, [X19, X20,LSL #3]

  (2133) 0x468cac LDUR	X20, [X29, #472]

  (2133) 0x468cb0 ADD	X20, X20, #1

  (2133) 0x468cb4 STUR	X20, [X29, #472]

  (2133) 0x468cb8 LDR	X20, [X16, X6,LSL #3]

  (2133) 0x468cbc B	468c84

0x468cc0 CMP	X22, X0

0x468cc4 B.GE	4692c4

0x468cc8 LDR	X8, [SP, #80]

0x468ccc LDP	X12, X13, [X29, #984]

0x468cd0 MOVZ	W4, #1

0x468cd4 LDR	X8, [X8]

0x468cd8 STUR	X8, [X29, #400]

0x468cdc LDP	X10, X8, [SP, #16]

0x468ce0 LDR	X9, [X10]

0x468ce4 LDR	X10, [X8]

0x468ce8 LDR	X8, [SP, #88]

0x468cec LDR	X11, [X8]

0x468cf0 LDR	X8, [SP, #32]

0x468cf4 LDR	X14, [X8]

0x468cf8 LDUR	X8, [X29, #384]

0x468cfc LDR	X8, [X8]

0x468d00 STUR	X8, [X29, #432]

0x468d04 ADD	X8, X26, #8

0x468d08 STR	X8, [SP, #136]

0x468d0c LDUR	X8, [X29, #392]

0x468d10 LDR	X17, [X8]

0x468d14 ADD	X8, X20, #8

0x468d18 STR	X8, [SP, #128]

0x468d1c ADD	X8, X23, #8

0x468d20 STR	X8, [SP, #120]

0x468d24 LDR	X8, [SP, #40]

0x468d28 LDR	X1, [X8]

0x468d2c ADD	X8, X21, #8

0x468d30 STR	X8, [SP, #112]

0x468d34 LDR	X8, [SP, #48]

0x468d38 LDR	X5, [X8]

0x468d3c B	468d50

  (2122) 0x468d40 LDUR	X8, [X29, #424]

  (2122) 0x468d44 ADD	X22, X22, #1

  (2122) 0x468d48 CMP	X22, X8

  (2122) 0x468d4c B.EQ	4692c4

  (2122) 0x468d50 LDUR	X8, [X29, #400]

  (2122) 0x468d54 ORR	X6, XZR, X12

  (2122) 0x468d58 ORR	X7, XZR, X13

  (2122) 0x468d5c LDR	X8, [X8, X22,LSL #3]

  (2122) 0x468d60 ADD	X30, X8, #1

  (2122) 0x468d64 LDR	X18, [X9, X8,LSL #3]

  (2122) 0x468d68 STUR	X8, [X29, #416]

  (2122) 0x468d6c LDR	X8, [X9, X30,LSL #3]

  (2122) 0x468d70 CMP	X18, X8

  (2122) 0x468d74 B.GE	468f20

  (2122) 0x468d78 LDUR	X8, [X29, #456]

  (2122) 0x468d7c ORR	X13, XZR, X7

  (2122) 0x468d80 ORR	X12, XZR, X6

  (2122) 0x468d84 LDR	X0, [X8]

  (2122) 0x468d88 LDUR	X8, [X29, #384]

  (2122) 0x468d8c LDR	X2, [X8]

  (2122) 0x468d90 LDUR	X8, [X29, #392]

  (2122) 0x468d94 LDR	X8, [X8]

  (2122) 0x468d98 B	468db0

0x468d9c HINT	#0

    (2127) 0x468da0 LDR	X15, [X9, X30,LSL #3]

    (2127) 0x468da4 ADD	X18, X18, #1

    (2127) 0x468da8 CMP	X18, X15

    (2127) 0x468dac B.GE	468f20

    (2127) 0x468db0 LDR	X28, [X10, X18,LSL #3]

    (2127) 0x468db4 LDR	X15, [X11, X28,LSL #3]

    (2127) 0x468db8 CMP	X15, #1

    (2127) 0x468dbc B.LT	468de8

    (2127) 0x468dc0 LDR	X16, [X0, X28,LSL #3]

    (2127) 0x468dc4 LDR	X15, [X24, X16,LSL #3]

    (2127) 0x468dc8 SUBS	X3, X15, X7

    (2127) 0x468dcc B.GE	468e00

    (2127) 0x468dd0 SUB	X15, X13, X7

    (2127) 0x468dd4 STR	X13, [X24, X16,LSL #3]

    (2127) 0x468dd8 ADD	X13, X13, #1

    (2127) 0x468ddc STR	X16, [X26, X15,LSL #3]

    (2127) 0x468de0 MOVZ	W16, #2

    (2127) 0x468de4 STR	X16, [X20, X15,LSL #3]

    (2127) 0x468de8 ADD	X3, X28, #1

    (2127) 0x468dec LDR	X27, [X9, X28,LSL #3]

    (2127) 0x468df0 LDR	X15, [X9, X3,LSL #3]

    (2127) 0x468df4 CMP	X27, X15

    (2127) 0x468df8 B.LT	468e20

    (2127) 0x468dfc B	468ea0

    (2127) 0x468e00 LDR	X15, [X20, X3,LSL #3]

    (2127) 0x468e04 ADD	X15, X15, #2

    (2127) 0x468e08 STR	X15, [X20, X3,LSL #3]

    (2127) 0x468e0c ADD	X3, X28, #1

    (2127) 0x468e10 LDR	X27, [X9, X28,LSL #3]

    (2127) 0x468e14 LDR	X15, [X9, X3,LSL #3]

    (2127) 0x468e18 CMP	X27, X15

    (2127) 0x468e1c B.GE	468ea0

    (2127) 0x468e20 LDUR	X15, [X29, #456]

    (2127) 0x468e24 LDR	X16, [X15]

    (2127) 0x468e28 B	468e50

      (2129) 0x468e2c LDR	X19, [X20, X15,LSL #3]

      (2129) 0x468e30 ADD	X19, X19, #1

      (2129) 0x468e34 STR	X19, [X20, X15,LSL #3]

      (2129) 0x468e38 HINT	#0

      (2129) 0x468e3c HINT	#0

      (2129) 0x468e40 LDR	X15, [X9, X3,LSL #3]

      (2129) 0x468e44 ADD	X27, X27, #1

      (2129) 0x468e48 CMP	X27, X15

      (2129) 0x468e4c B.GE	468ea0

      (2129) 0x468e50 LDR	X19, [X10, X27,LSL #3]

      (2129) 0x468e54 LDR	X15, [X11, X19,LSL #3]

      (2129) 0x468e58 CMP	X15, #1

      (2129) 0x468e5c B.LT	468e40

      (2129) 0x468e60 LDR	X19, [X16, X19,LSL #3]

      (2129) 0x468e64 CMP	X19, X22

      (2129) 0x468e68 B.EQ	468e40

      (2129) 0x468e6c LDR	X15, [X24, X19,LSL #3]

      (2129) 0x468e70 SUBS	X15, X15, X7

      (2129) 0x468e74 B.GE	468e2c

      (2129) 0x468e78 SUB	X15, X13, X7

      (2129) 0x468e7c STR	X13, [X24, X19,LSL #3]

      (2129) 0x468e80 ADD	X13, X13, #1

      (2129) 0x468e84 STR	X19, [X26, X15,LSL #3]

      (2129) 0x468e88 STR	X4, [X20, X15,LSL #3]

      (2129) 0x468e8c B	468e40

0x468e90 HINT	#0

0x468e94 HINT	#0

0x468e98 HINT	#0

0x468e9c HINT	#0

    (2127) 0x468ea0 LDR	X27, [X14, X28,LSL #3]

    (2127) 0x468ea4 LDR	X15, [X14, X3,LSL #3]

    (2127) 0x468ea8 CMP	X27, X15

    (2127) 0x468eac B.GE	468da0

    (2127) 0x468eb0 LDUR	X15, [X29, #464]

    (2127) 0x468eb4 LDR	X16, [X15]

    (2127) 0x468eb8 B	468edc

0x468ebc HINT	#0

      (2128) 0x468ec0 LDR	X19, [X21, X15,LSL #3]

      (2128) 0x468ec4 ADD	X19, X19, #1

      (2128) 0x468ec8 STR	X19, [X21, X15,LSL #3]

      (2128) 0x468ecc LDR	X15, [X14, X3,LSL #3]

      (2128) 0x468ed0 ADD	X27, X27, #1

      (2128) 0x468ed4 CMP	X27, X15

      (2128) 0x468ed8 B.GE	468da0

      (2128) 0x468edc LDR	X15, [X2, X27,LSL #3]

      (2128) 0x468ee0 LDR	X19, [X8, X15,LSL #3]

      (2128) 0x468ee4 CMP	X19, #1

      (2128) 0x468ee8 B.LT	468ecc

      (2128) 0x468eec LDR	X19, [X16, X15,LSL #3]

      (2128) 0x468ef0 LDR	X15, [X25, X19,LSL #3]

      (2128) 0x468ef4 SUBS	X15, X15, X6

      (2128) 0x468ef8 B.GE	468ec0

      (2128) 0x468efc SUB	X15, X12, X6

      (2128) 0x468f00 STR	X12, [X25, X19,LSL #3]

      (2128) 0x468f04 ADD	X12, X12, #1

      (2128) 0x468f08 STR	X19, [X23, X15,LSL #3]

      (2128) 0x468f0c STR	X4, [X21, X15,LSL #3]

      (2128) 0x468f10 B	468ecc

0x468f14 HINT	#0

0x468f18 HINT	#0

0x468f1c HINT	#0

  (2122) 0x468f20 LDUR	X8, [X29, #416]

  (2122) 0x468f24 LDR	X15, [X14, X30,LSL #3]

  (2122) 0x468f28 LDR	X8, [X14, X8,LSL #3]

  (2122) 0x468f2c CMP	X8, X15

  (2122) 0x468f30 B.GE	4690c0

  (2122) 0x468f34 LDUR	X15, [X29, #464]

  (2122) 0x468f38 LDR	X16, [X15]

  (2122) 0x468f3c LDR	X15, [SP, #144]

  (2122) 0x468f40 LDR	X18, [X15]

  (2122) 0x468f44 LDUR	X15, [X29, #376]

  (2122) 0x468f48 LDR	X0, [X15]

  (2122) 0x468f4c B	468f70

0x468f50 HINT	#0

0x468f54 HINT	#0

0x468f58 HINT	#0

0x468f5c HINT	#0

    (2124) 0x468f60 LDR	X15, [X14, X30,LSL #3]

    (2124) 0x468f64 ADD	X8, X8, #1

    (2124) 0x468f68 CMP	X8, X15

    (2124) 0x468f6c B.GE	4690c0

    (2124) 0x468f70 LDUR	X15, [X29, #432]

    (2124) 0x468f74 LDR	X3, [X15, X8,LSL #3]

    (2124) 0x468f78 LDR	X15, [X17, X3,LSL #3]

    (2124) 0x468f7c CMP	X15, #1

    (2124) 0x468f80 B.LT	468fac

    (2124) 0x468f84 LDR	X2, [X16, X3,LSL #3]

    (2124) 0x468f88 LDR	X15, [X25, X2,LSL #3]

    (2124) 0x468f8c SUBS	X15, X15, X6

    (2124) 0x468f90 B.GE	468fc4

    (2124) 0x468f94 SUB	X15, X12, X6

    (2124) 0x468f98 STR	X12, [X25, X2,LSL #3]

    (2124) 0x468f9c ADD	X12, X12, #1

    (2124) 0x468fa0 STR	X2, [X23, X15,LSL #3]

    (2124) 0x468fa4 MOVZ	W2, #2

    (2124) 0x468fa8 STR	X2, [X21, X15,LSL #3]

    (2124) 0x468fac LDR	X19, [X1, X3,LSL #3]

    (2124) 0x468fb0 ADD	X2, X3, #1

    (2124) 0x468fb4 LDR	X15, [X1, X2,LSL #3]

    (2124) 0x468fb8 CMP	X19, X15

    (2124) 0x468fbc B.LT	469004

    (2124) 0x468fc0 B	469040

    (2124) 0x468fc4 LDR	X2, [X21, X15,LSL #3]

    (2124) 0x468fc8 ADD	X2, X2, #2

    (2124) 0x468fcc STR	X2, [X21, X15,LSL #3]

    (2124) 0x468fd0 LDR	X19, [X1, X3,LSL #3]

    (2124) 0x468fd4 ADD	X2, X3, #1

    (2124) 0x468fd8 LDR	X15, [X1, X2,LSL #3]

    (2124) 0x468fdc CMP	X19, X15

    (2124) 0x468fe0 B.LT	469004

    (2124) 0x468fe4 B	469040

      (2126) 0x468fe8 LDR	X27, [X20, X15,LSL #3]

      (2126) 0x468fec ADD	X27, X27, #1

      (2126) 0x468ff0 STR	X27, [X20, X15,LSL #3]

      (2126) 0x468ff4 ADD	X19, X19, #1

      (2126) 0x468ff8 LDR	X15, [X1, X2,LSL #3]

      (2126) 0x468ffc CMP	X19, X15

      (2126) 0x469000 B.GE	469040

      (2126) 0x469004 LDR	X27, [X18, X19,LSL #3]

      (2126) 0x469008 CMP	X27, X22

      (2126) 0x46900c B.EQ	468ff4

      (2126) 0x469010 LDR	X15, [X24, X27,LSL #3]

      (2126) 0x469014 SUBS	X15, X15, X7

      (2126) 0x469018 B.GE	468fe8

      (2126) 0x46901c SUB	X15, X13, X7

      (2126) 0x469020 STR	X13, [X24, X27,LSL #3]

      (2126) 0x469024 ADD	X13, X13, #1

      (2126) 0x469028 ADD	X19, X19, #1

      (2126) 0x46902c STR	X27, [X26, X15,LSL #3]

      (2126) 0x469030 STR	X4, [X20, X15,LSL #3]

      (2126) 0x469034 LDR	X15, [X1, X2,LSL #3]

      (2126) 0x469038 CMP	X19, X15

      (2126) 0x46903c B.LT	469004

    (2124) 0x469040 LDR	X3, [X5, X3,LSL #3]

    (2124) 0x469044 LDR	X15, [X5, X2,LSL #3]

    (2124) 0x469048 CMP	X3, X15

    (2124) 0x46904c B.LT	469084

    (2124) 0x469050 B	468f60

0x469054 HINT	#0

0x469058 HINT	#0

0x46905c HINT	#0

      (2125) 0x469060 SUB	X15, X12, X6

      (2125) 0x469064 STR	X12, [X25, X19,LSL #3]

      (2125) 0x469068 ADD	X12, X12, #1

      (2125) 0x46906c ADD	X3, X3, #1

      (2125) 0x469070 STR	X19, [X23, X15,LSL #3]

      (2125) 0x469074 STR	X4, [X21, X15,LSL #3]

      (2125) 0x469078 LDR	X15, [X5, X2,LSL #3]

      (2125) 0x46907c CMP	X3, X15

      (2125) 0x469080 B.GE	468f60

      (2125) 0x469084 LDR	X19, [X0, X3,LSL #3]

      (2125) 0x469088 LDR	X15, [X25, X19,LSL #3]

      (2125) 0x46908c SUBS	X15, X15, X6

      (2125) 0x469090 B.LT	469060

      (2125) 0x469094 LDR	X19, [X21, X15,LSL #3]

      (2125) 0x469098 ADD	X3, X3, #1

      (2125) 0x46909c ADD	X19, X19, #1

      (2125) 0x4690a0 STR	X19, [X21, X15,LSL #3]

      (2125) 0x4690a4 LDR	X15, [X5, X2,LSL #3]

      (2125) 0x4690a8 CMP	X3, X15

      (2125) 0x4690ac B.LT	469084

    (2124) 0x4690b0 B	468f60

0x4690b4 HINT	#0

0x4690b8 HINT	#0

0x4690bc HINT	#0

  (2122) 0x4690c0 LDUR	X19, [X29, #408]

  (2122) 0x4690c4 CMP	X13, X7

  (2122) 0x4690c8 B.LE	46911c

  (2122) 0x4690cc LDUR	X8, [X29, #440]

  (2122) 0x4690d0 SUB	W15, W13, W7

  (2122) 0x4690d4 ORR	X18, XZR, X7

  (2122) 0x4690d8 LDR	X8, [X8]

  (2122) 0x4690dc TBZ	W15, #0, 469110

  (2122) 0x4690e0 LDUR	X16, [X29, #448]

  (2122) 0x4690e4 LDR	X15, [X20]

  (2122) 0x4690e8 LDR	X16, [X16]

  (2122) 0x4690ec CMP	X15, X16

  (2122) 0x4690f0 B.LT	469108

  (2122) 0x4690f4 LDUR	X16, [X29, #480]

  (2122) 0x4690f8 LDR	X15, [X26]

  (2122) 0x4690fc ADD	X18, X16, #1

  (2122) 0x469100 STUR	X18, [X29, #480]

  (2122) 0x469104 STR	X15, [X8, X16,LSL #3]

  (2122) 0x469108 ADD	X18, X7, #1

  (2122) 0x46910c STR	XZR, [X20]

  (2122) 0x469110 ADD	X15, X7, #1

  (2122) 0x469114 CMP	X13, X15

  (2122) 0x469118 B.NE	469220

  (2122) 0x46911c CMP	X12, X6

  (2122) 0x469120 B.LE	468d40

  (2122) 0x469124 LDR	X8, [X19]

  (2122) 0x469128 SUB	W15, W12, W6

  (2122) 0x46912c ORR	X18, XZR, X6

  (2122) 0x469130 TBZ	W15, #0, 469164

  (2122) 0x469134 LDUR	X16, [X29, #448]

  (2122) 0x469138 LDR	X15, [X21]

  (2122) 0x46913c LDR	X16, [X16]

  (2122) 0x469140 CMP	X15, X16

  (2122) 0x469144 B.LT	46915c

  (2122) 0x469148 LDUR	X16, [X29, #472]

  (2122) 0x46914c LDR	X15, [X23]

  (2122) 0x469150 ADD	X18, X16, #1

  (2122) 0x469154 STUR	X18, [X29, #472]

  (2122) 0x469158 STR	X15, [X8, X16,LSL #3]

  (2122) 0x46915c ADD	X18, X6, #1

  (2122) 0x469160 STR	XZR, [X21]

  (2122) 0x469164 ADD	X15, X6, #1

  (2122) 0x469168 CMP	X12, X15

  (2122) 0x46916c B.EQ	468d40

  (2122) 0x469170 SUB	X16, X12, X18

  (2122) 0x469174 UBFM	X15, X18, #61, #60

  (2122) 0x469178 LDP	X0, X18, [SP, #112]

  (2122) 0x46917c SUB	X15, X15, X6,LSL #3

  (2122) 0x469180 ADD	X18, X18, X15

  (2122) 0x469184 ADD	X0, X0, X15

  (2122) 0x469188 B	46919c

    (2130) 0x46918c STR	XZR, [X0], #16

    (2130) 0x469190 SUBS	X16, X16, #2

    (2130) 0x469194 ADD	X18, X18, #16

    (2130) 0x469198 B.EQ	468d40

    (2130) 0x46919c LDUR	X2, [X29, #448]

    (2130) 0x4691a0 LDUR	X15, [X0, #504]

    (2130) 0x4691a4 LDR	X2, [X2]

    (2130) 0x4691a8 CMP	X15, X2

    (2130) 0x4691ac B.GE	4691cc

    (2130) 0x4691b0 LDUR	X2, [X29, #448]

    (2130) 0x4691b4 STUR	XZR, [X0, #504]

    (2130) 0x4691b8 LDR	X15, [X0]

    (2130) 0x4691bc LDR	X2, [X2]

    (2130) 0x4691c0 CMP	X15, X2

    (2130) 0x4691c4 B.LT	46918c

    (2130) 0x4691c8 B	4691f8

    (2130) 0x4691cc LDUR	X2, [X29, #472]

    (2130) 0x4691d0 LDUR	X15, [X18, #504]

    (2130) 0x4691d4 ADD	X3, X2, #1

    (2130) 0x4691d8 STUR	X3, [X29, #472]

    (2130) 0x4691dc STR	X15, [X8, X2,LSL #3]

    (2130) 0x4691e0 LDUR	X2, [X29, #448]

    (2130) 0x4691e4 STUR	XZR, [X0, #504]

    (2130) 0x4691e8 LDR	X15, [X0]

    (2130) 0x4691ec LDR	X2, [X2]

    (2130) 0x4691f0 CMP	X15, X2

    (2130) 0x4691f4 B.LT	46918c

    (2130) 0x4691f8 LDUR	X2, [X29, #472]

    (2130) 0x4691fc LDR	X15, [X18]

    (2130) 0x469200 ADD	X3, X2, #1

    (2130) 0x469204 STUR	X3, [X29, #472]

    (2130) 0x469208 STR	X15, [X8, X2,LSL #3]

    (2130) 0x46920c B	46918c

0x469210 HINT	#0

0x469214 HINT	#0

0x469218 HINT	#0

0x46921c HINT	#0

(2123) 0x469220 SUB	X16, X13, X18

(2123) 0x469224 UBFM	X15, X18, #61, #60

(2123) 0x469228 LDP	X0, X18, [SP, #128]

(2123) 0x46922c SUB	X15, X15, X7,LSL #3

(2123) 0x469230 ADD	X18, X18, X15

(2123) 0x469234 ADD	X0, X0, X15

(2123) 0x469238 B	469250

0x46923c HINT	#0

(2123) 0x469240 STR	XZR, [X0], #16

(2123) 0x469244 SUBS	X16, X16, #2

(2123) 0x469248 ADD	X18, X18, #16

(2123) 0x46924c B.EQ	46911c

(2123) 0x469250 LDUR	X2, [X29, #448]

(2123) 0x469254 LDUR	X15, [X0, #504]

(2123) 0x469258 LDR	X2, [X2]

(2123) 0x46925c CMP	X15, X2

(2123) 0x469260 B.GE	469280

(2123) 0x469264 LDUR	X2, [X29, #448]

(2123) 0x469268 STUR	XZR, [X0, #504]

(2123) 0x46926c LDR	X15, [X0]

(2123) 0x469270 LDR	X2, [X2]

(2123) 0x469274 CMP	X15, X2

(2123) 0x469278 B.LT	469240

(2123) 0x46927c B	4692ac

(2123) 0x469280 LDUR	X2, [X29, #480]

(2123) 0x469284 LDUR	X15, [X18, #504]

(2123) 0x469288 ADD	X3, X2, #1

(2123) 0x46928c STUR	X3, [X29, #480]

(2123) 0x469290 STR	X15, [X8, X2,LSL #3]

(2123) 0x469294 LDUR	X2, [X29, #448]

(2123) 0x469298 STUR	XZR, [X0, #504]

(2123) 0x46929c LDR	X15, [X0]

(2123) 0x4692a0 LDR	X2, [X2]

(2123) 0x4692a4 CMP	X15, X2

(2123) 0x4692a8 B.LT	469240

(2123) 0x4692ac LDUR	X2, [X29, #480]

(2123) 0x4692b0 LDR	X15, [X18]

(2123) 0x4692b4 ADD	X3, X2, #1

(2123) 0x4692b8 STUR	X3, [X29, #480]

(2123) 0x4692bc STR	X15, [X8, X2,LSL #3]

(2123) 0x4692c0 B	469240

0x4692c4 LDP	X20, X19, [SP, #368]

0x4692c8 LDP	X22, X21, [SP, #352]

0x4692cc LDP	X24, X23, [SP, #336]

0x4692d0 LDP	X26, X25, [SP, #320]

0x4692d4 LDP	X28, X27, [SP, #304]

0x4692d8 LDP	X29, X30, [SP, #288]

0x4692dc ADD	SP, SP, #384

0x4692e0 RET

0x4692e4 HINT	#0

0x4692e8 HINT	#0

0x4692ec HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:1668-2230
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1668-1697,1705-1714,1720-1797,1806,1812-2000,2006-2083,2093-2095,2101-2230.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 67.17 to 59.33 cycles (1.13x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 67.17 to 4.50 cycles (14.93x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1460 bytes. The binary function is storing 464 bytes.

General properties

nb instructions	422
loop length	1688
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

42.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	17.50	17.50	18.42	18.42	18.33	18.33	18.25	18.25	0.00	0.00	0.00	0.00	67.17	66.83	67.00	23.50	23.50
cycles	17.50	17.50	18.42	18.42	18.33	18.33	18.25	18.25	0.00	0.00	0.00	0.00	67.17	66.83	67.00	23.50	23.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	42.13
Overall L1	67.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 67.17 cycles. At this rate:

22% of peak load performance is reached (21.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 467cb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X27, X22, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X28, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X0, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X1, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae70 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X11, X10, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X21, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 467d54 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X12, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X12, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X23, X14, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X20, X13, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X8, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 467d68 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X13, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X13, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X24, XZR, X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X11, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X25, XZR, X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 467dc0 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 467dc4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X10, X11, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 467e54 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X19, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X22, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468180 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 468730 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 467ef8 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 468730 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X2, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X4, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X8, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 468210 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X10, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X9, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4aba90 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 468794 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4687d4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ee7d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #592	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ee7ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #616	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f450 <@plt_start@+0xd0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 46885c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xbac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 46882c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X9, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a9060 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 46884c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a9060 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4ee84c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #616	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f920 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ee85c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X30, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X9, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 468918 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W14, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X13, X13, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X10, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X11, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4688e8 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xc38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
ORR X9, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4692c4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X12, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X12, X13, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468998 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X13, #63, #62	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468998 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468cc0 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4692c4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X12, X15, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X13, X14, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X16, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4689fc <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4692c4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MOVZ W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X26, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X23, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 468d50 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x10a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:1668-2230
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 67.17 to 4.50 cycles (14.93x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1460 bytes. The binary function is storing 464 bytes.

General properties

nb instructions	422
loop length	1688
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

42.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	17.50	17.50	18.42	18.42	18.33	18.33	18.25	18.25	0.00	0.00	0.00	0.00	67.17	66.83	67.00	23.50	23.50
cycles	17.50	17.50	18.42	18.42	18.33	18.33	18.25	18.25	0.00	0.00	0.00	0.00	67.17	66.83	67.00	23.50	23.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	42.13
Overall L1	67.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 67.17 cycles. At this rate:

22% of peak load performance is reached (21.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.91 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 467cb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #288	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X27, X22, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ORR X21, XZR, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X28, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X0, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X1, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae70 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X15, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X11, X10, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STUR X21, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LE 467d54 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X26, X12, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X12, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X23, X14, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X20, X13, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X8, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 467d68 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MADD X12, X9, X28, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X13, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X14, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X13, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X24, XZR, X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X11, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X25, XZR, X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 467dc0 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVN X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 467dc4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X27, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X10, X11, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X11, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 467e54 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X28, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X19, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X22, [X8, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468180 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 468730 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 467ef8 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X22, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 468730 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xa80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X2, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X4, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X5, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X9, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X8, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X9, X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 468210 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x560>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X10, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X10, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X10, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X3, X9, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4aba90 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 468794 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xae4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X11, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X8, X9, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 4687d4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ee7d8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #592	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ee7ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #616	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f450 <@plt_start@+0xd0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ W0, 46885c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xbac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 46882c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X9, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4a9060 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 46884c <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xb9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X0, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a9060 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4ee84c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #616	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f920 <@plt_start@+0x5a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <4ee85c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X30, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X9, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X8, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 468918 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xc68>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W14, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X10, X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X13, X13, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X10, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X12, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X11, X11, X22,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4688e8 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xc38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
ORR X9, XZR, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4692c4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X12, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X12, X13, #60, #59	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X12, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468998 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X13, #63, #62	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X10, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468998 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xce8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X10, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W10, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X10, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.NE 468cc0 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1010>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4692c4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X9, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X12, X15, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X13, X14, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X16, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4689fc <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0xd4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP X22, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4692c4 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x1614>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MOVZ W4, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X26, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X20, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X23, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X21, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B 468d50 <hypre_BoomerAMGCreate2ndS.omp_outlined.16+0x10a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS.omp_outlined.16–	1.82	0.34
○Loop 2140 - par_strength.c:1951-1953 - exec	0.06	0.01
○Loop 2159 - par_strength.c:1691-1693 - exec	0.02	0.01
○Loop 2138 - par_strength.c:1978-1984 - exec	0.00	0.00
▼Loop 2123 - par_strength.c:2095-2230 - exec–	0.00	0.00
▼Loop 2122 - par_strength.c:2095-2230 - exec–	0.00	0.00
○Loop 2130 - par_strength.c:2224-2230 - exec	0.00	0.00
▼Loop 2127 - par_strength.c:2106-2158 - exec–	0.00	0.00
○Loop 2129 - par_strength.c:2124-2139 - exec	0.00	0.00
○Loop 2128 - par_strength.c:2143-2158 - exec	0.00	0.00
▼Loop 2124 - par_strength.c:2163-2211 - exec–	0.00	0.00
○Loop 2125 - par_strength.c:2199-2211 - exec	0.00	0.00
○Loop 2126 - par_strength.c:2181-2195 - exec	0.00	0.00
○Loop 2139 - par_strength.c:1955-1957 - exec	0.00	0.00
▼Loop 2132 - par_strength.c:2000-2083 - exec–	0.00	0.00
▼Loop 2131 - par_strength.c:2000-2053 - exec–	0.00	0.00
▼Loop 2135 - par_strength.c:2011-2048 - exec–	0.13	0.02
○Loop 2137 - par_strength.c:2024-2034 - exec	0.76	0.12
○Loop 2136 - par_strength.c:2038-2048 - exec	0.00	0.00
○Loop 2134 - par_strength.c:2066-2073 - exec	0.00	0.00
○Loop 2133 - par_strength.c:2076-2083 - exec	0.00	0.00
▼Loop 2142 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2143 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2141 - par_strength.c:1806-1941 - exec–	0.00	0.00
▼Loop 2144 - par_strength.c:1877-1922 - exec–	0.00	0.00
○Loop 2145 - par_strength.c:1911-1922 - exec	0.00	0.00
○Loop 2146 - par_strength.c:1894-1907 - exec	0.00	0.00
▼Loop 2147 - par_strength.c:1823-1872 - exec–	0.00	0.00
○Loop 2149 - par_strength.c:1840-1854 - exec	0.00	0.00
○Loop 2148 - par_strength.c:1858-1872 - exec	0.00	0.00
○Loop 2150 - par_strength.c:1935-1941 - exec	0.00	0.00
▼Loop 2152 - par_strength.c:1714-1797 - exec–	0.00	0.00
▼Loop 2151 - par_strength.c:1714-1770 - exec–	0.01	0.01
▼Loop 2154 - par_strength.c:1731-1765 - exec–	0.12	0.02
○Loop 2156 - par_strength.c:1743-1752 - exec	0.72	0.11
○Loop 2155 - par_strength.c:1756-1765 - exec	0.00	0.00
○Loop 2157 - par_strength.c:1791-1797 - exec	0.00	0.00
○Loop 2153 - par_strength.c:1782-1788 - exec	0.00	0.00
○Loop 2158 - par_strength.c:1695-1697 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code