OV - exec - Function hypre_BoomerAMGCreateS.omp

	Function: hypre_BoomerAMGCreateS.omp_outlined.2	Module: exec	Source: par_strength.c:246-513 [...]	Coverage (incl. loops): 0.38% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 246 - 513

--------------------------------------------------------------------------------

246: #pragma omp parallel private(i,diag,row_scale,row_sum,jA,jS)

247: #endif

248:    {

249:    HYPRE_Int start, stop;

250:    hypre_GetSimpleThreadPartition(&start, &stop, num_variables);

251:    HYPRE_Int jS_diag = 0, jS_offd = 0;

252:

253:    for (i = start; i < stop; i++)

254:    {

255:       S_diag_i[i] = jS_diag;

256:       if (num_cols_offd)

257:       {

258:          S_offd_i[i] = jS_offd;

259:       }

260:

261:       diag = A_diag_data[A_diag_i[i]];

262:

263:       /* compute scaling factor and row sum */

264:       row_scale = 0.0;

265:       row_sum = diag;

266:       if (num_functions > 1)

267:       {

268:          if (diag < 0)

269:          {

270:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

271:             {

272:                if (dof_func[i] == dof_func[A_diag_j[jA]])

273:                {

274:                   row_scale = hypre_max(row_scale, A_diag_data[jA]);

275:                   row_sum += A_diag_data[jA];

276:                }

277:             }

278:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

279:             {

280:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

281:                {

282:                   row_scale = hypre_max(row_scale, A_offd_data[jA]);

283:                   row_sum += A_offd_data[jA];

[...]

289:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

290:             {

291:                if (dof_func[i] == dof_func[A_diag_j[jA]])

292:                {

293:                   row_scale = hypre_min(row_scale, A_diag_data[jA]);

294:                   row_sum += A_diag_data[jA];

295:                }

296:             }

297:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

298:             {

299:                if (dof_func[i] == dof_func_offd[A_offd_j[jA]])

300:                {

301:                   row_scale = hypre_min(row_scale, A_offd_data[jA]);

302:                   row_sum += A_offd_data[jA];

[...]

309:          if (diag < 0)

310:          {

311:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

312:             {

313:                row_scale = hypre_max(row_scale, A_diag_data[jA]);

314:                row_sum += A_diag_data[jA];

315:             }

316:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

317:             {

318:                row_scale = hypre_max(row_scale, A_offd_data[jA]);

319:                row_sum += A_offd_data[jA];

320:             }

321:          }

322:          else

323:          {

324:             for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

325:             {

326:                row_scale = hypre_min(row_scale, A_diag_data[jA]);

327:                row_sum += A_diag_data[jA];

328:             }

329:             for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

330:             {

331:                row_scale = hypre_min(row_scale, A_offd_data[jA]);

332:                row_sum += A_offd_data[jA];

333:             }

334:          } /* diag >= 0*/

335:       } /* num_functions <= 1 */

336:

337:       jS_diag += A_diag_i[i + 1] - A_diag_i[i] - 1;

338:       jS_offd += A_offd_i[i + 1] - A_offd_i[i];

339:

340:       /* compute row entries of S */

341:       S_temp_diag_j[A_diag_i[i]] = -1;

342:       if ((fabs(row_sum) > fabs(diag)*max_row_sum) && (max_row_sum < 1.0))

343:       {

344:          /* make all dependencies weak */

345:          for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

346:          {

347:             S_temp_diag_j[jA] = -1;

348:          }

349:          jS_diag -= A_diag_i[i + 1] - (A_diag_i[i] + 1);

350:

351:          for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

352:          {

353:             S_temp_offd_j[jA] = -1;

354:          }

355:          jS_offd -= A_offd_i[i + 1] - A_offd_i[i];

356:       }

357:       else

358:       {

359:          if (num_functions > 1)

360:          {

361:             if (diag < 0)

362:             {

363:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

364:                {

365:                   if (A_diag_data[jA] <= strength_threshold * row_scale

366:                       || dof_func[i] != dof_func[A_diag_j[jA]])

367:                   {

368:                      S_temp_diag_j[jA] = -1;

369:                      --jS_diag;

370:                   }

371:                   else

372:                   {

373:                      S_temp_diag_j[jA] = A_diag_j[jA];

374:                   }

375:                }

376:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

377:                {

378:                   if (A_offd_data[jA] <= strength_threshold * row_scale

379:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

380:                   {

381:                      S_temp_offd_j[jA] = -1;

382:                      --jS_offd;

383:                   }

384:                   else

385:                   {

386:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

392:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

393:                {

394:                   if (A_diag_data[jA] >= strength_threshold * row_scale

395:                       || dof_func[i] != dof_func[A_diag_j[jA]])

396:                   {

397:                      S_temp_diag_j[jA] = -1;

398:                      --jS_diag;

399:                   }

400:                   else

401:                   {

402:                      S_temp_diag_j[jA] = A_diag_j[jA];

403:                   }

404:                }

405:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

406:                {

407:                   if (A_offd_data[jA] >= strength_threshold * row_scale

408:                       || dof_func[i] != dof_func_offd[A_offd_j[jA]])

409:                   {

410:                      S_temp_offd_j[jA] = -1;

411:                      --jS_offd;

412:                   }

413:                   else

414:                   {

415:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

422:             if (diag < 0)

423:             {

424:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

425:                {

426:                   if (A_diag_data[jA] <= strength_threshold * row_scale)

427:                   {

428:                      S_temp_diag_j[jA] = -1;

429:                      --jS_diag;

430:                   }

431:                   else

432:                   {

433:                      S_temp_diag_j[jA] = A_diag_j[jA];

434:                   }

435:                }

436:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

437:                {

438:                   if (A_offd_data[jA] <= strength_threshold * row_scale)

439:                   {

440:                      S_temp_offd_j[jA] = -1;

441:                      --jS_offd;

442:                   }

443:                   else

444:                   {

445:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

451:                for (jA = A_diag_i[i]+1; jA < A_diag_i[i+1]; jA++)

452:                {

453:                   if (A_diag_data[jA] >= strength_threshold * row_scale)

454:                   {

455:                      S_temp_diag_j[jA] = -1;

456:                      --jS_diag;

457:                   }

458:                   else

459:                   {

460:                      S_temp_diag_j[jA] = A_diag_j[jA];

461:                   }

462:                }

463:                for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

464:                {

465:                   if (A_offd_data[jA] >= strength_threshold * row_scale)

466:                   {

467:                      S_temp_offd_j[jA] = -1;

468:                      --jS_offd;

469:                   }

470:                   else

471:                   {

472:                      S_temp_offd_j[jA] = A_offd_j[jA];

[...]

480:    hypre_prefix_sum_pair(&jS_diag, S_diag_i + num_variables, &jS_offd, S_offd_i + num_variables, prefix_sum_workspace);

[...]

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

0x463b60 SUB	SP, SP, #272

0x463b64 STP	X29, X30, [SP, #176]

0x463b68 STP	X28, X27, [SP, #192]

0x463b6c STP	X26, X25, [SP, #208]

0x463b70 STP	X24, X23, [SP, #224]

0x463b74 STP	X22, X21, [SP, #240]

0x463b78 STP	X20, X19, [SP, #256]

0x463b7c ADD	X29, SP, #176

0x463b80 LDR	X8, [X29, #184]

0x463b84 STR	X2, [SP, #16]

0x463b88 LDR	X2, [X2]

0x463b8c SUB	X0, X29, #16

0x463b90 SUB	X1, X29, #24

0x463b94 ORR	X24, XZR, X6

0x463b98 ORR	X22, XZR, X4

0x463b9c ORR	X19, XZR, X3

0x463ba0 LDR	X25, [X29, #168]

0x463ba4 STR	X7, [SP, #48]

0x463ba8 STUR	X5, [X29, #456]

0x463bac STR	X8, [SP, #24]

0x463bb0 LDR	X8, [X29, #152]

0x463bb4 STR	X8, [SP, #32]

0x463bb8 LDR	X8, [X29, #120]

0x463bbc STR	X8, [SP, #40]

0x463bc0 BL	4aae70

0x463bc4 LDP	X9, X12, [X29, #1000]

0x463bc8 LDR	X8, [X19]

0x463bcc STP	XZR, XZR, [X29, #984]

0x463bd0 STR	X19, [SP, #8]

0x463bd4 CMP	X12, X9

0x463bd8 B.GE	464774

0x463bdc LDUR	X11, [X29, #456]

0x463be0 LDP	X13, X3, [X29, #136]

0x463be4 LDR	X14, [X29, #176]

0x463be8 MOVI	D2, #0

0x463bec FMOV	D3, #1.0000000

0x463bf0 MOVN	X26, #0

0x463bf4 ORR	X9, XZR, XZR

0x463bf8 ORR	X10, XZR, XZR

0x463bfc LDR	X5, [X29, #160]

0x463c00 LDP	X16, X15, [X29, #104]

0x463c04 LDR	X0, [X24]

0x463c08 LDR	X6, [X29, #128]

0x463c0c LDR	X17, [X29, #96]

0x463c10 LDR	X30, [X25]

0x463c14 LDR	X18, [X11]

0x463c18 LDR	X11, [SP, #48]

0x463c1c STUR	X3, [X29, #464]

0x463c20 LDR	X3, [X3]

0x463c24 LDR	X7, [X15]

0x463c28 LDR	D0, [X5]

0x463c2c LDR	D1, [X14]

0x463c30 LDR	X19, [X13]

0x463c34 LDR	X4, [X16]

0x463c38 STUR	X6, [X29, #448]

0x463c3c LDR	X6, [X6]

0x463c40 LDR	X1, [X11]

0x463c44 LDR	X11, [SP, #40]

0x463c48 LDR	X2, [X11]

0x463c4c LDR	X11, [SP, #32]

0x463c50 STP	X19, X7, [X29, #944]

0x463c54 LDR	X24, [X11]

0x463c58 ADD	X11, X0, #16

0x463c5c STR	X11, [SP, #88]

0x463c60 ADD	X11, X3, #16

0x463c64 STR	X11, [SP, #80]

0x463c68 ADD	X11, X0, #8

0x463c6c STR	X11, [SP, #72]

0x463c70 ADD	X11, X7, #8

0x463c74 STR	X11, [SP, #64]

0x463c78 ADD	X11, X19, #8

0x463c7c STR	X11, [SP, #56]

0x463c80 B	463c9c

    (2030) 0x463c84 SUB	X11, X14, X5

    (2030) 0x463c88 ADD	X9, X11, X9

    (2030) 0x463c8c STUR	X9, [X29, #472]

    (2030) 0x463c90 LDUR	X11, [X29, #488]

    (2030) 0x463c94 CMP	X12, X11

    (2030) 0x463c98 B.GE	464774

    (2030) 0x463c9c STR	X10, [X8, X12,LSL #3]

    (2030) 0x463ca0 ORR	X27, XZR, X12

    (2030) 0x463ca4 LDR	X12, [X22]

    (2030) 0x463ca8 CBZ	X12, 463cb0

    (2030) 0x463cac STR	X9, [X18, X27,LSL #3]

    (2030) 0x463cb0 LDR	X19, [X1, X27,LSL #3]

    (2030) 0x463cb4 ADD	X12, X27, #1

    (2030) 0x463cb8 LDR	X14, [X17]

    (2030) 0x463cbc MOVI	D4, #0

    (2030) 0x463cc0 LDR	X28, [X1, X12,LSL #3]

    (2030) 0x463cc4 LDR	D5, [X0, X19,LSL #3]

    (2030) 0x463cc8 ADD	X20, X19, #1

    (2030) 0x463ccc FMOV	D6, D5

    (2030) 0x463cd0 CMP	X14, #2

    (2030) 0x463cd4 B.LT	463d2c

    (2030) 0x463cd8 FCMP	D5, #0

    (2030) 0x463cdc B.PL	463e80

    (2030) 0x463ce0 CMP	X20, X28

    (2030) 0x463ce4 B.GE	464024

    (2030) 0x463ce8 LDR	X21, [X4, X27,LSL #3]

    (2030) 0x463cec SUB	W14, W19, W28

    (2030) 0x463cf0 TBNZ	W14, #0, 464014

    (2030) 0x463cf4 LDUR	X11, [X29, #440]

    (2030) 0x463cf8 FMOV	D6, D5

    (2030) 0x463cfc LDR	X14, [X11, X20,LSL #3]

    (2030) 0x463d00 LDR	X14, [X4, X14,LSL #3]

    (2030) 0x463d04 CMP	X21, X14

    (2030) 0x463d08 B.NE	463d18

    (2030) 0x463d0c LDR	D6, [X0, X20,LSL #3]

    (2030) 0x463d10 FMAXNM	D4, D6, D2

    (2030) 0x463d14 FADD	D6, D5, D6

    (2030) 0x463d18 ADD	X20, X19, #2

    (2030) 0x463d1c SUB	X14, X28, #2

    (2030) 0x463d20 CMP	X14, X19

    (2030) 0x463d24 B.EQ	464024

    (2030) 0x463d28 B	4640a4

    (2030) 0x463d2c FCMP	D5, #0

    (2030) 0x463d30 B.PL	463ee0

    (2030) 0x463d34 CMP	X20, X28

    (2030) 0x463d38 B.GE	463de0

    (2030) 0x463d3c ORN	W11, WZR, W19

    (2030) 0x463d40 FMOV	D6, D5

    (2030) 0x463d44 ADD	W11, W28, W11

    (2030) 0x463d48 ANDS	X14, X11, #4160

    (2030) 0x463d4c B.EQ	463d7c

    (2030) 0x463d50 HINT	#0

    (2030) 0x463d54 HINT	#0

    (2030) 0x463d58 HINT	#0

    (2030) 0x463d5c HINT	#0

      (2038) 0x463d60 LDR	D7, [X0, X20,LSL #3]

      (2038) 0x463d64 ADD	X20, X20, #1

      (2038) 0x463d68 FCMP	D4, D7

      (2038) 0x463d6c FADD	D6, D6, D7

      (2038) 0x463d70 FCSEL	D4, D7, D4, #4

      (2038) 0x463d74 SUBS	X14, X14, #1

      (2038) 0x463d78 B.NE	463d60

    (2030) 0x463d7c SUB	X11, X28, X19

    (2030) 0x463d80 SUB	X11, X11, #2

    (2030) 0x463d84 CMP	X11, #3

    (2030) 0x463d88 B.CC	463de0

    (2030) 0x463d8c LDR	X11, [SP, #88]

    (2030) 0x463d90 SUB	X14, X28, X20

    (2030) 0x463d94 ADD	X5, X11, X20,LSL #3

    (2030) 0x463d98 HINT	#0

    (2030) 0x463d9c HINT	#0

      (2037) 0x463da0 LDP	D7, D16, [X5, #1008]

      (2037) 0x463da4 FCMP	D4, D7

      (2037) 0x463da8 FADD	D6, D6, D7

      (2037) 0x463dac FCSEL	D4, D7, D4, #4

      (2037) 0x463db0 FADD	D6, D6, D16

      (2037) 0x463db4 FCMP	D4, D16

      (2037) 0x463db8 FCSEL	D4, D16, D4, #4

      (2037) 0x463dbc LDP	D7, D16, [X5], #32

      (2037) 0x463dc0 FCMP	D4, D7

      (2037) 0x463dc4 FADD	D6, D6, D7

      (2037) 0x463dc8 FCSEL	D4, D7, D4, #4

      (2037) 0x463dcc FADD	D6, D6, D16

      (2037) 0x463dd0 FCMP	D4, D16

      (2037) 0x463dd4 FCSEL	D4, D16, D4, #4

      (2037) 0x463dd8 SUBS	X14, X14, #4

      (2037) 0x463ddc B.NE	463da0

    (2030) 0x463de0 LDR	X21, [X2, X27,LSL #3]

    (2030) 0x463de4 LDR	X20, [X2, X12,LSL #3]

    (2030) 0x463de8 SUBS	X14, X21, X20

    (2030) 0x463dec B.GE	4642a8

    (2030) 0x463df0 SUB	W11, W20, W21

    (2030) 0x463df4 ORR	X23, XZR, X21

    (2030) 0x463df8 ANDS	X5, X11, #4160

    (2030) 0x463dfc B.EQ	463e1c

      (2036) 0x463e00 LDR	D7, [X3, X23,LSL #3]

      (2036) 0x463e04 ADD	X23, X23, #1

      (2036) 0x463e08 FCMP	D4, D7

      (2036) 0x463e0c FADD	D6, D6, D7

      (2036) 0x463e10 FCSEL	D4, D7, D4, #4

      (2036) 0x463e14 SUBS	X5, X5, #1

      (2036) 0x463e18 B.NE	463e00

    (2030) 0x463e1c CMN	X14, #4

    (2030) 0x463e20 B.HI	4642a8

    (2030) 0x463e24 LDR	X11, [SP, #80]

    (2030) 0x463e28 ADD	X14, X11, X23,LSL #3

      (2035) 0x463e2c LDP	D7, D16, [X14, #1008]

      (2035) 0x463e30 ADD	X23, X23, #4

      (2035) 0x463e34 FCMP	D4, D7

      (2035) 0x463e38 FADD	D6, D6, D7

      (2035) 0x463e3c FCSEL	D4, D7, D4, #4

      (2035) 0x463e40 FADD	D6, D6, D16

      (2035) 0x463e44 FCMP	D4, D16

      (2035) 0x463e48 FCSEL	D4, D16, D4, #4

      (2035) 0x463e4c LDP	D7, D16, [X14], #32

      (2035) 0x463e50 FCMP	D4, D7

      (2035) 0x463e54 FADD	D6, D6, D7

      (2035) 0x463e58 FCSEL	D4, D7, D4, #4

      (2035) 0x463e5c FADD	D6, D6, D16

      (2035) 0x463e60 FCMP	D4, D16

      (2035) 0x463e64 FCSEL	D4, D16, D4, #4

      (2035) 0x463e68 CMP	X20, X23

      (2035) 0x463e6c B.NE	463e2c

    (2030) 0x463e70 B	4642a8

0x463e74 HINT	#0

0x463e78 HINT	#0

0x463e7c HINT	#0

    (2030) 0x463e80 CMP	X20, X28

    (2030) 0x463e84 B.GE	46406c

    (2030) 0x463e88 LDR	X21, [X4, X27,LSL #3]

    (2030) 0x463e8c SUB	W14, W19, W28

    (2030) 0x463e90 TBNZ	W14, #0, 46405c

    (2030) 0x463e94 LDUR	X11, [X29, #440]

    (2030) 0x463e98 FMOV	D6, D5

    (2030) 0x463e9c LDR	X14, [X11, X20,LSL #3]

    (2030) 0x463ea0 LDR	X14, [X4, X14,LSL #3]

    (2030) 0x463ea4 CMP	X21, X14

    (2030) 0x463ea8 B.NE	463ebc

    (2030) 0x463eac LDR	D6, [X0, X20,LSL #3]

    (2030) 0x463eb0 FCMP	D6, #0

    (2030) 0x463eb4 FCSEL	D4, D2, D6, #12

    (2030) 0x463eb8 FADD	D6, D5, D6

    (2030) 0x463ebc ADD	X20, X19, #2

    (2030) 0x463ec0 SUB	X14, X28, #2

    (2030) 0x463ec4 CMP	X14, X19

    (2030) 0x463ec8 B.EQ	46406c

    (2030) 0x463ecc B	4641f4

0x463ed0 HINT	#0

0x463ed4 HINT	#0

0x463ed8 HINT	#0

0x463edc HINT	#0

    (2030) 0x463ee0 CMP	X20, X28

    (2030) 0x463ee4 B.GE	463f80

    (2030) 0x463ee8 ORN	W11, WZR, W19

    (2030) 0x463eec FMOV	D6, D5

    (2030) 0x463ef0 ADD	W11, W28, W11

    (2030) 0x463ef4 ANDS	X14, X11, #4160

    (2030) 0x463ef8 B.EQ	463f1c

    (2030) 0x463efc HINT	#0

      (2034) 0x463f00 LDR	D7, [X0, X20,LSL #3]

      (2034) 0x463f04 ADD	X20, X20, #1

      (2034) 0x463f08 FCMP	D4, D7

      (2034) 0x463f0c FADD	D6, D6, D7

      (2034) 0x463f10 FCSEL	D4, D4, D7, #4

      (2034) 0x463f14 SUBS	X14, X14, #1

      (2034) 0x463f18 B.NE	463f00

    (2030) 0x463f1c SUB	X11, X28, X19

    (2030) 0x463f20 SUB	X11, X11, #2

    (2030) 0x463f24 CMP	X11, #3

    (2030) 0x463f28 B.CC	463f80

    (2030) 0x463f2c LDR	X11, [SP, #88]

    (2030) 0x463f30 SUB	X14, X28, X20

    (2030) 0x463f34 ADD	X5, X11, X20,LSL #3

    (2030) 0x463f38 HINT	#0

    (2030) 0x463f3c HINT	#0

      (2033) 0x463f40 LDP	D7, D16, [X5, #1008]

      (2033) 0x463f44 FCMP	D4, D7

      (2033) 0x463f48 FADD	D6, D6, D7

      (2033) 0x463f4c FCSEL	D4, D4, D7, #4

      (2033) 0x463f50 FADD	D6, D6, D16

      (2033) 0x463f54 FCMP	D4, D16

      (2033) 0x463f58 FCSEL	D4, D4, D16, #4

      (2033) 0x463f5c LDP	D7, D16, [X5], #32

      (2033) 0x463f60 FCMP	D4, D7

      (2033) 0x463f64 FADD	D6, D6, D7

      (2033) 0x463f68 FCSEL	D4, D4, D7, #4

      (2033) 0x463f6c FADD	D6, D6, D16

      (2033) 0x463f70 FCMP	D4, D16

      (2033) 0x463f74 FCSEL	D4, D4, D16, #4

      (2033) 0x463f78 SUBS	X14, X14, #4

      (2033) 0x463f7c B.NE	463f40

    (2030) 0x463f80 LDR	X21, [X2, X27,LSL #3]

    (2030) 0x463f84 LDR	X20, [X2, X12,LSL #3]

    (2030) 0x463f88 SUBS	X14, X21, X20

    (2030) 0x463f8c B.GE	4642a8

    (2030) 0x463f90 SUB	W11, W20, W21

    (2030) 0x463f94 ORR	X23, XZR, X21

    (2030) 0x463f98 ANDS	X5, X11, #4160

    (2030) 0x463f9c B.EQ	463fbc

      (2032) 0x463fa0 LDR	D7, [X3, X23,LSL #3]

      (2032) 0x463fa4 ADD	X23, X23, #1

      (2032) 0x463fa8 FCMP	D4, D7

      (2032) 0x463fac FADD	D6, D6, D7

      (2032) 0x463fb0 FCSEL	D4, D4, D7, #4

      (2032) 0x463fb4 SUBS	X5, X5, #1

      (2032) 0x463fb8 B.NE	463fa0

    (2030) 0x463fbc CMN	X14, #4

    (2030) 0x463fc0 B.HI	4642a8

    (2030) 0x463fc4 LDR	X11, [SP, #80]

    (2030) 0x463fc8 ADD	X14, X11, X23,LSL #3

      (2031) 0x463fcc LDP	D7, D16, [X14, #1008]

      (2031) 0x463fd0 ADD	X23, X23, #4

      (2031) 0x463fd4 FCMP	D4, D7

      (2031) 0x463fd8 FADD	D6, D6, D7

      (2031) 0x463fdc FCSEL	D4, D4, D7, #4

      (2031) 0x463fe0 FADD	D6, D6, D16

      (2031) 0x463fe4 FCMP	D4, D16

      (2031) 0x463fe8 FCSEL	D4, D4, D16, #4

      (2031) 0x463fec LDP	D7, D16, [X14], #32

      (2031) 0x463ff0 FCMP	D4, D7

      (2031) 0x463ff4 FADD	D6, D6, D7

      (2031) 0x463ff8 FCSEL	D4, D4, D7, #4

      (2031) 0x463ffc FADD	D6, D6, D16

      (2031) 0x464000 FCMP	D4, D16

      (2031) 0x464004 FCSEL	D4, D4, D16, #4

      (2031) 0x464008 CMP	X20, X23

      (2031) 0x46400c B.NE	463fcc

    (2030) 0x464010 B	4642a8

    (2030) 0x464014 FMOV	D6, D5

    (2030) 0x464018 SUB	X14, X28, #2

    (2030) 0x46401c CMP	X14, X19

    (2030) 0x464020 B.NE	4640a4

    (2030) 0x464024 LDR	X21, [X2, X27,LSL #3]

    (2030) 0x464028 LDR	X20, [X2, X12,LSL #3]

    (2030) 0x46402c CMP	X20, X21

    (2030) 0x464030 B.LE	4642a8

    (2030) 0x464034 LDUR	X11, [X29, #464]

    (2030) 0x464038 LDR	X23, [X4, X27,LSL #3]

    (2030) 0x46403c SUB	W14, W20, W21

    (2030) 0x464040 LDR	X5, [X11]

    (2030) 0x464044 TBNZ	W14, #0, 464134

    (2030) 0x464048 ORR	X7, XZR, X21

    (2030) 0x46404c ADD	X14, X21, #1

    (2030) 0x464050 CMP	X20, X14

    (2030) 0x464054 B.NE	464168

    (2030) 0x464058 B	4642a8

    (2030) 0x46405c FMOV	D6, D5

    (2030) 0x464060 SUB	X14, X28, #2

    (2030) 0x464064 CMP	X14, X19

    (2030) 0x464068 B.NE	4641f4

    (2030) 0x46406c LDR	X21, [X2, X27,LSL #3]

    (2030) 0x464070 LDR	X20, [X2, X12,LSL #3]

    (2030) 0x464074 CMP	X20, X21

    (2030) 0x464078 B.LE	4642a8

    (2030) 0x46407c LDUR	X11, [X29, #464]

    (2030) 0x464080 LDR	X23, [X4, X27,LSL #3]

    (2030) 0x464084 LDR	X5, [X11]

    (2030) 0x464088 SUB	W11, W20, W21

    (2030) 0x46408c TBNZ	W11, #0, 464274

    (2030) 0x464090 ORR	X7, XZR, X21

    (2030) 0x464094 ADD	X11, X21, #1

    (2030) 0x464098 CMP	X20, X11

    (2030) 0x46409c B.EQ	4642a8

  (2040) 0x4640a0 B	4646e8

    (2030) 0x4640a4 LDR	X11, [SP, #72]

    (2030) 0x4640a8 SUB	X23, X28, X20

    (2030) 0x4640ac ADD	X14, X11, X20,LSL #3

    (2030) 0x4640b0 LDR	X11, [SP, #64]

    (2030) 0x4640b4 ADD	X20, X11, X20,LSL #3

    (2030) 0x4640b8 B	4640d0

0x4640bc HINT	#0

      (2043) 0x4640c0 ADD	X20, X20, #16

      (2043) 0x4640c4 SUBS	X23, X23, #2

      (2043) 0x4640c8 ADD	X14, X14, #16

      (2043) 0x4640cc B.EQ	464024

      (2043) 0x4640d0 LDUR	X5, [X20, #504]

      (2043) 0x4640d4 LDR	X5, [X4, X5,LSL #3]

      (2043) 0x4640d8 CMP	X21, X5

      (2043) 0x4640dc B.EQ	464100

      (2043) 0x4640e0 LDR	X5, [X20]

      (2043) 0x4640e4 LDR	X5, [X4, X5,LSL #3]

      (2043) 0x4640e8 CMP	X21, X5

      (2043) 0x4640ec B.NE	4640c0

      (2043) 0x4640f0 B	464120

0x4640f4 HINT	#0

0x4640f8 HINT	#0

0x4640fc HINT	#0

      (2043) 0x464100 LDUR	D7, [X14, #504]

      (2043) 0x464104 FCMP	D4, D7

      (2043) 0x464108 FADD	D6, D6, D7

      (2043) 0x46410c FCSEL	D4, D7, D4, #4

      (2043) 0x464110 LDR	X5, [X20]

      (2043) 0x464114 LDR	X5, [X4, X5,LSL #3]

      (2043) 0x464118 CMP	X21, X5

      (2043) 0x46411c B.NE	4640c0

      (2043) 0x464120 LDR	D7, [X14]

      (2043) 0x464124 FCMP	D4, D7

      (2043) 0x464128 FADD	D6, D6, D7

      (2043) 0x46412c FCSEL	D4, D7, D4, #4

      (2043) 0x464130 B	4640c0

    (2030) 0x464134 LDUR	X11, [X29, #432]

    (2030) 0x464138 LDR	X14, [X11, X21,LSL #3]

    (2030) 0x46413c LDR	X14, [X6, X14,LSL #3]

    (2030) 0x464140 CMP	X23, X14

    (2030) 0x464144 B.NE	464158

    (2030) 0x464148 LDR	D7, [X5, X21,LSL #3]

    (2030) 0x46414c FCMP	D4, D7

    (2030) 0x464150 FADD	D6, D6, D7

    (2030) 0x464154 FCSEL	D4, D7, D4, #4

    (2030) 0x464158 ADD	X7, X21, #1

    (2030) 0x46415c ADD	X14, X21, #1

    (2030) 0x464160 CMP	X20, X14

    (2030) 0x464164 B.EQ	4642a8

    (2030) 0x464168 LDR	X11, [SP, #56]

    (2030) 0x46416c ADD	X5, X5, X7,LSL #3

    (2030) 0x464170 SUB	X14, X20, X7

    (2030) 0x464174 ADD	X5, X5, #8

    (2030) 0x464178 ADD	X7, X11, X7,LSL #3

    (2030) 0x46417c B	464190

      (2042) 0x464180 SUBS	X14, X14, #2

      (2042) 0x464184 ADD	X5, X5, #16

      (2042) 0x464188 ADD	X7, X7, #16

      (2042) 0x46418c B.EQ	4642a8

      (2042) 0x464190 LDUR	X11, [X7, #504]

      (2042) 0x464194 LDR	X11, [X6, X11,LSL #3]

      (2042) 0x464198 CMP	X23, X11

      (2042) 0x46419c B.EQ	4641c0

      (2042) 0x4641a0 LDR	X11, [X7]

      (2042) 0x4641a4 LDR	X11, [X6, X11,LSL #3]

      (2042) 0x4641a8 CMP	X23, X11

      (2042) 0x4641ac B.NE	464180

      (2042) 0x4641b0 B	4641e0

0x4641b4 HINT	#0

0x4641b8 HINT	#0

0x4641bc HINT	#0

      (2042) 0x4641c0 LDUR	D7, [X5, #504]

      (2042) 0x4641c4 FCMP	D4, D7

      (2042) 0x4641c8 FADD	D6, D6, D7

      (2042) 0x4641cc FCSEL	D4, D7, D4, #4

      (2042) 0x4641d0 LDR	X11, [X7]

      (2042) 0x4641d4 LDR	X11, [X6, X11,LSL #3]

      (2042) 0x4641d8 CMP	X23, X11

      (2042) 0x4641dc B.NE	464180

      (2042) 0x4641e0 LDR	D7, [X5]

      (2042) 0x4641e4 FCMP	D4, D7

      (2042) 0x4641e8 FADD	D6, D6, D7

      (2042) 0x4641ec FCSEL	D4, D7, D4, #4

      (2042) 0x4641f0 B	464180

    (2030) 0x4641f4 LDR	X11, [SP, #72]

    (2030) 0x4641f8 SUB	X23, X28, X20

    (2030) 0x4641fc ADD	X14, X11, X20,LSL #3

    (2030) 0x464200 LDR	X11, [SP, #64]

    (2030) 0x464204 ADD	X20, X11, X20,LSL #3

    (2030) 0x464208 B	46421c

      (2041) 0x46420c ADD	X20, X20, #16

      (2041) 0x464210 SUBS	X23, X23, #2

      (2041) 0x464214 ADD	X14, X14, #16

      (2041) 0x464218 B.EQ	46406c

      (2041) 0x46421c LDUR	X11, [X20, #504]

      (2041) 0x464220 LDR	X11, [X4, X11,LSL #3]

      (2041) 0x464224 CMP	X21, X11

      (2041) 0x464228 B.EQ	464240

      (2041) 0x46422c LDR	X11, [X20]

      (2041) 0x464230 LDR	X11, [X4, X11,LSL #3]

      (2041) 0x464234 CMP	X21, X11

      (2041) 0x464238 B.NE	46420c

      (2041) 0x46423c B	464260

      (2041) 0x464240 LDUR	D7, [X14, #504]

      (2041) 0x464244 FCMP	D4, D7

      (2041) 0x464248 FADD	D6, D6, D7

      (2041) 0x46424c FCSEL	D4, D4, D7, #4

      (2041) 0x464250 LDR	X11, [X20]

      (2041) 0x464254 LDR	X11, [X4, X11,LSL #3]

      (2041) 0x464258 CMP	X21, X11

      (2041) 0x46425c B.NE	46420c

      (2041) 0x464260 LDR	D7, [X14]

      (2041) 0x464264 FCMP	D4, D7

      (2041) 0x464268 FADD	D6, D6, D7

      (2041) 0x46426c FCSEL	D4, D4, D7, #4

      (2041) 0x464270 B	46420c

    (2030) 0x464274 LDUR	X11, [X29, #432]

    (2030) 0x464278 LDR	X11, [X11, X21,LSL #3]

    (2030) 0x46427c LDR	X11, [X6, X11,LSL #3]

    (2030) 0x464280 CMP	X23, X11

    (2030) 0x464284 B.NE	464298

    (2030) 0x464288 LDR	D7, [X5, X21,LSL #3]

    (2030) 0x46428c FCMP	D4, D7

    (2030) 0x464290 FADD	D6, D6, D7

    (2030) 0x464294 FCSEL	D4, D4, D7, #4

    (2030) 0x464298 ADD	X7, X21, #1

    (2030) 0x46429c ADD	X11, X21, #1

    (2030) 0x4642a0 CMP	X20, X11

    (2030) 0x4642a4 B.NE	4646e8

    (2030) 0x4642a8 ORN	X11, XZR, X19

    (2030) 0x4642ac ADD	X10, X28, X10

    (2030) 0x4642b0 FCMP	D0, D3

    (2030) 0x4642b4 ADD	X10, X10, X11

    (2030) 0x4642b8 SUB	X11, X20, X21

    (2030) 0x4642bc ADD	X9, X11, X9

    (2030) 0x4642c0 STP	X9, X10, [X29, #984]

    (2030) 0x4642c4 STR	X26, [X24, X19,LSL #3]

    (2030) 0x4642c8 B.PL	464360

    (2030) 0x4642cc FABS	D7, D5

    (2030) 0x4642d0 FABS	D6, D6

    (2030) 0x4642d4 FMUL	D7, D7, D0

    (2030) 0x4642d8 FCMP	D6, D7

    (2030) 0x4642dc B.LE	464360

    (2030) 0x4642e0 LDR	X11, [X1, X27,LSL #3]

    (2030) 0x4642e4 LDR	X5, [X1, X12,LSL #3]

    (2030) 0x4642e8 ADD	X14, X11, #1

    (2030) 0x4642ec CMP	X14, X5

    (2030) 0x4642f0 B.GE	46431c

    (2030) 0x4642f4 HINT	#0

    (2030) 0x4642f8 HINT	#0

    (2030) 0x4642fc HINT	#0

      (2053) 0x464300 STR	X26, [X24, X14,LSL #3]

      (2053) 0x464304 ADD	X14, X14, #1

      (2053) 0x464308 LDR	X5, [X1, X12,LSL #3]

      (2053) 0x46430c CMP	X14, X5

      (2053) 0x464310 B.LT	464300

    (2030) 0x464314 LDR	X11, [X1, X27,LSL #3]

    (2030) 0x464318 ADD	X14, X11, #1

    (2030) 0x46431c SUB	X11, X14, X5

    (2030) 0x464320 ADD	X10, X11, X10

    (2030) 0x464324 STUR	X10, [X29, #480]

    (2030) 0x464328 LDR	X14, [X2, X27,LSL #3]

    (2030) 0x46432c LDR	X5, [X2, X12,LSL #3]

    (2030) 0x464330 CMP	X14, X5

    (2030) 0x464334 B.GE	463c84

    (2030) 0x464338 HINT	#0

    (2030) 0x46433c HINT	#0

      (2052) 0x464340 STR	X26, [X30, X14,LSL #3]

      (2052) 0x464344 ADD	X14, X14, #1

      (2052) 0x464348 LDR	X5, [X2, X12,LSL #3]

      (2052) 0x46434c CMP	X14, X5

      (2052) 0x464350 B.LT	464340

    (2030) 0x464354 LDR	X14, [X2, X27,LSL #3]

    (2030) 0x464358 B	463c84

0x46435c HINT	#0

    (2030) 0x464360 LDR	X14, [X1, X27,LSL #3]

    (2030) 0x464364 LDR	X11, [X17]

    (2030) 0x464368 ADD	X19, X14, #1

    (2030) 0x46436c LDR	X14, [X1, X12,LSL #3]

    (2030) 0x464370 CMP	X11, #2

    (2030) 0x464374 B.LT	464480

    (2030) 0x464378 FCMP	D5, #0

    (2030) 0x46437c B.PL	464544

    (2030) 0x464380 CMP	X19, X14

    (2030) 0x464384 B.GE	4643f0

    (2030) 0x464388 LDR	X14, [X16]

    (2030) 0x46438c LDR	X5, [X15]

    (2030) 0x464390 FMUL	D5, D4, D1

    (2030) 0x464394 B	4643bc

0x464398 HINT	#0

0x46439c HINT	#0

      (2051) 0x4643a0 SUB	X10, X10, #1

      (2051) 0x4643a4 STR	X26, [X24, X19,LSL #3]

      (2051) 0x4643a8 STUR	X10, [X29, #480]

      (2051) 0x4643ac LDR	X11, [X1, X12,LSL #3]

      (2051) 0x4643b0 ADD	X19, X19, #1

      (2051) 0x4643b4 CMP	X19, X11

      (2051) 0x4643b8 B.GE	4643f0

      (2051) 0x4643bc LDR	D6, [X0, X19,LSL #3]

      (2051) 0x4643c0 FCMP	D6, D5

      (2051) 0x4643c4 B.LS	4643a0

      (2051) 0x4643c8 LDR	X7, [X5, X19,LSL #3]

      (2051) 0x4643cc LDR	X11, [X14, X27,LSL #3]

      (2051) 0x4643d0 LDR	X20, [X14, X7,LSL #3]

      (2051) 0x4643d4 CMP	X11, X20

      (2051) 0x4643d8 B.NE	4643a0

      (2051) 0x4643dc STR	X7, [X24, X19,LSL #3]

      (2051) 0x4643e0 LDR	X11, [X1, X12,LSL #3]

      (2051) 0x4643e4 ADD	X19, X19, #1

      (2051) 0x4643e8 CMP	X19, X11

      (2051) 0x4643ec B.LT	4643bc

    (2030) 0x4643f0 LDR	X14, [X2, X27,LSL #3]

    (2030) 0x4643f4 LDR	X11, [X2, X12,LSL #3]

    (2030) 0x4643f8 CMP	X14, X11

    (2030) 0x4643fc B.GE	463c90

    (2030) 0x464400 LDUR	X11, [X29, #448]

    (2030) 0x464404 LDR	X5, [X16]

    (2030) 0x464408 LDR	X19, [X13]

    (2030) 0x46440c FMUL	D4, D4, D1

    (2030) 0x464410 LDR	X20, [X25]

    (2030) 0x464414 LDR	X7, [X11]

    (2030) 0x464418 B	46443c

0x46441c HINT	#0

      (2050) 0x464420 SUB	X9, X9, #1

      (2050) 0x464424 STR	X26, [X20, X14,LSL #3]

      (2050) 0x464428 STUR	X9, [X29, #472]

      (2050) 0x46442c LDR	X11, [X2, X12,LSL #3]

      (2050) 0x464430 ADD	X14, X14, #1

      (2050) 0x464434 CMP	X14, X11

      (2050) 0x464438 B.GE	463c90

      (2050) 0x46443c LDR	D5, [X3, X14,LSL #3]

      (2050) 0x464440 FCMP	D5, D4

      (2050) 0x464444 B.LS	464420

      (2050) 0x464448 LDR	X21, [X19, X14,LSL #3]

      (2050) 0x46444c LDR	X11, [X5, X27,LSL #3]

      (2050) 0x464450 LDR	X23, [X7, X21,LSL #3]

      (2050) 0x464454 CMP	X11, X23

      (2050) 0x464458 B.NE	464420

      (2050) 0x46445c STR	X21, [X20, X14,LSL #3]

      (2050) 0x464460 LDR	X11, [X2, X12,LSL #3]

      (2050) 0x464464 ADD	X14, X14, #1

      (2050) 0x464468 CMP	X14, X11

      (2050) 0x46446c B.LT	46443c

    (2030) 0x464470 B	463c90

0x464474 HINT	#0

0x464478 HINT	#0

0x46447c HINT	#0

    (2030) 0x464480 FCMP	D5, #0

    (2030) 0x464484 B.PL	464634

    (2030) 0x464488 CMP	X19, X14

    (2030) 0x46448c B.GE	4644e0

    (2030) 0x464490 LDR	X14, [X15]

    (2030) 0x464494 FMUL	D5, D4, D1

    (2030) 0x464498 B	4644b8

0x46449c HINT	#0

      (2047) 0x4644a0 LDR	X11, [X14, X19,LSL #3]

      (2047) 0x4644a4 STR	X11, [X24, X19,LSL #3]

      (2047) 0x4644a8 LDR	X11, [X1, X12,LSL #3]

      (2047) 0x4644ac ADD	X19, X19, #1

      (2047) 0x4644b0 CMP	X19, X11

      (2047) 0x4644b4 B.GE	4644e0

      (2047) 0x4644b8 LDR	D6, [X0, X19,LSL #3]

      (2047) 0x4644bc FCMP	D6, D5

      (2047) 0x4644c0 B.HI	4644a0

      (2047) 0x4644c4 SUB	X10, X10, #1

      (2047) 0x4644c8 STR	X26, [X24, X19,LSL #3]

      (2047) 0x4644cc STUR	X10, [X29, #480]

      (2047) 0x4644d0 LDR	X11, [X1, X12,LSL #3]

      (2047) 0x4644d4 ADD	X19, X19, #1

      (2047) 0x4644d8 CMP	X19, X11

      (2047) 0x4644dc B.LT	4644b8

    (2030) 0x4644e0 LDR	X14, [X2, X27,LSL #3]

    (2030) 0x4644e4 LDR	X11, [X2, X12,LSL #3]

    (2030) 0x4644e8 CMP	X14, X11

    (2030) 0x4644ec B.GE	463c90

    (2030) 0x4644f0 LDR	X5, [X25]

    (2030) 0x4644f4 LDR	X7, [X13]

    (2030) 0x4644f8 FMUL	D4, D4, D1

    (2030) 0x4644fc B	464518

      (2046) 0x464500 LDR	X11, [X7, X14,LSL #3]

      (2046) 0x464504 STR	X11, [X5, X14,LSL #3]

      (2046) 0x464508 LDR	X11, [X2, X12,LSL #3]

      (2046) 0x46450c ADD	X14, X14, #1

      (2046) 0x464510 CMP	X14, X11

      (2046) 0x464514 B.GE	463c90

      (2046) 0x464518 LDR	D5, [X3, X14,LSL #3]

      (2046) 0x46451c FCMP	D5, D4

      (2046) 0x464520 B.HI	464500

      (2046) 0x464524 SUB	X9, X9, #1

      (2046) 0x464528 STR	X26, [X5, X14,LSL #3]

      (2046) 0x46452c STUR	X9, [X29, #472]

      (2046) 0x464530 LDR	X11, [X2, X12,LSL #3]

      (2046) 0x464534 ADD	X14, X14, #1

      (2046) 0x464538 CMP	X14, X11

      (2046) 0x46453c B.LT	464518

    (2030) 0x464540 B	463c90

    (2030) 0x464544 CMP	X19, X14

    (2030) 0x464548 B.GE	4645b0

    (2030) 0x46454c LDR	X14, [X16]

    (2030) 0x464550 LDR	X5, [X15]

    (2030) 0x464554 FMUL	D5, D4, D1

    (2030) 0x464558 B	46457c

0x46455c HINT	#0

      (2049) 0x464560 SUB	X10, X10, #1

      (2049) 0x464564 STR	X26, [X24, X19,LSL #3]

      (2049) 0x464568 STUR	X10, [X29, #480]

      (2049) 0x46456c LDR	X11, [X1, X12,LSL #3]

      (2049) 0x464570 ADD	X19, X19, #1

      (2049) 0x464574 CMP	X19, X11

      (2049) 0x464578 B.GE	4645b0

      (2049) 0x46457c LDR	D6, [X0, X19,LSL #3]

      (2049) 0x464580 FCMP	D6, D5

      (2049) 0x464584 B.GE	464560

      (2049) 0x464588 LDR	X7, [X5, X19,LSL #3]

      (2049) 0x46458c LDR	X11, [X14, X27,LSL #3]

      (2049) 0x464590 LDR	X20, [X14, X7,LSL #3]

      (2049) 0x464594 CMP	X11, X20

      (2049) 0x464598 B.NE	464560

      (2049) 0x46459c STR	X7, [X24, X19,LSL #3]

      (2049) 0x4645a0 LDR	X11, [X1, X12,LSL #3]

      (2049) 0x4645a4 ADD	X19, X19, #1

      (2049) 0x4645a8 CMP	X19, X11

      (2049) 0x4645ac B.LT	46457c

    (2030) 0x4645b0 LDR	X14, [X2, X27,LSL #3]

    (2030) 0x4645b4 LDR	X11, [X2, X12,LSL #3]

    (2030) 0x4645b8 CMP	X14, X11

    (2030) 0x4645bc B.GE	463c90

    (2030) 0x4645c0 LDUR	X11, [X29, #448]

    (2030) 0x4645c4 LDR	X5, [X16]

    (2030) 0x4645c8 LDR	X19, [X13]

    (2030) 0x4645cc FMUL	D4, D4, D1

    (2030) 0x4645d0 LDR	X20, [X25]

    (2030) 0x4645d4 LDR	X7, [X11]

    (2030) 0x4645d8 B	4645fc

0x4645dc HINT	#0

      (2048) 0x4645e0 SUB	X9, X9, #1

      (2048) 0x4645e4 STR	X26, [X20, X14,LSL #3]

      (2048) 0x4645e8 STUR	X9, [X29, #472]

      (2048) 0x4645ec LDR	X11, [X2, X12,LSL #3]

      (2048) 0x4645f0 ADD	X14, X14, #1

      (2048) 0x4645f4 CMP	X14, X11

      (2048) 0x4645f8 B.GE	463c90

      (2048) 0x4645fc LDR	D5, [X3, X14,LSL #3]

      (2048) 0x464600 FCMP	D5, D4

      (2048) 0x464604 B.GE	4645e0

      (2048) 0x464608 LDR	X21, [X19, X14,LSL #3]

      (2048) 0x46460c LDR	X11, [X5, X27,LSL #3]

      (2048) 0x464610 LDR	X23, [X7, X21,LSL #3]

      (2048) 0x464614 CMP	X11, X23

      (2048) 0x464618 B.NE	4645e0

      (2048) 0x46461c STR	X21, [X20, X14,LSL #3]

      (2048) 0x464620 LDR	X11, [X2, X12,LSL #3]

      (2048) 0x464624 ADD	X14, X14, #1

      (2048) 0x464628 CMP	X14, X11

      (2048) 0x46462c B.LT	4645fc

    (2030) 0x464630 B	463c90

    (2030) 0x464634 FMUL	D4, D4, D1

    (2030) 0x464638 CMP	X19, X14

    (2030) 0x46463c B.GE	464688

    (2030) 0x464640 LDR	X14, [X15]

    (2030) 0x464644 B	464660

      (2045) 0x464648 LDR	X11, [X14, X19,LSL #3]

      (2045) 0x46464c STR	X11, [X24, X19,LSL #3]

      (2045) 0x464650 LDR	X11, [X1, X12,LSL #3]

      (2045) 0x464654 ADD	X19, X19, #1

      (2045) 0x464658 CMP	X19, X11

      (2045) 0x46465c B.GE	464688

      (2045) 0x464660 LDR	D5, [X0, X19,LSL #3]

      (2045) 0x464664 FCMP	D5, D4

      (2045) 0x464668 B.LT	464648

      (2045) 0x46466c SUB	X10, X10, #1

      (2045) 0x464670 STR	X26, [X24, X19,LSL #3]

      (2045) 0x464674 STUR	X10, [X29, #480]

      (2045) 0x464678 LDR	X11, [X1, X12,LSL #3]

      (2045) 0x46467c ADD	X19, X19, #1

      (2045) 0x464680 CMP	X19, X11

      (2045) 0x464684 B.LT	464660

    (2030) 0x464688 LDR	X14, [X2, X27,LSL #3]

    (2030) 0x46468c LDR	X11, [X2, X12,LSL #3]

    (2030) 0x464690 CMP	X14, X11

    (2030) 0x464694 B.GE	463c90

    (2030) 0x464698 LDR	X5, [X25]

    (2030) 0x46469c LDR	X7, [X13]

    (2030) 0x4646a0 B	4646bc

      (2044) 0x4646a4 LDR	X11, [X7, X14,LSL #3]

      (2044) 0x4646a8 STR	X11, [X5, X14,LSL #3]

      (2044) 0x4646ac LDR	X11, [X2, X12,LSL #3]

      (2044) 0x4646b0 ADD	X14, X14, #1

      (2044) 0x4646b4 CMP	X14, X11

      (2044) 0x4646b8 B.GE	463c90

      (2044) 0x4646bc LDR	D5, [X3, X14,LSL #3]

      (2044) 0x4646c0 FCMP	D5, D4

      (2044) 0x4646c4 B.LT	4646a4

      (2044) 0x4646c8 SUB	X9, X9, #1

      (2044) 0x4646cc STR	X26, [X5, X14,LSL #3]

      (2044) 0x4646d0 STUR	X9, [X29, #472]

      (2044) 0x4646d4 LDR	X11, [X2, X12,LSL #3]

      (2044) 0x4646d8 ADD	X14, X14, #1

      (2044) 0x4646dc CMP	X14, X11

      (2044) 0x4646e0 B.LT	4646bc

    (2030) 0x4646e4 B	463c90

  (2040) 0x4646e8 ADD	X11, X5, X7,LSL #3

  (2040) 0x4646ec SUB	X14, X20, X7

  (2040) 0x4646f0 ADD	X5, X11, #8

  (2040) 0x4646f4 LDR	X11, [SP, #56]

  (2040) 0x4646f8 ADD	X7, X11, X7,LSL #3

  (2040) 0x4646fc B	464710

  (2040) 0x464700 SUBS	X14, X14, #2

  (2040) 0x464704 ADD	X5, X5, #16

  (2040) 0x464708 ADD	X7, X7, #16

  (2040) 0x46470c B.EQ	4642a8

  (2040) 0x464710 LDUR	X11, [X7, #504]

  (2040) 0x464714 LDR	X11, [X6, X11,LSL #3]

  (2040) 0x464718 CMP	X23, X11

  (2040) 0x46471c B.EQ	464740

  (2040) 0x464720 LDR	X11, [X7]

  (2040) 0x464724 LDR	X11, [X6, X11,LSL #3]

  (2040) 0x464728 CMP	X23, X11

  (2040) 0x46472c B.NE	464700

  (2040) 0x464730 B	464760

0x464734 HINT	#0

0x464738 HINT	#0

0x46473c HINT	#0

(2039) 0x464740 LDUR	D7, [X5, #504]

(2039) 0x464744 FCMP	D4, D7

(2039) 0x464748 FADD	D6, D6, D7

(2039) 0x46474c FCSEL	D4, D4, D7, #4

(2039) 0x464750 LDR	X11, [X7]

(2039) 0x464754 LDR	X11, [X6, X11,LSL #3]

(2039) 0x464758 CMP	X23, X11

(2039) 0x46475c B.NE	464700

  (2040) 0x464760 LDR	D7, [X5]

  (2040) 0x464764 FCMP	D4, D7

  (2040) 0x464768 FADD	D6, D6, D7

  (2040) 0x46476c FCSEL	D4, D4, D7, #4

  (2040) 0x464770 B	464700

0x464774 LDP	X9, X11, [SP, #16]

0x464778 LDUR	X19, [X29, #456]

0x46477c SUB	X0, X29, #32

0x464780 SUB	X2, X29, #40

0x464784 LDR	X9, [X9]

0x464788 LDR	X10, [X19]

0x46478c LDR	X4, [X11]

0x464790 ADD	X1, X8, X9,LSL #3

0x464794 ADD	X3, X10, X9,LSL #3

0x464798 BL	4aba90

0x46479c LDP	X8, X10, [X29, #1000]

0x4647a0 CMP	X10, X8

0x4647a4 B.GE	4648a4

0x4647a8 LDR	X11, [SP, #8]

0x4647ac LDP	X15, X13, [SP, #40]

0x4647b0 LDR	X14, [SP, #32]

0x4647b4 LDP	X9, X8, [X29, #192]

0x4647b8 LDR	X12, [X19]

0x4647bc LDR	X16, [X25]

0x4647c0 LDR	X11, [X11]

0x4647c4 LDR	X13, [X13]

0x4647c8 LDR	X14, [X14]

0x4647cc LDR	X15, [X15]

0x4647d0 B	4647ec

0x4647d4 HINT	#0

0x4647d8 HINT	#0

0x4647dc HINT	#0

  (2027) 0x4647e0 LDUR	X17, [X29, #488]

  (2027) 0x4647e4 CMP	X10, X17

  (2027) 0x4647e8 B.GE	4648a4

  (2027) 0x4647ec ORR	X17, XZR, X10

  (2027) 0x4647f0 LDUR	X10, [X29, #480]

  (2027) 0x4647f4 LDR	X18, [X11, X17,LSL #3]

  (2027) 0x4647f8 ADD	X10, X18, X10

  (2027) 0x4647fc STR	X10, [X11, X17,LSL #3]

  (2027) 0x464800 LDUR	X10, [X29, #472]

  (2027) 0x464804 LDR	X18, [X12, X17,LSL #3]

  (2027) 0x464808 ADD	X10, X18, X10

  (2027) 0x46480c STR	X10, [X12, X17,LSL #3]

  (2027) 0x464810 ADD	X10, X17, #1

  (2027) 0x464814 LDR	X18, [X13, X17,LSL #3]

  (2027) 0x464818 LDR	X0, [X13, X10,LSL #3]

  (2027) 0x46481c CMP	X18, X0

  (2027) 0x464820 B.GE	464864

(2028) 0x464824 LDR	X1, [X11, X17,LSL #3]

(2028) 0x464828 LDR	X2, [X9]

(2028) 0x46482c B	46484c

0x464830 HINT	#0

0x464834 HINT	#0

0x464838 HINT	#0

0x46483c HINT	#0

(2028) 0x464840 ADD	X18, X18, #1

(2028) 0x464844 CMP	X18, X0

(2028) 0x464848 B.GE	464864

(2028) 0x46484c LDR	X3, [X14, X18,LSL #3]

(2028) 0x464850 TBNZ	X3, #63, 464840

(2028) 0x464854 STR	X3, [X2, X1,LSL #3]

(2028) 0x464858 ADD	X1, X1, #1

(2028) 0x46485c LDR	X0, [X13, X10,LSL #3]

(2028) 0x464860 B	464840

  (2027) 0x464864 LDR	X18, [X15, X17,LSL #3]

  (2027) 0x464868 LDR	X0, [X15, X10,LSL #3]

  (2027) 0x46486c CMP	X18, X0

  (2027) 0x464870 B.GE	4647e0

  (2027) 0x464874 LDR	X17, [X12, X17,LSL #3]

  (2027) 0x464878 LDR	X1, [X8]

  (2027) 0x46487c B	46488c

    (2029) 0x464880 ADD	X18, X18, #1

    (2029) 0x464884 CMP	X18, X0

    (2029) 0x464888 B.GE	4647e0

    (2029) 0x46488c LDR	X2, [X16, X18,LSL #3]

    (2029) 0x464890 TBNZ	X2, #63, 464880

    (2029) 0x464894 STR	X2, [X1, X17,LSL #3]

    (2029) 0x464898 ADD	X17, X17, #1

    (2029) 0x46489c LDR	X0, [X15, X10,LSL #3]

    (2029) 0x4648a0 B	464880

0x4648a4 LDP	X20, X19, [SP, #256]

0x4648a8 LDP	X22, X21, [SP, #240]

0x4648ac LDP	X24, X23, [SP, #224]

0x4648b0 LDP	X26, X25, [SP, #208]

0x4648b4 LDP	X28, X27, [SP, #192]

0x4648b8 LDP	X29, X30, [SP, #176]

0x4648bc ADD	SP, SP, #272

0x4648c0 RET

0x4648c4 HINT	#0

0x4648c8 HINT	#0

0x4648cc HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:246-513
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:246-283,289-302,309-386,392-415,422-445,451-472,480,492-513.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.67 to 0.67 cycles (37.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 60% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 24.67 to 19.67 cycles (1.25x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.67 to 1.00 cycles (24.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 520 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	142
loop length	568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.00	4.00	4.00	4.00	4.00	4.00	0.50	0.50	0.50	0.50	24.67	24.67	24.67	11.00	11.00
cycles	3.50	3.50	4.00	4.00	4.00	4.00	4.00	4.00	0.50	0.50	0.50	0.50	24.67	24.67	24.67	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.13
Overall L1	24.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.67 cycles. At this rate:

21% of peak load performance is reached (21.08 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 463b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X2, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X1, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4aae70 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X12, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X19, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X12, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464774 <hypre_BoomerAMGCreateS.omp_outlined.2+0xc14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X3, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVN X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X16, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR D0, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X6, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X19, X7, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X3, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X19, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 463c9c <hypre_BoomerAMGCreateS.omp_outlined.2+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X9, X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X19, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X1, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X10, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aba90 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X10, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4648a4 <hypre_BoomerAMGCreateS.omp_outlined.2+0xd44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4647ec <hypre_BoomerAMGCreateS.omp_outlined.2+0xc8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_strength.c:246-513
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.67 to 1.00 cycles (24.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 520 bytes. The binary function is storing 240 bytes.

General properties

nb instructions	142
loop length	568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.00	4.00	4.00	4.00	4.00	4.00	0.50	0.50	0.50	0.50	24.67	24.67	24.67	11.00	11.00
cycles	3.50	3.50	4.00	4.00	4.00	4.00	4.00	4.00	0.50	0.50	0.50	0.50	24.67	24.67	24.67	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.13
Overall L1	24.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.67 cycles. At this rate:

21% of peak load performance is reached (21.08 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.73 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 463b60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X2, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X1, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X24, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X5, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 4aae70 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X12, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X19, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X12, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 464774 <hypre_BoomerAMGCreateS.omp_outlined.2+0xc14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X13, X3, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D3, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVN X26, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X16, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X30, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X18, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR D0, [X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X19, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X6, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X19, X7, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X24, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X3, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X0, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X7, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X11, X19, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 463c9c <hypre_BoomerAMGCreateS.omp_outlined.2+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X9, X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDUR X19, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X0, X29, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X2, X29, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X1, X8, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X3, X10, X9,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aba90 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X10, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 4648a4 <hypre_BoomerAMGCreateS.omp_outlined.2+0xd44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X13, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X9, X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X12, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4647ec <hypre_BoomerAMGCreateS.omp_outlined.2+0xc8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP X20, X19, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreateS.omp_outlined.2–	0.38	0.07
▼Loop 2028 - par_strength.c:492-513 - exec–	0.10	0.02
▼Loop 2027 - par_strength.c:492-513 - exec–	0.01	0.01
○Loop 2029 - par_strength.c:508-513 - exec	0.00	0.00
▼Loop 2039 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2040 - par_strength.c:253-472 - exec–	0.00	0.00
▼Loop 2030 - par_strength.c:253-472 - exec–	0.08	0.01
○Loop 2045 - par_strength.c:451-460 - exec	0.16	0.03
○Loop 2033 - par_strength.c:324-327 - exec	0.02	0.01
○Loop 2034 - par_strength.c:324-327 - exec	0.00	0.00
○Loop 2043 - par_strength.c:270-275 - exec	0.00	0.00
○Loop 2041 - par_strength.c:289-294 - exec	0.00	0.00
○Loop 2050 - par_strength.c:376-386 - exec	0.00	0.00
○Loop 2036 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2042 - par_strength.c:278-283 - exec	0.00	0.00
○Loop 2037 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2047 - par_strength.c:424-433 - exec	0.00	0.00
○Loop 2032 - par_strength.c:329-332 - exec	0.00	0.00
○Loop 2035 - par_strength.c:316-319 - exec	0.00	0.00
○Loop 2038 - par_strength.c:311-314 - exec	0.00	0.00
○Loop 2046 - par_strength.c:436-445 - exec	0.00	0.00
○Loop 2049 - par_strength.c:392-402 - exec	0.00	0.00
○Loop 2044 - par_strength.c:463-472 - exec	0.00	0.00
○Loop 2052 - par_strength.c:351-353 - exec	0.00	0.00
○Loop 2048 - par_strength.c:405-415 - exec	0.00	0.00
○Loop 2053 - par_strength.c:345-347 - exec	0.00	0.00
○Loop 2051 - par_strength.c:363-373 - exec	0.00	0.00
○Loop 2031 - par_strength.c:329-332 - exec	0.00	0.00

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Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code