OV - exec - Function hypre_BoomerAMGBuildExtPIInterp.omp

	Function: hypre_BoomerAMGBuildExtPIInterp.omp_outlined	Module: exec	Source: par_lr_interp.c:1196-1757 [...]	Coverage (incl. loops): 0.23% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1196 - 1757

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1196: #pragma omp parallel private(i,my_thread_num,num_threads,start,stop,coarse_counter,jj_counter,jj_counter_offd, P_marker, P_marker_offd,jj,kk,i1,k1,loc_col,jj_begin_row,jj_begin_row_offd,jj_end_row,jj_end_row_offd,diagonal,sum,sgn,jj1,i2,distribute,strong_f_marker)

[...]

1219:        jj_counter = start_indexing;

1220:        jj_counter_offd = start_indexing;

1221:        if (n_fine)

1222:        {

1223:            P_marker = hypre_CTAlloc(HYPRE_Int, n_fine);

1224:            for (i = 0; i < n_fine; i++)

1225:            {  P_marker[i] = -1; }

1226:        }

1227:        if (full_off_procNodes)

1228:        {

1229:          P_marker_offd = hypre_CTAlloc(HYPRE_Int, full_off_procNodes);

1230:          for (i = 0; i < full_off_procNodes; i++)

1231:          {  P_marker_offd[i] = -1;}

1232:        }

1233:

1234:        /* this thread's row range */

1235:        my_thread_num = hypre_GetThreadNum();

1236:        num_threads = hypre_NumActiveThreads();

1237:        start = (n_fine/num_threads)*my_thread_num;

1238:        if (my_thread_num == num_threads-1)

[...]

1244:        for (i = start; i < stop; i++)

1245:        {

1246:          P_diag_i[i] = jj_counter;

1247:          if (num_procs > 1)

1248:            P_offd_i[i] = jj_counter_offd;

1249:

1250:          if (CF_marker[i] >= 0)

1251:          {

1252:            jj_counter++;

1253:            fine_to_coarse[i] = coarse_counter;

1254:            coarse_counter++;

[...]

1262:          else if (CF_marker[i] != -3)

1263:          {

1264:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1265:            {

1266:              i1 = S_diag_j[jj];

1267:              if (CF_marker[i1] >= 0)

1268:              { /* i1 is a C point */

1269:                if (P_marker[i1] < P_diag_i[i])

1270:                {

1271:                  P_marker[i1] = jj_counter;

1272:                  jj_counter++;

1273:                }

1274:              }

1275:              else if (CF_marker[i1] != -3)

1276:              { /* i1 is a F point, loop through it's strong neighbors */

1277:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1278:                {

1279:                  k1 = S_diag_j[kk];

1280:                  if (CF_marker[k1] >= 0)

1281:                  {

1282:                    if(P_marker[k1] < P_diag_i[i])

1283:                    {

1284:                      P_marker[k1] = jj_counter;

1285:                      jj_counter++;

1286:                    }

1287:                  }

1288:                }

1289:                if(num_procs > 1)

1290:                {

1291:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1292:                  {

1293:                    if(col_offd_S_to_A)

1294:                      k1 = col_offd_S_to_A[S_offd_j[kk]];

1295:                    else

1296:                      k1 = S_offd_j[kk];

1297:                    if (CF_marker_offd[k1] >= 0)

1298:                    {

1299:                      if(P_marker_offd[k1] < P_offd_i[i])

1300:                      {

1301:                        tmp_CF_marker_offd[k1] = 1;

1302:                        P_marker_offd[k1] = jj_counter_offd;

1303:                        jj_counter_offd++;

[...]

1311:            if (num_procs > 1)

1312:            {

1313:              for (jj = S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1314:              {

1315:                i1 = S_offd_j[jj];

1316:                if(col_offd_S_to_A)

1317:                  i1 = col_offd_S_to_A[i1];

1318:                if (CF_marker_offd[i1] >= 0)

1319:                {

1320:                  if(P_marker_offd[i1] < P_offd_i[i])

1321:                  {

1322:                    tmp_CF_marker_offd[i1] = 1;

1323:                    P_marker_offd[i1] = jj_counter_offd;

1324:                    jj_counter_offd++;

1325:                  }

1326:                }

1327:                else if (CF_marker_offd[i1] != -3)

1328:                { /* F point; look at neighbors of i1. Sop contains global col

1329:                   * numbers and entries that could be in S_diag or S_offd or

1330:                   * neither. */

1331:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1332:                  {

1333:                    k1 = Sop_j[kk];

1334:                    if(k1 >= col_1 && k1 < col_n)

1335:                    { /* In S_diag */

1336:                      loc_col = k1-col_1;

1337:                      if(P_marker[loc_col] < P_diag_i[i])

1338:                      {

1339:                        P_marker[loc_col] = jj_counter;

1340:                        jj_counter++;

1341:                      }

1342:                    }

1343:                    else

1344:                    {

1345:                      loc_col = -k1 - 1;

1346:                      if(P_marker_offd[loc_col] < P_offd_i[i])

1347:                      {

1348:                        P_marker_offd[loc_col] = jj_counter_offd;

1349:                        tmp_CF_marker_offd[loc_col] = 1;

1350:                        jj_counter_offd++;

[...]

1363: #pragma omp barrier

1364: #endif

1365:        P_diag_i[stop] = jj_counter;

1366:        P_offd_i[stop] = jj_counter_offd;

1367:        fine_to_coarse_offset[my_thread_num] = coarse_counter;

1368:        diag_offset[my_thread_num] = jj_counter;

1369:        offd_offset[my_thread_num] = jj_counter_offd;

1370:

1371:        /* Stitch P_diag_i, P_offd_i and fine_to_coarse together */

1372: #ifdef HYPRE_USING_OPENMP

1373: #pragma omp barrier

1374: #endif

1375:        if(my_thread_num == 0)

1376:        {

1377:          /* Calculate the offset for P_diag_i and P_offd_i for each thread */

1378:          for (i = 1; i < num_threads; i++)

1379:          {

1380:            diag_offset[i] = diag_offset[i-1] + diag_offset[i];

1381:            fine_to_coarse_offset[i] = fine_to_coarse_offset[i-1] + fine_to_coarse_offset[i];

1382:            offd_offset[i] = offd_offset[i-1] + offd_offset[i];

1383:          }

1384:        }

1385: #ifdef HYPRE_USING_OPENMP

1386: #pragma omp barrier

1387: #endif

1388:

1389:        if(my_thread_num > 0)

1390:        {

1391:          /* update row pointer array with offset,

1392:           * making sure to update the row stop index */

1393:          for (i = start+1; i <= stop; i++)

1394:          {

1395:             P_diag_i[i] += diag_offset[my_thread_num-1];

1396:             P_offd_i[i] += offd_offset[my_thread_num-1];

1397:          }

1398:          /* update fine_to_coarse by offsetting with the offset

1399:           * from the preceding thread */

1400:          for (i = start; i < stop; i++)

1401:          {

1402:            if(fine_to_coarse[i] >= 0)

1403:            { fine_to_coarse[i] += fine_to_coarse_offset[my_thread_num-1]; }

1404:          }

1405:        }

1406: #ifdef HYPRE_USING_OPENMP

1407: #pragma omp barrier

1408: #endif

1409:

1410:        if(my_thread_num == 0)

1411:        {

1412:          if (debug_flag==4)

1413:          {

1414:             wall_time = time_getWallclockSeconds() - wall_time;

1415:             hypre_printf("Proc = %d     determine structure    %f\n",

1416:                           my_id, wall_time);

1417:             fflush(NULL);

[...]

1423:          if (debug_flag== 4) wall_time = time_getWallclockSeconds();

1424:

1425:          P_diag_size =  P_diag_i[n_fine];

1426:          P_offd_size = P_offd_i[n_fine];

1427:

1428:          if (P_diag_size)

1429:          {

1430:             P_diag_j    = hypre_CTAlloc(HYPRE_Int, P_diag_size);

1431:             P_diag_data = hypre_CTAlloc(HYPRE_Real, P_diag_size);

1432:          }

1433:

1434:          if (P_offd_size)

1435:          {

1436:             P_offd_j    = hypre_CTAlloc(HYPRE_Int, P_offd_size);

1437:             P_offd_data = hypre_CTAlloc(HYPRE_Real, P_offd_size);

1438:          }

1439:        }

1440:

1441:        /* Fine to coarse mapping */

1442:        if(num_procs > 1   &&   my_thread_num == 0)

1443:        {

1444:          for (i = 0; i < n_fine; i++)

1445:            fine_to_coarse[i] += my_first_cpt;

1446:

1447:          hypre_alt_insert_new_nodes(comm_pkg, extend_comm_pkg, fine_to_coarse,

1448:                   full_off_procNodes,

1449:                   fine_to_coarse_offd);

1450:

1451:          for (i = 0; i < n_fine; i++)

1452:            fine_to_coarse[i] -= my_first_cpt;

1453:        }

1454:

1455:        for (i = 0; i < n_fine; i++)

1456:          P_marker[i] = -1;

1457:

1458:        for (i = 0; i < full_off_procNodes; i++)

1459:          P_marker_offd[i] = -1;

[...]

1467: #pragma omp barrier

1468: #endif

1469:        for (i = start; i < stop; i++)

1470:        {

1471:          jj_begin_row = P_diag_i[i];

[...]

1480:          if (CF_marker[i] >= 0)

1481:          {

1482:            P_diag_j[jj_counter]    = fine_to_coarse[i];

1483:            P_diag_data[jj_counter] = one;

[...]

1491:          else if (CF_marker[i] != -3)

1492:          {

1493:            strong_f_marker--;

1494:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1495:            {

1496:              i1 = S_diag_j[jj];

[...]

1503:              if (CF_marker[i1] >= 0)

1504:              {

1505:                if (P_marker[i1] < jj_begin_row)

1506:                {

1507:                  P_marker[i1] = jj_counter;

1508:                  P_diag_j[jj_counter]    = fine_to_coarse[i1];

1509:                  P_diag_data[jj_counter] = zero;

1510:                  jj_counter++;

1511:                }

1512:              }

1513:              else  if (CF_marker[i1] != -3)

1514:              {

1515:                P_marker[i1] = strong_f_marker;

1516:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1517:                {

1518:                  k1 = S_diag_j[kk];

1519:                  if (CF_marker[k1] >= 0)

1520:                  {

1521:                    if(P_marker[k1] < jj_begin_row)

1522:                    {

1523:                      P_marker[k1] = jj_counter;

1524:                      P_diag_j[jj_counter] = fine_to_coarse[k1];

1525:                      P_diag_data[jj_counter] = zero;

1526:                      jj_counter++;

1527:                    }

1528:                  }

1529:                }

1530:                if(num_procs > 1)

1531:                {

1532:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1533:                  {

1534:                    if(col_offd_S_to_A)

1535:                     k1 = col_offd_S_to_A[S_offd_j[kk]];

1536:                    else

1537:                     k1 = S_offd_j[kk];

1538:                    if(CF_marker_offd[k1] >= 0)

1539:                    {

1540:                      if(P_marker_offd[k1] < jj_begin_row_offd)

1541:                      {

1542:                        P_marker_offd[k1] = jj_counter_offd;

1543:                        P_offd_j[jj_counter_offd] = k1;

1544:                        P_offd_data[jj_counter_offd] = zero;

1545:                        jj_counter_offd++;

[...]

1553:            if ( num_procs > 1)

1554:            {

1555:              for (jj=S_offd_i[i]; jj < S_offd_i[i+1]; jj++)

1556:              {

1557:                i1 = S_offd_j[jj];

1558:                if(col_offd_S_to_A)

1559:                  i1 = col_offd_S_to_A[i1];

1560:                if ( CF_marker_offd[i1] >= 0)

1561:                {

1562:                  if(P_marker_offd[i1] < jj_begin_row_offd)

1563:                  {

1564:                    P_marker_offd[i1] = jj_counter_offd;

1565:                    P_offd_j[jj_counter_offd] = i1;

1566:                    P_offd_data[jj_counter_offd] = zero;

1567:                    jj_counter_offd++;

1568:                  }

1569:                }

1570:                else if (CF_marker_offd[i1] != -3)

1571:                {

1572:                  P_marker_offd[i1] = strong_f_marker;

1573:                  for(kk = Sop_i[i1]; kk < Sop_i[i1+1]; kk++)

1574:                  {

1575:                    k1 = Sop_j[kk];

1576:                    /* Find local col number */

1577:                    if(k1 >= col_1 && k1 < col_n)

1578:                    {

1579:                      loc_col = k1-col_1;

1580:                      if(P_marker[loc_col] < jj_begin_row)

1581:                      {

1582:                        P_marker[loc_col] = jj_counter;

1583:                        P_diag_j[jj_counter] = fine_to_coarse[loc_col];

1584:                        P_diag_data[jj_counter] = zero;

1585:                        jj_counter++;

1586:                      }

1587:                    }

1588:                    else

1589:                    {

1590:                      loc_col = -k1 - 1;

1591:                      if(P_marker_offd[loc_col] < jj_begin_row_offd)

1592:                      {

1593:                        P_marker_offd[loc_col] = jj_counter_offd;

1594:                        P_offd_j[jj_counter_offd]=loc_col;

1595:                        P_offd_data[jj_counter_offd] = zero;

1596:                        jj_counter_offd++;

[...]

1607:            diagonal = A_diag_data[A_diag_i[i]];

1608:

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

1676:              }

1677:            }

1678:            if(num_procs > 1)

1679:            {

1680:              for(jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

1681:              {

1682:                i1 = A_offd_j[jj];

1683:                if(P_marker_offd[i1] >= jj_begin_row_offd)

1684:                  P_offd_data[P_marker_offd[i1]] += A_offd_data[jj];

1685:                else if(P_marker_offd[i1] == strong_f_marker)

1686:                {

1687:                  sum = zero;

1688:                  for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1689:                  {

1690:                    k1 = A_ext_j[jj1];

1691:                    if(k1 >= col_1 && k1 < col_n)

1692:                    { /* diag */

1693:                      loc_col = k1 - col_1;

1694:                      if(P_marker[loc_col] >= jj_begin_row || loc_col == i)

1695:                        sum += A_ext_data[jj1];

1696:                    }

1697:                    else

1698:                    {

1699:                      loc_col = -k1 - 1;

1700:                      if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1701:                        sum += A_ext_data[jj1];

1702:                    }

1703:                  }

1704:                  if(sum != 0)

1705:                  {

1706:                    distribute = A_offd_data[jj] / sum;

1707:                    for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

1708:                    {

1709:                      k1 = A_ext_j[jj1];

1710:                      if(k1 >= col_1 && k1 < col_n)

1711:                      { /* diag */

1712:                        loc_col = k1 - col_1;

1713:                        if(P_marker[loc_col] >= jj_begin_row)

1714:                          P_diag_data[P_marker[loc_col]] += distribute*

1715:                           A_ext_data[jj1];

1716:                                if(loc_col == i)

1717:                                  diagonal += distribute*A_ext_data[jj1];

1718:                      }

1719:                      else

1720:                      {

1721:                        loc_col = -k1 - 1;

1722:                        if(P_marker_offd[loc_col] >= jj_begin_row_offd)

1723:                          P_offd_data[P_marker_offd[loc_col]] += distribute*

1724:                            A_ext_data[jj1];

[...]

1733:                else if (CF_marker_offd[i1] != -3)

1734:                {

1735:                  if(num_functions == 1 || dof_func[i] == dof_func_offd[i1])

1736:                    diagonal += A_offd_data[jj];

1737:                }

1738:              }

1739:            }

1740:            if (diagonal)

1741:            {

1742:              for(jj = jj_begin_row; jj < jj_end_row; jj++)

1743:                 P_diag_data[jj] /= -diagonal;

1744:              for(jj = jj_begin_row_offd; jj < jj_end_row_offd; jj++)

1745:                 P_offd_data[jj] /= -diagonal;

1746:            }

1747:          }

1748:          strong_f_marker--;

[...]

1754:        if (n_fine)

1755:        {  hypre_TFree(P_marker); }

1756:        if (full_off_procNodes)

1757:        {  hypre_TFree(P_marker_offd); }

0x43a020 STP	X29, X30, [SP, #928]!

0x43a024 STP	X28, X27, [SP, #16]

0x43a028 STP	X26, X25, [SP, #32]

0x43a02c STP	X24, X23, [SP, #48]

0x43a030 STP	X22, X21, [SP, #64]

0x43a034 STP	X20, X19, [SP, #80]

0x43a038 ADD	X29, SP, #0

0x43a03c SUB	SP, SP, #448

0x43a040 STUR	X7, [X29, #464]

0x43a044 STUR	X6, [X29, #480]

0x43a048 LDR	X20, [X2]

0x43a04c ORR	X19, XZR, X3

0x43a050 STUR	X5, [X29, #448]

0x43a054 STR	X0, [SP, #192]

0x43a058 LDR	X0, [X3]

0x43a05c LDR	X8, [X29, #432]

0x43a060 STR	X8, [SP, #96]

0x43a064 LDP	X8, X9, [X29, #416]

0x43a068 STUR	X9, [X29, #296]

0x43a06c STR	X8, [SP, #88]

0x43a070 LDR	X8, [X29, #408]

0x43a074 STR	X8, [SP, #80]

0x43a078 LDR	X8, [X29, #400]

0x43a07c STR	X8, [SP, #152]

0x43a080 LDR	X8, [X29, #392]

0x43a084 STR	X8, [SP, #144]

0x43a088 LDP	X8, X9, [X29, #376]

0x43a08c STUR	X9, [X29, #360]

0x43a090 STR	X8, [SP, #136]

0x43a094 LDR	X8, [X29, #368]

0x43a098 STR	X8, [SP, #128]

0x43a09c LDP	X8, X26, [X29, #336]

0x43a0a0 LDP	X25, X21, [X29, #352]

0x43a0a4 STUR	X8, [X29, #496]

0x43a0a8 LDP	X27, X8, [X29, #320]

0x43a0ac STUR	X8, [X29, #320]

0x43a0b0 LDR	X8, [X29, #312]

0x43a0b4 STR	X8, [SP, #24]

0x43a0b8 LDR	X8, [X29, #304]

0x43a0bc STR	X8, [SP, #16]

0x43a0c0 LDR	X8, [X29, #296]

0x43a0c4 STR	X8, [SP, #48]

0x43a0c8 LDP	X8, X9, [X29, #280]

0x43a0cc STUR	X8, [X29, #344]

0x43a0d0 LDP	X8, X10, [X29, #264]

0x43a0d4 STP	X8, X9, [X29, #904]

0x43a0d8 LDR	X8, [X29, #256]

0x43a0dc STUR	X10, [X29, #432]

0x43a0e0 STR	X8, [SP, #216]

0x43a0e4 LDR	X8, [X29, #248]

0x43a0e8 STR	X8, [SP, #64]

0x43a0ec LDR	X8, [X29, #240]

0x43a0f0 STR	X8, [SP, #8]

0x43a0f4 LDR	X8, [X29, #232]

0x43a0f8 STR	X8, [SP, #40]

0x43a0fc LDR	X8, [X29, #224]

0x43a100 STR	X8, [SP, #56]

0x43a104 LDR	X8, [X29, #216]

0x43a108 STR	X8, [SP, #200]

0x43a10c LDP	X8, X9, [X29, #200]

0x43a110 STUR	X9, [X29, #424]

0x43a114 STR	X8, [SP, #208]

0x43a118 LDR	X8, [X29, #176]

0x43a11c LDP	X28, X24, [X29, #184]

0x43a120 STR	X8, [SP, #120]

0x43a124 LDR	X8, [X29, #168]

0x43a128 STR	X8, [SP, #112]

0x43a12c LDP	X8, X9, [X29, #152]

0x43a130 STUR	X9, [X29, #456]

0x43a134 LDP	X10, X9, [X29, #136]

0x43a138 STUR	X8, [X29, #336]

0x43a13c STUR	X9, [X29, #352]

0x43a140 LDP	X11, X9, [X29, #120]

0x43a144 STP	X9, X10, [X29, #816]

0x43a148 LDP	X8, X9, [X29, #104]

0x43a14c STP	X8, X11, [X29, #920]

0x43a150 LDR	X8, [X29, #96]

0x43a154 STP	X8, X9, [X29, #880]

0x43a158 STR	X4, [SP, #224]

0x43a15c CBZ	X0, 43a1f8

0x43a160 MOVZ	W1, #8

0x43a164 BL	4a90d0

0x43a168 LDR	X8, [X19]

0x43a16c ORR	X22, XZR, X0

0x43a170 CMP	X8, #1

0x43a174 B.LT	43a194

0x43a178 MOVN	X9, #0

0x43a17c ORR	X8, XZR, XZR

(885) 0x43a180 STR	X9, [X22, X8,LSL #3]

(885) 0x43a184 ADD	X8, X8, #1

(885) 0x43a188 LDR	X10, [X19]

(885) 0x43a18c CMP	X8, X10

(885) 0x43a190 B.LT	43a180

0x43a194 LDR	X4, [SP, #224]

0x43a198 LDR	X0, [X4]

0x43a19c STP	X26, X21, [SP, #160]

0x43a1a0 STR	X27, [SP, #32]

0x43a1a4 STR	X25, [SP, #104]

0x43a1a8 CBZ	X0, 43a20c

0x43a1ac MOVZ	W1, #8

0x43a1b0 BL	4a90d0

0x43a1b4 LDR	X11, [SP, #224]

0x43a1b8 ORR	X23, XZR, X0

0x43a1bc LDR	X8, [X11]

0x43a1c0 CMP	X8, #1

0x43a1c4 B.LT	43a20c

0x43a1c8 MOVN	X9, #0

0x43a1cc ORR	X8, XZR, XZR

0x43a1d0 HINT	#0

0x43a1d4 HINT	#0

0x43a1d8 HINT	#0

0x43a1dc HINT	#0

(884) 0x43a1e0 STR	X9, [X23, X8,LSL #3]

(884) 0x43a1e4 ADD	X8, X8, #1

(884) 0x43a1e8 LDR	X10, [X11]

(884) 0x43a1ec CMP	X8, X10

(884) 0x43a1f0 B.LT	43a1e0

0x43a1f4 B	43a20c

0x43a1f8 LDR	X0, [X4]

0x43a1fc STP	X26, X21, [SP, #160]

0x43a200 STR	X27, [SP, #32]

0x43a204 STR	X25, [SP, #104]

0x43a208 CBNZ	X0, 43a1ac

0x43a20c BL	4aae50

0x43a210 ORR	X21, XZR, X0

0x43a214 BL	4aae30

0x43a218 LDR	X8, [X19]

0x43a21c SUB	X9, X0, #1

0x43a220 STUR	X19, [X29, #328]

0x43a224 STR	X21, [SP, #176]

0x43a228 ORR	X26, XZR, XZR

0x43a22c CMP	X21, X9

0x43a230 SDIV	X10, X8, X0

0x43a234 MADD	X27, X10, X21, XZR

0x43a238 STR	X10, [SP, #72]

0x43a23c ADD	X10, X10, X27

0x43a240 CSEL	X14, X8, X10, #0

0x43a244 STUR	X14, [X29, #384]

0x43a248 STR	X0, [SP, #184]

0x43a24c CMP	X14, X27

0x43a250 B.GT	43a370

0x43a254 ORR	X19, XZR, X20

0x43a258 STUR	X28, [X29, #488]

0x43a25c ADRP	X0,

0x43a260 ADD	X0, X0, #1224

0x43a264 ORR	X21, XZR, X14

0x43a268 LDR	X8, [SP, #192]

0x43a26c LDR	W28, [X8]

0x43a270 ORR	W1, WZR, W28

0x43a274 BL	40f890

0x43a278 LDUR	X8, [X29, #448]

0x43a27c LDR	X25, [SP, #176]

0x43a280 ADRP	X0,

0x43a284 ADD	X0, X0, #1248

0x43a288 ORR	W1, WZR, W28

0x43a28c LDR	X8, [X8]

0x43a290 STR	X19, [X8, X21,LSL #3]

0x43a294 LDUR	X8, [X29, #464]

0x43a298 LDR	X8, [X8]

0x43a29c STR	X20, [X8, X21,LSL #3]

0x43a2a0 LDR	X21, [SP, #208]

0x43a2a4 LDR	X8, [X21]

0x43a2a8 STR	X26, [X8, X25,LSL #3]

0x43a2ac LDUR	X8, [X29, #424]

0x43a2b0 LDR	X26, [SP, #200]

0x43a2b4 LDR	X8, [X8]

0x43a2b8 STR	X19, [X8, X25,LSL #3]

0x43a2bc LDR	X8, [X26]

0x43a2c0 STR	X20, [X8, X25,LSL #3]

0x43a2c4 ORR	W20, WZR, W28

0x43a2c8 BL	40f890

0x43a2cc LDUR	X19, [X29, #328]

0x43a2d0 LDR	X28, [SP, #216]

0x43a2d4 LDR	X12, [SP, #184]

0x43a2d8 CBNZ	X25, 43a74c

0x43a2dc SUBS	X8, X12, #1

0x43a2e0 B.LE	43a74c

0x43a2e4 LDUR	X9, [X29, #424]

0x43a2e8 LDR	X11, [X26]

0x43a2ec LDR	X10, [X21]

0x43a2f0 ADD	X13, X11, X12,LSL #3

0x43a2f4 LDR	X9, [X9]

0x43a2f8 ADD	X15, X10, X12,LSL #3

0x43a2fc ADD	X14, X9, X12,LSL #3

0x43a300 CMP	X9, X13

0x43a304 CCMP	X11, X14, #2, #3

0x43a308 CSINC	W12, WZR, WZR, #2

0x43a30c CMP	X10, X13

0x43a310 CCMP	X11, X15, #2, #3

0x43a314 CSINC	W13, WZR, WZR, #2

0x43a318 CMP	X10, X14

0x43a31c CCMP	X9, X15, #2, #3

0x43a320 B.CC	43a708

0x43a324 TBNZ	W12, #0, 43a708

0x43a328 CBNZ	W13, 43a708

0x43a32c LDR	X12, [X9], #8

0x43a330 LDR	X13, [X11], #8

0x43a334 LDR	X14, [X10], #8

0x43a338 HINT	#0

0x43a33c HINT	#0

(874) 0x43a340 LDR	X15, [X9]

(874) 0x43a344 SUBS	X8, X8, #1

(874) 0x43a348 ADD	X12, X15, X12

(874) 0x43a34c STR	X12, [X9], #8

(874) 0x43a350 LDR	X15, [X10]

(874) 0x43a354 ADD	X14, X15, X14

(874) 0x43a358 STR	X14, [X10], #8

(874) 0x43a35c LDR	X15, [X11]

(874) 0x43a360 ADD	X13, X15, X13

(874) 0x43a364 STR	X13, [X11], #8

(874) 0x43a368 B.NE	43a340

0x43a36c B	43a74c

0x43a370 LDUR	X9, [X29, #464]

0x43a374 LDUR	X8, [X29, #448]

0x43a378 ORR	X18, XZR, X27

0x43a37c ORR	X19, XZR, X20

0x43a380 LDR	X25, [X9]

0x43a384 LDP	X11, X9, [X29, #880]

0x43a388 LDR	X8, [X8]

0x43a38c LDR	X10, [X11]

0x43a390 LDR	X11, [X9]

0x43a394 LDUR	X9, [X29, #416]

0x43a398 LDR	X12, [X9]

0x43a39c LDUR	X9, [X29, #304]

0x43a3a0 LDR	X13, [X9]

0x43a3a4 LDUR	X9, [X29, #352]

0x43a3a8 LDR	X9, [X9]

0x43a3ac STUR	X9, [X29, #488]

0x43a3b0 LDUR	X9, [X29, #312]

0x43a3b4 LDR	X15, [X9]

0x43a3b8 LDUR	X9, [X29, #336]

0x43a3bc LDR	X9, [X9]

0x43a3c0 STUR	X9, [X29, #472]

0x43a3c4 LDUR	X9, [X29, #408]

0x43a3c8 LDR	X16, [X9]

0x43a3cc STUR	X16, [X29, #440]

0x43a3d0 B	43a400

0x43a3d4 HINT	#0

0x43a3d8 HINT	#0

0x43a3dc HINT	#0

        (875) 0x43a3e0 LDR	X9, [X10, X18,LSL #3]

        (875) 0x43a3e4 TBNZ	X9, #63, 43a420

        (875) 0x43a3e8 ADD	X19, X19, #1

        (875) 0x43a3ec STR	X26, [X16, X18,LSL #3]

        (875) 0x43a3f0 ADD	X26, X26, #1

        (875) 0x43a3f4 ADD	X18, X18, #1

        (875) 0x43a3f8 CMP	X18, X14

        (875) 0x43a3fc B.EQ	43a258

        (875) 0x43a400 LDUR	X9, [X29, #480]

        (875) 0x43a404 STR	X19, [X8, X18,LSL #3]

        (875) 0x43a408 LDR	X9, [X9]

        (875) 0x43a40c CMP	X9, #2

        (875) 0x43a410 B.LT	43a3e0

        (875) 0x43a414 STR	X20, [X25, X18,LSL #3]

        (875) 0x43a418 B	43a3e0

0x43a41c HINT	#0

        (875) 0x43a420 CMN	X9, #3

        (875) 0x43a424 B.EQ	43a3f4

      (876) 0x43a428 ADD	X1, X18, #1

      (876) 0x43a42c LDR	X2, [X11, X18,LSL #3]

      (876) 0x43a430 LDR	X9, [X11, X1,LSL #3]

      (876) 0x43a434 CMP	X2, X9

      (876) 0x43a438 B.GE	43a5c4

      (876) 0x43a43c LDUR	X9, [X29, #304]

      (876) 0x43a440 LDR	X3, [X9]

      (876) 0x43a444 LDUR	X9, [X29, #312]

      (876) 0x43a448 LDR	X4, [X9]

      (876) 0x43a44c LDUR	X9, [X29, #336]

      (876) 0x43a450 LDR	X5, [X9]

      (876) 0x43a454 B	43a470

0x43a458 HINT	#0

0x43a45c HINT	#0

        (880) 0x43a460 LDR	X9, [X11, X1,LSL #3]

        (880) 0x43a464 ADD	X2, X2, #1

        (880) 0x43a468 CMP	X2, X9

        (880) 0x43a46c B.GE	43a5c4

        (880) 0x43a470 LDR	X9, [X12, X2,LSL #3]

        (880) 0x43a474 LDR	X14, [X10, X9,LSL #3]

        (880) 0x43a478 TBNZ	X14, #63, 43a4a0

        (880) 0x43a47c LDR	X14, [X22, X9,LSL #3]

        (880) 0x43a480 LDR	X0, [X8, X18,LSL #3]

        (880) 0x43a484 CMP	X14, X0

        (880) 0x43a488 B.GE	43a460

        (880) 0x43a48c STR	X19, [X22, X9,LSL #3]

        (880) 0x43a490 ADD	X19, X19, #1

        (880) 0x43a494 B	43a460

0x43a498 HINT	#0

0x43a49c HINT	#0

        (880) 0x43a4a0 CMN	X14, #3

        (880) 0x43a4a4 B.EQ	43a460

        (880) 0x43a4a8 ADD	X6, X9, #1

        (880) 0x43a4ac LDR	X0, [X11, X9,LSL #3]

        (880) 0x43a4b0 LDR	X7, [X11, X6,LSL #3]

        (880) 0x43a4b4 B	43a4c4

0x43a4b8 HINT	#0

0x43a4bc HINT	#0

          (883) 0x43a4c0 ADD	X0, X0, #1

          (883) 0x43a4c4 CMP	X0, X7

          (883) 0x43a4c8 B.GE	43a4f8

          (883) 0x43a4cc LDR	X14, [X12, X0,LSL #3]

          (883) 0x43a4d0 LDR	X21, [X10, X14,LSL #3]

          (883) 0x43a4d4 TBNZ	X21, #63, 43a4c0

          (883) 0x43a4d8 LDR	X21, [X22, X14,LSL #3]

          (883) 0x43a4dc LDR	X30, [X8, X18,LSL #3]

          (883) 0x43a4e0 CMP	X21, X30

          (883) 0x43a4e4 B.GE	43a4c0

          (883) 0x43a4e8 STR	X19, [X22, X14,LSL #3]

          (883) 0x43a4ec ADD	X19, X19, #1

          (883) 0x43a4f0 LDR	X7, [X11, X6,LSL #3]

          (883) 0x43a4f4 B	43a4c0

        (880) 0x43a4f8 LDUR	X14, [X29, #480]

        (880) 0x43a4fc LDR	X14, [X14]

        (880) 0x43a500 CMP	X14, #2

        (880) 0x43a504 B.LT	43a460

        (880) 0x43a508 LDR	X7, [X3, X9,LSL #3]

        (880) 0x43a50c LDR	X0, [X3, X6,LSL #3]

        (880) 0x43a510 CMP	X7, X0

        (880) 0x43a514 B.GE	43a460

        (880) 0x43a518 LDUR	X9, [X29, #352]

        (880) 0x43a51c LDR	X21, [X9]

        (880) 0x43a520 LDUR	X9, [X29, #464]

        (880) 0x43a524 LDR	X30, [X9]

        (880) 0x43a528 LDUR	X9, [X29, #456]

        (880) 0x43a52c LDR	X9, [X9]

        (880) 0x43a530 CBNZ	X4, 43a54c

        (880) 0x43a534 B	43a590

0x43a538 HINT	#0

0x43a53c HINT	#0

          (881) 0x43a540 ADD	X7, X7, #1

          (881) 0x43a544 CMP	X7, X0

          (881) 0x43a548 B.GE	43a460

          (881) 0x43a54c LDR	X14, [X21, X7,LSL #3]

          (881) 0x43a550 LDR	X14, [X4, X14,LSL #3]

          (881) 0x43a554 LDR	X16, [X5, X14,LSL #3]

          (881) 0x43a558 TBNZ	X16, #63, 43a540

          (881) 0x43a55c LDR	X16, [X23, X14,LSL #3]

          (881) 0x43a560 LDR	X17, [X30, X18,LSL #3]

          (881) 0x43a564 CMP	X16, X17

          (881) 0x43a568 B.GE	43a540

          (881) 0x43a56c MOVZ	W16, #1

          (881) 0x43a570 STR	X16, [X9, X14,LSL #3]

          (881) 0x43a574 STR	X20, [X23, X14,LSL #3]

          (881) 0x43a578 ADD	X20, X20, #1

          (881) 0x43a57c LDR	X0, [X3, X6,LSL #3]

          (881) 0x43a580 B	43a540

          (882) 0x43a584 ADD	X7, X7, #1

          (882) 0x43a588 CMP	X7, X0

          (882) 0x43a58c B.GE	43a460

          (882) 0x43a590 LDR	X14, [X21, X7,LSL #3]

          (882) 0x43a594 LDR	X16, [X5, X14,LSL #3]

          (882) 0x43a598 TBNZ	X16, #63, 43a584

          (882) 0x43a59c LDR	X16, [X23, X14,LSL #3]

          (882) 0x43a5a0 LDR	X17, [X30, X18,LSL #3]

          (882) 0x43a5a4 CMP	X16, X17

          (882) 0x43a5a8 B.GE	43a584

          (882) 0x43a5ac MOVZ	W16, #1

          (882) 0x43a5b0 STR	X16, [X9, X14,LSL #3]

          (882) 0x43a5b4 STR	X20, [X23, X14,LSL #3]

          (882) 0x43a5b8 ADD	X20, X20, #1

          (882) 0x43a5bc LDR	X0, [X3, X6,LSL #3]

          (882) 0x43a5c0 B	43a584

      (876) 0x43a5c4 LDUR	X9, [X29, #480]

      (876) 0x43a5c8 LDR	X9, [X9]

      (876) 0x43a5cc CMP	X9, #2

      (876) 0x43a5d0 B.LT	43a6fc

      (876) 0x43a5d4 LDR	X2, [X13, X18,LSL #3]

      (876) 0x43a5d8 LDR	X9, [X13, X1,LSL #3]

      (876) 0x43a5dc CMP	X2, X9

      (876) 0x43a5e0 B.GE	43a6fc

    (877) 0x43a5e4 LDR	X9, [SP, #112]

    (877) 0x43a5e8 LDR	X3, [X9]

    (877) 0x43a5ec LDR	X9, [SP, #120]

    (877) 0x43a5f0 LDR	X4, [X9]

    (877) 0x43a5f4 LDUR	X9, [X29, #464]

    (877) 0x43a5f8 LDR	X5, [X9]

    (877) 0x43a5fc LDUR	X9, [X29, #456]

    (877) 0x43a600 LDR	X6, [X9]

    (877) 0x43a604 B	43a618

    (877) 0x43a608 LDR	X9, [X13, X1,LSL #3]

    (877) 0x43a60c ADD	X2, X2, #1

    (877) 0x43a610 CMP	X2, X9

    (877) 0x43a614 B.GE	43a6fc

    (877) 0x43a618 LDUR	X9, [X29, #488]

    (877) 0x43a61c LDR	X9, [X9, X2,LSL #3]

    (877) 0x43a620 CBZ	X15, 43a628

    (877) 0x43a624 LDR	X9, [X15, X9,LSL #3]

    (877) 0x43a628 LDUR	X14, [X29, #472]

    (877) 0x43a62c LDR	X14, [X14, X9,LSL #3]

    (877) 0x43a630 TBNZ	X14, #63, 43a660

    (877) 0x43a634 LDR	X14, [X23, X9,LSL #3]

    (877) 0x43a638 LDR	X16, [X5, X18,LSL #3]

    (877) 0x43a63c CMP	X14, X16

    (877) 0x43a640 B.GE	43a608

    (877) 0x43a644 MOVZ	W14, #1

    (877) 0x43a648 STR	X14, [X6, X9,LSL #3]

    (877) 0x43a64c STR	X20, [X23, X9,LSL #3]

    (877) 0x43a650 ADD	X20, X20, #1

    (877) 0x43a654 B	43a608

0x43a658 HINT	#0

0x43a65c HINT	#0

    (877) 0x43a660 CMN	X14, #3

    (877) 0x43a664 B.EQ	43a608

    (877) 0x43a668 ADD	X9, X3, X9,LSL #3

    (877) 0x43a66c LDP	X0, X14, [X9]

    (877) 0x43a670 CMP	X0, X14

    (877) 0x43a674 B.GE	43a608

  (879) 0x43a678 LDUR	X14, [X29, #464]

  (879) 0x43a67c LDR	X7, [X14]

  (879) 0x43a680 LDUR	X14, [X29, #456]

  (879) 0x43a684 LDR	X21, [X14]

  (879) 0x43a688 B	43a69c

  (879) 0x43a68c LDR	X14, [X9, #8]

  (879) 0x43a690 ADD	X0, X0, #1

  (879) 0x43a694 CMP	X0, X14

  (879) 0x43a698 B.GE	43a608

  (879) 0x43a69c LDR	X30, [X4, X0,LSL #3]

  (879) 0x43a6a0 LDR	X14, [X28]

  (879) 0x43a6a4 LDR	X16, [X24]

  (879) 0x43a6a8 SUBS	X14, X30, X14

  (879) 0x43a6ac CCMP	X30, X16, #0, #10

  (879) 0x43a6b0 B.LT	43a6e0

  (879) 0x43a6b4 ORN	X14, XZR, X30

  (879) 0x43a6b8 LDR	X17, [X7, X18,LSL #3]

  (879) 0x43a6bc LDR	X16, [X23, X14,LSL #3]

  (879) 0x43a6c0 CMP	X16, X17

  (879) 0x43a6c4 B.GE	43a68c

  (879) 0x43a6c8 STR	X20, [X23, X14,LSL #3]

  (879) 0x43a6cc MOVZ	W16, #1

  (879) 0x43a6d0 ADD	X20, X20, #1

  (879) 0x43a6d4 STR	X16, [X21, X14,LSL #3]

  (879) 0x43a6d8 B	43a68c

0x43a6dc HINT	#0

(878) 0x43a6e0 LDR	X16, [X22, X14,LSL #3]

(878) 0x43a6e4 LDR	X17, [X8, X18,LSL #3]

(878) 0x43a6e8 CMP	X16, X17

(878) 0x43a6ec B.GE	43a68c

(878) 0x43a6f0 STR	X19, [X22, X14,LSL #3]

(878) 0x43a6f4 ADD	X19, X19, #1

(878) 0x43a6f8 B	43a68c

      (876) 0x43a6fc LDUR	X14, [X29, #384]

      (876) 0x43a700 LDUR	X16, [X29, #440]

      (876) 0x43a704 B	43a3f4

0x43a708 ADD	X11, X11, #8

0x43a70c ADD	X10, X10, #8

0x43a710 ADD	X9, X9, #8

0x43a714 HINT	#0

0x43a718 HINT	#0

0x43a71c HINT	#0

(873) 0x43a720 LDP	X12, X13, [X9, #1016]

(873) 0x43a724 SUBS	X8, X8, #1

(873) 0x43a728 ADD	X12, X13, X12

(873) 0x43a72c STR	X12, [X9], #8

(873) 0x43a730 LDP	X12, X13, [X10, #1016]

(873) 0x43a734 ADD	X12, X13, X12

(873) 0x43a738 STR	X12, [X10], #8

(873) 0x43a73c LDP	X12, X13, [X11, #1016]

(873) 0x43a740 ADD	X12, X13, X12

(873) 0x43a744 STR	X12, [X11], #8

(873) 0x43a748 B.NE	43a720

0x43a74c ADRP	X0,

0x43a750 ADD	X0, X0, #1272

0x43a754 ORR	W1, WZR, W20

0x43a758 BL	40f890

0x43a75c LDUR	X1, [X29, #384]

0x43a760 CMP	X25, #1

0x43a764 B.LT	43a7f0

0x43a768 SUBS	X8, X1, X27

0x43a76c B.LE	43a7f0

0x43a770 LDUR	X9, [X29, #424]

0x43a774 LDUR	X11, [X29, #448]

0x43a778 LDUR	X12, [X29, #464]

0x43a77c ORR	X13, XZR, X27

0x43a780 LDR	X16, [X26]

0x43a784 LDR	X15, [X9]

0x43a788 LDR	X11, [X11]

0x43a78c LDR	X12, [X12]

0x43a790 UBFM	X9, X25, #61, #60

0x43a794 SUB	X10, X9, #8

0x43a798 ADD	X9, X15, X10

0x43a79c ADD	X10, X16, X10

0x43a7a0 CMP	X8, #15

0x43a7a4 B.HI	43b720

  (848) 0x43a7a8 SUB	X14, X1, X13

  (848) 0x43a7ac UBFM	X13, X13, #61, #60

  (848) 0x43a7b0 ADD	X13, X13, #8

  (848) 0x43a7b4 ADD	X12, X12, X13

  (848) 0x43a7b8 ADD	X11, X11, X13

  (848) 0x43a7bc HINT	#0

    (846) 0x43a7c0 LDR	X13, [X9]

    (846) 0x43a7c4 LDR	X15, [X11]

    (846) 0x43a7c8 SUBS	X14, X14, #1

    (846) 0x43a7cc ADD	X13, X15, X13

    (846) 0x43a7d0 STR	X13, [X11], #8

    (846) 0x43a7d4 LDR	X13, [X10]

    (846) 0x43a7d8 LDR	X15, [X12]

    (846) 0x43a7dc ADD	X13, X15, X13

    (846) 0x43a7e0 STR	X13, [X12], #8

    (846) 0x43a7e4 B.NE	43a7c0

  (848) 0x43a7e8 CMP	X1, X27

  (848) 0x43a7ec B.GT	43b81c

  (848) 0x43a7f0 ADRP	X0,

  (848) 0x43a7f4 ADD	X0, X0, #1296

  (848) 0x43a7f8 ORR	W1, WZR, W20

  (848) 0x43a7fc BL	40f890

  (848) 0x43a800 CBZ	X25, 43a814

  (848) 0x43a804 LDR	X8, [X19]

  (848) 0x43a808 LDR	X12, [SP, #224]

  (848) 0x43a80c LDUR	X28, [X29, #488]

  (848) 0x43a810 B	43a9c4

  (848) 0x43a814 LDR	X9, [SP, #56]

  (848) 0x43a818 LDR	X8, [X9]

  (848) 0x43a81c CMP	X8, #4

  (848) 0x43a820 B.NE	43a870

  (848) 0x43a824 ORR	X21, XZR, X9

  (848) 0x43a828 BL	4aaee0

  (848) 0x43a82c LDR	X8, [SP, #40]

  (848) 0x43a830 ADRP	X0,

  (848) 0x43a834 ADD	X0, X0, #355

  (848) 0x43a838 LDR	D1, [X8]

  (848) 0x43a83c FSUB	D0, D0, S1

  (848) 0x43a840 STR	D0, [X8]

  (848) 0x43a844 LDR	X8, [SP, #8]

  (848) 0x43a848 LDR	X1, [X8]

  (848) 0x43a84c BL	4a9320

  (848) 0x43a850 ORR	X0, XZR, XZR

  (848) 0x43a854 BL	40f760

  (848) 0x43a858 LDR	X8, [X21]

  (848) 0x43a85c CMP	X8, #4

  (848) 0x43a860 B.NE	43a870

  (848) 0x43a864 BL	4aaee0

  (848) 0x43a868 LDR	X8, [SP, #40]

  (848) 0x43a86c STR	D0, [X8]

  (848) 0x43a870 LDUR	X8, [X29, #448]

  (848) 0x43a874 LDR	X9, [X19]

  (848) 0x43a878 LDR	X10, [SP, #64]

  (848) 0x43a87c LDR	X8, [X8]

  (848) 0x43a880 LDR	X8, [X8, X9,LSL #3]

  (848) 0x43a884 STR	X8, [X10]

  (848) 0x43a888 LDUR	X8, [X29, #464]

  (848) 0x43a88c LDR	X9, [X19]

  (848) 0x43a890 LDR	X8, [X8]

  (848) 0x43a894 LDR	X0, [X8, X9,LSL #3]

  (848) 0x43a898 STR	X0, [X28]

  (848) 0x43a89c LDR	X8, [X10]

  (848) 0x43a8a0 CBZ	X8, 43a8d4

  (848) 0x43a8a4 MOVZ	W1, #8

  (848) 0x43a8a8 ORR	X0, XZR, X8

  (848) 0x43a8ac ORR	X21, XZR, X10

  (848) 0x43a8b0 BL	4a90d0

  (848) 0x43a8b4 LDUR	X8, [X29, #392]

  (848) 0x43a8b8 MOVZ	W1, #8

  (848) 0x43a8bc STR	X0, [X8]

  (848) 0x43a8c0 LDR	X0, [X21]

  (848) 0x43a8c4 BL	4a90d0

  (848) 0x43a8c8 LDUR	X8, [X29, #432]

  (848) 0x43a8cc STR	X0, [X8]

  (848) 0x43a8d0 LDR	X0, [X28]

  (848) 0x43a8d4 LDR	X12, [SP, #224]

  (848) 0x43a8d8 CBZ	X0, 43a904

  (848) 0x43a8dc MOVZ	W1, #8

  (848) 0x43a8e0 BL	4a90d0

  (848) 0x43a8e4 LDUR	X8, [X29, #344]

  (848) 0x43a8e8 MOVZ	W1, #8

  (848) 0x43a8ec STR	X0, [X8]

  (848) 0x43a8f0 LDR	X0, [X28]

  (848) 0x43a8f4 BL	4a90d0

  (848) 0x43a8f8 LDR	X12, [SP, #224]

  (848) 0x43a8fc LDUR	X8, [X29, #400]

  (848) 0x43a900 STR	X0, [X8]

  (848) 0x43a904 LDP	X8, X28, [X29, #992]

  (848) 0x43a908 LDR	X9, [X8]

  (848) 0x43a90c LDR	X8, [X19]

  (848) 0x43a910 CMP	X9, #1

  (848) 0x43a914 B.LE	43a9c4

  (848) 0x43a918 LDR	X13, [SP, #48]

  (848) 0x43a91c CMP	X8, #1

  (848) 0x43a920 B.LT	43a960

  (848) 0x43a924 LDUR	X9, [X29, #408]

  (848) 0x43a928 ORR	X8, XZR, XZR

  (848) 0x43a92c LDR	X9, [X9]

  (848) 0x43a930 HINT	#0

  (848) 0x43a934 HINT	#0

  (848) 0x43a938 HINT	#0

  (848) 0x43a93c HINT	#0

    (872) 0x43a940 LDR	X10, [X13]

    (872) 0x43a944 LDR	X11, [X9, X8,LSL #3]

    (872) 0x43a948 ADD	X10, X11, X10

    (872) 0x43a94c STR	X10, [X9, X8,LSL #3]

    (872) 0x43a950 ADD	X8, X8, #1

    (872) 0x43a954 LDR	X10, [X19]

    (872) 0x43a958 CMP	X8, X10

    (872) 0x43a95c B.LT	43a940

  (848) 0x43a960 LDP	X9, X8, [SP, #16]

  (848) 0x43a964 LDR	X3, [X12]

  (848) 0x43a968 LDR	X1, [X8]

  (848) 0x43a96c LDUR	X8, [X29, #408]

  (848) 0x43a970 LDR	X0, [X9]

  (848) 0x43a974 LDR	X2, [X8]

  (848) 0x43a978 LDR	X8, [SP, #32]

  (848) 0x43a97c LDR	X4, [X8]

  (848) 0x43a980 BL	47a4c0

  (848) 0x43a984 LDR	X12, [SP, #224]

  (848) 0x43a988 LDR	X8, [X19]

  (848) 0x43a98c CMP	X8, #1

  (848) 0x43a990 B.LT	43a9f4

  (848) 0x43a994 LDUR	X8, [X29, #408]

  (848) 0x43a998 LDR	X13, [SP, #48]

  (848) 0x43a99c ORR	X9, XZR, XZR

  (848) 0x43a9a0 LDR	X10, [X8]

    (871) 0x43a9a4 LDR	X8, [X13]

    (871) 0x43a9a8 LDR	X11, [X10, X9,LSL #3]

    (871) 0x43a9ac SUB	X8, X11, X8

    (871) 0x43a9b0 STR	X8, [X10, X9,LSL #3]

    (871) 0x43a9b4 ADD	X9, X9, #1

    (871) 0x43a9b8 LDR	X8, [X19]

    (871) 0x43a9bc CMP	X9, X8

    (871) 0x43a9c0 B.LT	43a9a4

  (848) 0x43a9c4 CMP	X8, #1

  (848) 0x43a9c8 B.LT	43a9f4

  (848) 0x43a9cc MOVN	X9, #0

  (848) 0x43a9d0 ORR	X8, XZR, XZR

  (848) 0x43a9d4 HINT	#0

  (848) 0x43a9d8 HINT	#0

  (848) 0x43a9dc HINT	#0

    (870) 0x43a9e0 STR	X9, [X22, X8,LSL #3]

    (870) 0x43a9e4 ADD	X8, X8, #1

    (870) 0x43a9e8 LDR	X10, [X19]

    (870) 0x43a9ec CMP	X8, X10

    (870) 0x43a9f0 B.LT	43a9e0

  (848) 0x43a9f4 LDR	X8, [X12]

  (848) 0x43a9f8 CMP	X8, #1

  (848) 0x43a9fc B.LT	43aa1c

  (848) 0x43aa00 MOVN	X9, #0

  (848) 0x43aa04 ORR	X8, XZR, XZR

    (869) 0x43aa08 STR	X9, [X23, X8,LSL #3]

    (869) 0x43aa0c ADD	X8, X8, #1

    (869) 0x43aa10 LDR	X10, [X12]

    (869) 0x43aa14 CMP	X8, X10

    (869) 0x43aa18 B.LT	43aa08

  (848) 0x43aa1c ADRP	X0,

  (848) 0x43aa20 ADD	X0, X0, #1320

  (848) 0x43aa24 ORR	W1, WZR, W20

  (848) 0x43aa28 BL	40f890

  (848) 0x43aa2c LDUR	X13, [X29, #384]

  (848) 0x43aa30 LDUR	X9, [X29, #320]

  (848) 0x43aa34 CMP	X13, X27

  (848) 0x43aa38 B.GT	43aa7c

  (848) 0x43aa3c LDR	X8, [X19]

  (848) 0x43aa40 CBZ	X8, 43aa4c

  (848) 0x43aa44 ORR	X0, XZR, X22

  (848) 0x43aa48 BL	4a91d0

  (848) 0x43aa4c LDR	X8, [SP, #224]

  (848) 0x43aa50 LDR	X8, [X8]

  (848) 0x43aa54 CBZ	X8, 43b700

0x43aa58 ORR	X0, XZR, X23

0x43aa5c ADD	SP, SP, #448

0x43aa60 LDP	X20, X19, [SP, #80]

0x43aa64 LDP	X22, X21, [SP, #64]

0x43aa68 LDP	X24, X23, [SP, #48]

0x43aa6c LDP	X26, X25, [SP, #32]

0x43aa70 LDP	X28, X27, [SP, #16]

0x43aa74 LDP	X29, X30, [SP], #96

0x43aa78 B	4a91d0

  (848) 0x43aa7c LDUR	X8, [X29, #448]

  (848) 0x43aa80 FMOV	D0, #1.0000000

  (848) 0x43aa84 FMOV	D1, #-1.0000000

  (848) 0x43aa88 MOVN	X7, #1

  (848) 0x43aa8c LDR	X14, [X8]

  (848) 0x43aa90 LDUR	X8, [X29, #464]

  (848) 0x43aa94 LDR	X8, [X8]

  (848) 0x43aa98 STR	X8, [SP, #184]

  (848) 0x43aa9c LDP	X11, X8, [X29, #880]

  (848) 0x43aaa0 LDR	X10, [X11]

  (848) 0x43aaa4 LDR	X11, [X8]

  (848) 0x43aaa8 LDUR	X8, [X29, #416]

  (848) 0x43aaac LDR	X12, [X8]

  (848) 0x43aab0 LDUR	X8, [X29, #304]

  (848) 0x43aab4 LDR	X26, [X8]

  (848) 0x43aab8 LDUR	X8, [X29, #352]

  (848) 0x43aabc LDR	X8, [X8]

  (848) 0x43aac0 STUR	X8, [X29, #472]

  (848) 0x43aac4 LDUR	X8, [X29, #312]

  (848) 0x43aac8 LDR	X8, [X8]

  (848) 0x43aacc STUR	X8, [X29, #464]

  (848) 0x43aad0 LDUR	X8, [X29, #336]

  (848) 0x43aad4 LDR	X8, [X8]

  (848) 0x43aad8 STUR	X8, [X29, #456]

  (848) 0x43aadc LDR	X8, [SP, #160]

  (848) 0x43aae0 LDR	X15, [X8]

  (848) 0x43aae4 LDR	X8, [SP, #104]

  (848) 0x43aae8 LDR	X8, [X8]

  (848) 0x43aaec STUR	X8, [X29, #424]

  (848) 0x43aaf0 LDR	X8, [SP, #168]

  (848) 0x43aaf4 LDR	X16, [X8]

  (848) 0x43aaf8 LDR	X8, [SP, #128]

  (848) 0x43aafc LDR	X8, [X8]

  (848) 0x43ab00 STR	X8, [SP, #104]

  (848) 0x43ab04 LDR	X8, [SP, #136]

  (848) 0x43ab08 STUR	X15, [X29, #488]

  (848) 0x43ab0c ADD	X15, X15, #8

  (848) 0x43ab10 STUR	X15, [X29, #376]

  (848) 0x43ab14 ADD	X15, X16, #8

  (848) 0x43ab18 STUR	X15, [X29, #368]

  (848) 0x43ab1c LDR	X8, [X8]

  (848) 0x43ab20 STUR	X8, [X29, #448]

  (848) 0x43ab24 LDUR	X8, [X29, #432]

  (848) 0x43ab28 LDR	X17, [X8]

  (848) 0x43ab2c LDUR	X8, [X29, #400]

  (848) 0x43ab30 LDR	X8, [X8]

  (848) 0x43ab34 ADD	X15, X17, #16

  (848) 0x43ab38 STP	X15, X8, [SP, #64]

  (848) 0x43ab3c ADD	X8, X8, #16

  (848) 0x43ab40 STR	X8, [SP, #56]

  (848) 0x43ab44 LDUR	X8, [X29, #408]

  (848) 0x43ab48 STUR	X26, [X29, #416]

  (848) 0x43ab4c LDR	X15, [X8]

  (848) 0x43ab50 LDUR	X8, [X29, #392]

  (848) 0x43ab54 STR	X14, [SP, #192]

  (848) 0x43ab58 STUR	X16, [X29, #440]

  (848) 0x43ab5c LDR	X18, [X8]

  (848) 0x43ab60 STP	X15, X17, [SP, #168]

  (848) 0x43ab64 STR	X18, [SP, #160]

  (848) 0x43ab68 B	43ab8c

    (850) 0x43ab6c LDR	D2, [X9]

    (850) 0x43ab70 LDR	X8, [X15, X27,LSL #3]

    (850) 0x43ab74 STR	X8, [X18, X5,LSL #3]

    (850) 0x43ab78 STR	D2, [X17, X5,LSL #3]

    (850) 0x43ab7c SUB	X7, X7, #1

    (850) 0x43ab80 ADD	X27, X27, #1

    (850) 0x43ab84 CMP	X27, X13

    (850) 0x43ab88 B.EQ	43aa3c

    (850) 0x43ab8c LDR	X5, [X14, X27,LSL #3]

    (850) 0x43ab90 LDR	X8, [X10, X27,LSL #3]

    (850) 0x43ab94 TBZ	X8, #63, 43ab6c

    (850) 0x43ab98 CMN	X8, #3

    (850) 0x43ab9c B.EQ	43ab7c

    (850) 0x43aba0 LDR	X8, [SP, #184]

    (850) 0x43aba4 ADD	X30, X27, #1

    (850) 0x43aba8 SUB	X7, X7, #1

    (850) 0x43abac ORR	X6, XZR, X5

    (850) 0x43abb0 LDR	X13, [X11, X30,LSL #3]

    (850) 0x43abb4 LDR	X9, [X8, X27,LSL #3]

    (850) 0x43abb8 LDR	X8, [X11, X27,LSL #3]

    (850) 0x43abbc ORR	X1, XZR, X9

    (850) 0x43abc0 CMP	X8, X13

    (850) 0x43abc4 B.GE	43adac

    (850) 0x43abc8 LDP	X15, X13, [X29, #816]

    (850) 0x43abcc ORR	X6, XZR, X5

    (850) 0x43abd0 ORR	X1, XZR, X9

    (850) 0x43abd4 LDR	X16, [X13]

    (850) 0x43abd8 LDUR	X13, [X29, #336]

    (850) 0x43abdc LDR	X14, [X15]

    (850) 0x43abe0 LDR	X2, [X13]

    (850) 0x43abe4 LDUR	X13, [X29, #408]

    (850) 0x43abe8 LDR	X3, [X13]

    (850) 0x43abec LDUR	X13, [X29, #392]

    (850) 0x43abf0 LDR	X4, [X13]

    (850) 0x43abf4 LDUR	X13, [X29, #432]

    (850) 0x43abf8 LDR	X19, [X13]

    (850) 0x43abfc B	43ac14

      (865) 0x43ac00 LDUR	X26, [X29, #416]

      (865) 0x43ac04 LDR	X13, [X11, X30,LSL #3]

      (865) 0x43ac08 ADD	X8, X8, #1

      (865) 0x43ac0c CMP	X8, X13

      (865) 0x43ac10 B.GE	43adac

      (865) 0x43ac14 LDR	X13, [X12, X8,LSL #3]

      (865) 0x43ac18 LDR	X15, [X10, X13,LSL #3]

      (865) 0x43ac1c TBNZ	X15, #63, 43ac4c

      (865) 0x43ac20 LDR	X15, [X22, X13,LSL #3]

      (865) 0x43ac24 CMP	X15, X5

      (865) 0x43ac28 B.GE	43ac04

      (865) 0x43ac2c STR	X6, [X22, X13,LSL #3]

      (865) 0x43ac30 LDR	X13, [X3, X13,LSL #3]

      (865) 0x43ac34 STR	X13, [X4, X6,LSL #3]

      (865) 0x43ac38 LDUR	X13, [X29, #496]

      (865) 0x43ac3c LDR	D2, [X13]

      (865) 0x43ac40 STR	D2, [X19, X6,LSL #3]

      (865) 0x43ac44 ADD	X6, X6, #1

      (865) 0x43ac48 B	43ac04

      (865) 0x43ac4c CMN	X15, #3

      (865) 0x43ac50 B.EQ	43ac04

      (865) 0x43ac54 STR	X7, [X22, X13,LSL #3]

      (865) 0x43ac58 ADD	X20, X13, #1

      (865) 0x43ac5c LDR	X15, [X11, X13,LSL #3]

      (865) 0x43ac60 LDR	X26, [X11, X20,LSL #3]

      (865) 0x43ac64 CMP	X15, X26

      (865) 0x43ac68 B.GE	43acd0

      (865) 0x43ac6c LDUR	X17, [X29, #408]

      (865) 0x43ac70 LDR	X18, [X17]

      (865) 0x43ac74 LDUR	X17, [X29, #392]

      (865) 0x43ac78 LDR	X21, [X17]

      (865) 0x43ac7c LDUR	X17, [X29, #432]

      (865) 0x43ac80 LDR	X0, [X17]

      (865) 0x43ac84 B	43ac94

        (868) 0x43ac88 ADD	X15, X15, #1

        (868) 0x43ac8c CMP	X15, X26

        (868) 0x43ac90 B.GE	43acd0

        (868) 0x43ac94 LDR	X17, [X12, X15,LSL #3]

        (868) 0x43ac98 LDR	X25, [X10, X17,LSL #3]

        (868) 0x43ac9c TBNZ	X25, #63, 43ac88

        (868) 0x43aca0 LDR	X25, [X22, X17,LSL #3]

        (868) 0x43aca4 CMP	X25, X5

        (868) 0x43aca8 B.GE	43ac88

        (868) 0x43acac STR	X6, [X22, X17,LSL #3]

        (868) 0x43acb0 LDR	X17, [X18, X17,LSL #3]

        (868) 0x43acb4 STR	X17, [X21, X6,LSL #3]

        (868) 0x43acb8 LDUR	X17, [X29, #496]

        (868) 0x43acbc LDR	X26, [X11, X20,LSL #3]

        (868) 0x43acc0 LDR	D2, [X17]

        (868) 0x43acc4 STR	D2, [X0, X6,LSL #3]

        (868) 0x43acc8 ADD	X6, X6, #1

        (868) 0x43accc B	43ac88

      (865) 0x43acd0 LDUR	X15, [X29, #480]

      (865) 0x43acd4 LDR	X15, [X15]

      (865) 0x43acd8 CMP	X15, #2

      (865) 0x43acdc B.LT	43ac00

      (865) 0x43ace0 LDR	X21, [X14, X13,LSL #3]

      (865) 0x43ace4 LDR	X15, [X14, X20,LSL #3]

      (865) 0x43ace8 CMP	X21, X15

      (865) 0x43acec B.GE	43ac00

      (865) 0x43acf0 LDUR	X13, [X29, #352]

      (865) 0x43acf4 LDUR	X17, [X29, #400]

      (865) 0x43acf8 LDR	X26, [X13]

      (865) 0x43acfc LDUR	X13, [X29, #344]

      (865) 0x43ad00 LDR	X18, [X17]

      (865) 0x43ad04 LDR	X13, [X13]

      (865) 0x43ad08 CBNZ	X16, 43ad2c

      (865) 0x43ad0c B	43ad74

0x43ad10 HINT	#0

0x43ad14 HINT	#0

0x43ad18 HINT	#0

0x43ad1c HINT	#0

        (866) 0x43ad20 ADD	X21, X21, #1

        (866) 0x43ad24 CMP	X21, X15

        (866) 0x43ad28 B.GE	43ac00

        (866) 0x43ad2c LDR	X17, [X26, X21,LSL #3]

        (866) 0x43ad30 LDR	X17, [X16, X17,LSL #3]

        (866) 0x43ad34 LDR	X0, [X2, X17,LSL #3]

        (866) 0x43ad38 TBNZ	X0, #63, 43ad20

        (866) 0x43ad3c LDR	X0, [X23, X17,LSL #3]

        (866) 0x43ad40 CMP	X0, X9

        (866) 0x43ad44 B.GE	43ad20

        (866) 0x43ad48 LDUR	X15, [X29, #496]

        (866) 0x43ad4c STR	X1, [X23, X17,LSL #3]

        (866) 0x43ad50 STR	X17, [X13, X1,LSL #3]

        (866) 0x43ad54 LDR	D2, [X15]

        (866) 0x43ad58 LDR	X15, [X14, X20,LSL #3]

        (866) 0x43ad5c STR	D2, [X18, X1,LSL #3]

        (866) 0x43ad60 ADD	X1, X1, #1

        (866) 0x43ad64 B	43ad20

        (867) 0x43ad68 ADD	X21, X21, #1

        (867) 0x43ad6c CMP	X21, X15

        (867) 0x43ad70 B.GE	43ac00

        (867) 0x43ad74 LDR	X17, [X26, X21,LSL #3]

        (867) 0x43ad78 LDR	X0, [X2, X17,LSL #3]

        (867) 0x43ad7c TBNZ	X0, #63, 43ad68

        (867) 0x43ad80 LDR	X0, [X23, X17,LSL #3]

        (867) 0x43ad84 CMP	X0, X9

        (867) 0x43ad88 B.GE	43ad68

        (867) 0x43ad8c LDUR	X15, [X29, #496]

        (867) 0x43ad90 STR	X1, [X23, X17,LSL #3]

        (867) 0x43ad94 STR	X17, [X13, X1,LSL #3]

        (867) 0x43ad98 LDR	D2, [X15]

        (867) 0x43ad9c LDR	X15, [X14, X20,LSL #3]

        (867) 0x43ada0 STR	D2, [X18, X1,LSL #3]

        (867) 0x43ada4 ADD	X1, X1, #1

        (867) 0x43ada8 B	43ad68

    (850) 0x43adac LDUR	X8, [X29, #480]

    (850) 0x43adb0 LDR	X19, [X8]

    (850) 0x43adb4 CMP	X19, #2

    (850) 0x43adb8 B.LT	43af14

    (850) 0x43adbc LDR	X8, [X26, X27,LSL #3]

    (850) 0x43adc0 LDR	X13, [X26, X30,LSL #3]

    (850) 0x43adc4 CMP	X8, X13

    (850) 0x43adc8 B.GE	43af14

    (850) 0x43adcc LDP	X15, X13, [SP, #112]

    (850) 0x43add0 LDR	X16, [X13]

    (850) 0x43add4 LDUR	X13, [X29, #344]

    (850) 0x43add8 LDR	X14, [X15]

    (850) 0x43addc LDR	X2, [X13]

    (850) 0x43ade0 LDUR	X13, [X29, #400]

    (850) 0x43ade4 LDR	X3, [X13]

    (850) 0x43ade8 B	43adfc

      (863) 0x43adec LDR	X13, [X26, X30,LSL #3]

      (863) 0x43adf0 ADD	X8, X8, #1

      (863) 0x43adf4 CMP	X8, X13

      (863) 0x43adf8 B.GE	43af0c

      (863) 0x43adfc LDP	X15, X13, [X29, #976]

      (863) 0x43ae00 LDR	X13, [X13, X8,LSL #3]

      (863) 0x43ae04 CBZ	X15, 43ae0c

      (863) 0x43ae08 LDR	X13, [X15, X13,LSL #3]

      (863) 0x43ae0c LDUR	X15, [X29, #456]

      (863) 0x43ae10 LDR	X15, [X15, X13,LSL #3]

      (863) 0x43ae14 TBNZ	X15, #63, 43ae40

      (863) 0x43ae18 LDR	X15, [X23, X13,LSL #3]

      (863) 0x43ae1c CMP	X15, X9

      (863) 0x43ae20 B.GE	43adec

      (863) 0x43ae24 STR	X1, [X23, X13,LSL #3]

      (863) 0x43ae28 STR	X13, [X2, X1,LSL #3]

      (863) 0x43ae2c LDUR	X13, [X29, #496]

      (863) 0x43ae30 LDR	D2, [X13]

      (863) 0x43ae34 STR	D2, [X3, X1,LSL #3]

      (863) 0x43ae38 ADD	X1, X1, #1

      (863) 0x43ae3c B	43adec

      (863) 0x43ae40 CMN	X15, #3

      (863) 0x43ae44 B.EQ	43adec

      (863) 0x43ae48 UBFM	X15, X13, #61, #60

      (863) 0x43ae4c ADD	X13, X14, X13,LSL #3

      (863) 0x43ae50 STR	X7, [X23, X15]

      (863) 0x43ae54 LDP	X15, X17, [X13]

      (863) 0x43ae58 CMP	X15, X17

      (863) 0x43ae5c B.GE	43adec

      (863) 0x43ae60 LDUR	X17, [X29, #344]

      (863) 0x43ae64 LDR	X18, [X17]

      (863) 0x43ae68 LDUR	X17, [X29, #400]

      (863) 0x43ae6c LDR	X4, [X17]

      (863) 0x43ae70 LDUR	X17, [X29, #408]

      (863) 0x43ae74 LDR	X19, [X17]

      (863) 0x43ae78 LDUR	X17, [X29, #392]

      (863) 0x43ae7c LDR	X20, [X17]

      (863) 0x43ae80 LDUR	X17, [X29, #432]

      (863) 0x43ae84 LDR	X21, [X17]

      (863) 0x43ae88 B	43ae9c

        (864) 0x43ae8c LDR	X17, [X13, #8]

        (864) 0x43ae90 ADD	X15, X15, #1

        (864) 0x43ae94 CMP	X15, X17

        (864) 0x43ae98 B.GE	43adec

        (864) 0x43ae9c LDR	X17, [X16, X15,LSL #3]

        (864) 0x43aea0 LDR	X0, [X28]

        (864) 0x43aea4 LDR	X25, [X24]

        (864) 0x43aea8 SUBS	X0, X17, X0

        (864) 0x43aeac CCMP	X17, X25, #0, #10

        (864) 0x43aeb0 B.LT	43aee0

        (864) 0x43aeb4 ORN	X17, XZR, X17

        (864) 0x43aeb8 LDR	X0, [X23, X17,LSL #3]

        (864) 0x43aebc CMP	X0, X9

        (864) 0x43aec0 B.GE	43ae8c

        (864) 0x43aec4 STR	X1, [X23, X17,LSL #3]

        (864) 0x43aec8 STR	X17, [X18, X1,LSL #3]

        (864) 0x43aecc LDUR	X17, [X29, #496]

        (864) 0x43aed0 LDR	D2, [X17]

        (864) 0x43aed4 STR	D2, [X4, X1,LSL #3]

        (864) 0x43aed8 ADD	X1, X1, #1

        (864) 0x43aedc B	43ae8c

        (864) 0x43aee0 LDR	X17, [X22, X0,LSL #3]

        (864) 0x43aee4 CMP	X17, X5

        (864) 0x43aee8 B.GE	43ae8c

        (864) 0x43aeec STR	X6, [X22, X0,LSL #3]

        (864) 0x43aef0 LDR	X17, [X19, X0,LSL #3]

        (864) 0x43aef4 STR	X17, [X20, X6,LSL #3]

        (864) 0x43aef8 LDUR	X17, [X29, #496]

        (864) 0x43aefc LDR	D2, [X17]

        (864) 0x43af00 STR	D2, [X21, X6,LSL #3]

        (864) 0x43af04 ADD	X6, X6, #1

        (864) 0x43af08 B	43ae8c

    (850) 0x43af0c LDUR	X8, [X29, #480]

    (850) 0x43af10 LDR	X19, [X8]

    (850) 0x43af14 LDUR	X14, [X29, #424]

    (850) 0x43af18 LDUR	X13, [X29, #488]

    (850) 0x43af1c LDUR	X15, [X29, #440]

    (850) 0x43af20 LDR	X8, [X14, X27,LSL #3]

    (850) 0x43af24 LDR	X4, [X14, X30,LSL #3]

    (850) 0x43af28 LDR	D2, [X13, X8,LSL #3]

    (850) 0x43af2c ADD	X3, X8, #1

    (850) 0x43af30 CMP	X3, X4

    (850) 0x43af34 B.GE	43b38c

    (850) 0x43af38 LDP	X14, X13, [SP, #144]

    (850) 0x43af3c LDUR	X8, [X29, #432]

    (850) 0x43af40 LDR	X25, [X14]

    (850) 0x43af44 LDR	X14, [X13]

    (850) 0x43af48 LDR	X13, [SP, #128]

    (850) 0x43af4c LDR	X8, [X8]

    (850) 0x43af50 LDR	X26, [X13]

    (850) 0x43af54 LDR	X13, [SP, #136]

    (850) 0x43af58 LDR	X13, [X13]

    (850) 0x43af5c STP	X13, X14, [SP, #208]

    (850) 0x43af60 ADD	X13, X13, #8

    (850) 0x43af64 STR	X13, [SP, #200]

    (850) 0x43af68 B	43af8c

      (858) 0x43af6c LDUR	X14, [X29, #488]

      (858) 0x43af70 LDR	D4, [X8, X13,LSL #3]

      (858) 0x43af74 LDR	D3, [X14, X3,LSL #3]

      (858) 0x43af78 FADD	D3, D3, D4

      (858) 0x43af7c STR	D3, [X8, X13,LSL #3]

      (858) 0x43af80 ADD	X3, X3, #1

      (858) 0x43af84 CMP	X3, X4

      (858) 0x43af88 B.EQ	43b38c

      (858) 0x43af8c LDR	X20, [X15, X3,LSL #3]

      (858) 0x43af90 LDR	X13, [X22, X20,LSL #3]

      (858) 0x43af94 CMP	X13, X5

      (858) 0x43af98 B.GE	43af6c

      (858) 0x43af9c CMP	X13, X7

      (858) 0x43afa0 B.NE	43b024

      (858) 0x43afa4 LDUR	X13, [X29, #496]

      (858) 0x43afa8 LDUR	X15, [X29, #424]

      (858) 0x43afac ADD	X21, X20, #1

      (858) 0x43afb0 LDR	D4, [X13]

      (858) 0x43afb4 LDR	X14, [X15, X20,LSL #3]

      (858) 0x43afb8 LDUR	X13, [X29, #488]

      (858) 0x43afbc LDR	X16, [X15, X21,LSL #3]

      (858) 0x43afc0 LDR	D3, [X13, X14,LSL #3]

      (858) 0x43afc4 ADD	X2, X14, #1

      (858) 0x43afc8 FCMP	D3, #0

      (858) 0x43afcc FCSEL	D3, D1, D0, #4

      (858) 0x43afd0 CMP	X2, X16

      (858) 0x43afd4 B.GE	43b06c

      (858) 0x43afd8 SUB	W13, W14, W16

      (858) 0x43afdc TBNZ	W13, #0, 43b05c

      (858) 0x43afe0 LDUR	X13, [X29, #440]

      (858) 0x43afe4 LDR	X13, [X13, X2,LSL #3]

      (858) 0x43afe8 LDR	X15, [X22, X13,LSL #3]

      (858) 0x43afec CMP	X13, X27

      (858) 0x43aff0 CCMP	X15, X5, #0, #1

      (858) 0x43aff4 B.LT	43b010

      (858) 0x43aff8 LDUR	X13, [X29, #488]

      (858) 0x43affc LDR	D5, [X13, X2,LSL #3]

      (858) 0x43b000 FMUL	D6, D3, D5

      (858) 0x43b004 FCMP	D6, #0

      (858) 0x43b008 B.PL	43b010

      (858) 0x43b00c FADD	D4, D4, D5

      (858) 0x43b010 ADD	X18, X14, #2

      (858) 0x43b014 SUB	X13, X16, #2

      (858) 0x43b018 CMP	X13, X14

      (858) 0x43b01c B.EQ	43b06c

      (858) 0x43b020 B	43b0a8

      (858) 0x43b024 LDR	X13, [X10, X20,LSL #3]

      (858) 0x43b028 CMN	X13, #3

      (858) 0x43b02c B.EQ	43af80

      (858) 0x43b030 CMP	X25, #1

      (858) 0x43b034 B.EQ	43b04c

      (858) 0x43b038 LDR	X14, [SP, #216]

      (858) 0x43b03c LDR	X13, [X14, X27,LSL #3]

      (858) 0x43b040 LDR	X14, [X14, X20,LSL #3]

      (858) 0x43b044 CMP	X13, X14

      (858) 0x43b048 B.NE	43af80

      (858) 0x43b04c LDUR	X13, [X29, #488]

      (858) 0x43b050 LDR	D3, [X13, X3,LSL #3]

      (858) 0x43b054 FADD	D2, D2, D3

      (858) 0x43b058 B	43af80

      (858) 0x43b05c ORR	X18, XZR, X2

      (858) 0x43b060 SUB	X13, X16, #2

      (858) 0x43b064 CMP	X13, X14

      (858) 0x43b068 B.NE	43b0a8

      (858) 0x43b06c CMP	X19, #2

      (858) 0x43b070 B.LT	43b160

      (858) 0x43b074 LDR	X15, [X26, X20,LSL #3]

      (858) 0x43b078 LDR	X13, [X26, X21,LSL #3]

      (858) 0x43b07c CMP	X13, X15

      (858) 0x43b080 B.LE	43b160

      (858) 0x43b084 LDUR	X17, [X29, #360]

      (858) 0x43b088 LDR	X18, [X17]

      (858) 0x43b08c SUB	W17, W13, W15

      (858) 0x43b090 TBNZ	W17, #0, 43b124

      (858) 0x43b094 ORR	X0, XZR, X15

      (858) 0x43b098 ADD	X15, X15, #1

      (858) 0x43b09c CMP	X13, X15

      (858) 0x43b0a0 B.EQ	43b160

      (858) 0x43b0a4 B	43b248

      (858) 0x43b0a8 LDP	X17, X15, [X29, #880]

      (858) 0x43b0ac SUB	X13, X16, X18

      (858) 0x43b0b0 ADD	X15, X15, X18,LSL #3

      (858) 0x43b0b4 ADD	X18, X17, X18,LSL #3

      (858) 0x43b0b8 B	43b0d0

0x43b0bc HINT	#0

        (862) 0x43b0c0 ADD	X18, X18, #16

        (862) 0x43b0c4 SUBS	X13, X13, #2

        (862) 0x43b0c8 ADD	X15, X15, #16

        (862) 0x43b0cc B.EQ	43b06c

        (862) 0x43b0d0 LDUR	X17, [X18, #504]

        (862) 0x43b0d4 LDR	X0, [X22, X17,LSL #3]

        (862) 0x43b0d8 CMP	X17, X27

        (862) 0x43b0dc CCMP	X0, X5, #0, #1

        (862) 0x43b0e0 B.LT	43b0f8

        (862) 0x43b0e4 LDUR	D5, [X15, #504]

        (862) 0x43b0e8 FMUL	D6, D3, D5

        (862) 0x43b0ec FCMP	D6, #0

        (862) 0x43b0f0 B.PL	43b0f8

        (862) 0x43b0f4 FADD	D4, D4, D5

        (862) 0x43b0f8 LDR	X17, [X18]

        (862) 0x43b0fc LDR	X0, [X22, X17,LSL #3]

        (862) 0x43b100 CMP	X17, X27

        (862) 0x43b104 CCMP	X0, X5, #0, #1

        (862) 0x43b108 B.LT	43b0c0

        (862) 0x43b10c LDR	D5, [X15]

        (862) 0x43b110 FMUL	D6, D3, D5

        (862) 0x43b114 FCMP	D6, #0

        (862) 0x43b118 B.PL	43b0c0

        (862) 0x43b11c FADD	D4, D4, D5

        (862) 0x43b120 B	43b0c0

      (858) 0x43b124 LDR	X17, [SP, #208]

      (858) 0x43b128 LDR	X17, [X17, X15,LSL #3]

      (858) 0x43b12c LDR	X17, [X23, X17,LSL #3]

      (858) 0x43b130 CMP	X17, X9

      (858) 0x43b134 B.LT	43b14c

      (858) 0x43b138 LDR	D5, [X18, X15,LSL #3]

      (858) 0x43b13c FMUL	D6, D3, D5

      (858) 0x43b140 FCMP	D6, #0

      (858) 0x43b144 B.PL	43b14c

      (858) 0x43b148 FADD	D4, D4, D5

      (858) 0x43b14c ADD	X0, X15, #1

      (858) 0x43b150 ADD	X15, X15, #1

      (858) 0x43b154 CMP	X13, X15

      (858) 0x43b158 B.NE	43b248

      (858) 0x43b15c HINT	#0

      (858) 0x43b160 LDUR	X13, [X29, #488]

      (858) 0x43b164 FCMP	D4, #0

      (858) 0x43b168 LDR	D5, [X13, X3,LSL #3]

      (858) 0x43b16c B.EQ	43b23c

      (858) 0x43b170 FDIV	D4, D5, D4

      (858) 0x43b174 CMP	X2, X16

      (858) 0x43b178 B.GE	43b1f8

      (858) 0x43b17c LDUR	X13, [X29, #432]

      (858) 0x43b180 ORN	X15, XZR, X14

      (858) 0x43b184 ADD	X15, X15, X16

      (858) 0x43b188 LDP	X16, X17, [X29, #880]

      (858) 0x43b18c LDR	X13, [X13]

      (858) 0x43b190 ADD	X16, X16, X14,LSL #3

      (858) 0x43b194 ADD	X14, X17, X14,LSL #3

      (858) 0x43b198 B	43b1ac

0x43b19c HINT	#0

        (860) 0x43b1a0 SUBS	X15, X15, #1

        (860) 0x43b1a4 ADD	X14, X14, #8

        (860) 0x43b1a8 B.EQ	43b1f8

        (860) 0x43b1ac LDR	X18, [X16], #8

        (860) 0x43b1b0 LDR	X0, [X22, X18,LSL #3]

        (860) 0x43b1b4 CMP	X0, X5

        (860) 0x43b1b8 B.LT	43b1d8

        (860) 0x43b1bc LDR	D5, [X14]

        (860) 0x43b1c0 FMUL	D6, D3, D5

        (860) 0x43b1c4 FCMP	D6, #0

        (860) 0x43b1c8 B.PL	43b1d8

        (860) 0x43b1cc LDR	D6, [X13, X0,LSL #3]

        (860) 0x43b1d0 FMADD	D5, D4, D5, D6

        (860) 0x43b1d4 STR	D5, [X13, X0,LSL #3]

        (860) 0x43b1d8 CMP	X18, X27

        (860) 0x43b1dc B.NE	43b1a0

        (860) 0x43b1e0 LDR	D5, [X14]

        (860) 0x43b1e4 FMUL	D6, D3, D5

        (860) 0x43b1e8 FCMP	D6, #0

        (860) 0x43b1ec B.PL	43b1a0

        (860) 0x43b1f0 FMADD	D2, D4, D5, D2

        (860) 0x43b1f4 B	43b1a0

      (858) 0x43b1f8 CMP	X19, #2

      (858) 0x43b1fc B.LT	43b2fc

      (858) 0x43b200 LDR	X15, [X26, X20,LSL #3]

      (858) 0x43b204 LDR	X14, [X26, X21,LSL #3]

      (858) 0x43b208 CMP	X14, X15

      (858) 0x43b20c B.LE	43b2fc

      (858) 0x43b210 LDUR	X13, [X29, #360]

      (858) 0x43b214 SUB	W17, W14, W15

      (858) 0x43b218 LDR	X16, [X13]

      (858) 0x43b21c LDUR	X13, [X29, #400]

      (858) 0x43b220 LDR	X13, [X13]

      (858) 0x43b224 TBNZ	W17, #0, 43b2bc

      (858) 0x43b228 ORR	X18, XZR, X15

      (858) 0x43b22c ADD	X15, X15, #1

      (858) 0x43b230 CMP	X14, X15

      (858) 0x43b234 B.EQ	43b2fc

      (858) 0x43b238 B	43b304

      (858) 0x43b23c LDUR	X15, [X29, #440]

      (858) 0x43b240 FADD	D2, D2, D5

      (858) 0x43b244 B	43af80

      (858) 0x43b248 LDR	X15, [SP, #200]

      (858) 0x43b24c ADD	X17, X18, X0,LSL #3

      (858) 0x43b250 SUB	X13, X13, X0

      (858) 0x43b254 ADD	X18, X17, #8

      (858) 0x43b258 ADD	X15, X15, X0,LSL #3

      (858) 0x43b25c B	43b270

        (861) 0x43b260 SUBS	X13, X13, #2

        (861) 0x43b264 ADD	X15, X15, #16

        (861) 0x43b268 ADD	X18, X18, #16

        (861) 0x43b26c B.EQ	43b160

        (861) 0x43b270 LDUR	X17, [X15, #504]

        (861) 0x43b274 LDR	X17, [X23, X17,LSL #3]

        (861) 0x43b278 CMP	X17, X9

        (861) 0x43b27c B.LT	43b294

        (861) 0x43b280 LDUR	D5, [X18, #504]

        (861) 0x43b284 FMUL	D6, D3, D5

        (861) 0x43b288 FCMP	D6, #0

        (861) 0x43b28c B.PL	43b294

        (861) 0x43b290 FADD	D4, D4, D5

        (861) 0x43b294 LDR	X17, [X15]

        (861) 0x43b298 LDR	X17, [X23, X17,LSL #3]

        (861) 0x43b29c CMP	X17, X9

        (861) 0x43b2a0 B.LT	43b260

        (861) 0x43b2a4 LDR	D5, [X18]

        (861) 0x43b2a8 FMUL	D6, D3, D5

        (861) 0x43b2ac FCMP	D6, #0

        (861) 0x43b2b0 B.PL	43b260

        (861) 0x43b2b4 FADD	D4, D4, D5

        (861) 0x43b2b8 B	43b260

      (858) 0x43b2bc LDR	X17, [SP, #208]

      (858) 0x43b2c0 LDR	X17, [X17, X15,LSL #3]

      (858) 0x43b2c4 LDR	X18, [X23, X17,LSL #3]

      (858) 0x43b2c8 CMP	X18, X9

      (858) 0x43b2cc B.LT	43b2ec

      (858) 0x43b2d0 LDR	D5, [X16, X15,LSL #3]

      (858) 0x43b2d4 FMUL	D6, D3, D5

      (858) 0x43b2d8 FCMP	D6, #0

      (858) 0x43b2dc B.PL	43b2ec

      (858) 0x43b2e0 LDR	D6, [X13, X18,LSL #3]

      (858) 0x43b2e4 FMADD	D5, D4, D5, D6

      (858) 0x43b2e8 STR	D5, [X13, X18,LSL #3]

      (858) 0x43b2ec ADD	X18, X15, #1

      (858) 0x43b2f0 ADD	X15, X15, #1

      (858) 0x43b2f4 CMP	X14, X15

      (858) 0x43b2f8 B.NE	43b304

      (858) 0x43b2fc LDUR	X15, [X29, #440]

      (858) 0x43b300 B	43af80

      (858) 0x43b304 LDR	X15, [SP, #200]

      (858) 0x43b308 ADD	X16, X16, X18,LSL #3

      (858) 0x43b30c SUB	X14, X14, X18

      (858) 0x43b310 ADD	X16, X16, #8

      (858) 0x43b314 ADD	X15, X15, X18,LSL #3

      (858) 0x43b318 B	43b330

0x43b31c HINT	#0

        (859) 0x43b320 SUBS	X14, X14, #2

        (859) 0x43b324 ADD	X15, X15, #16

        (859) 0x43b328 ADD	X16, X16, #16

        (859) 0x43b32c B.EQ	43b2fc

        (859) 0x43b330 LDUR	X17, [X15, #504]

        (859) 0x43b334 LDR	X18, [X23, X17,LSL #3]

        (859) 0x43b338 CMP	X18, X9

        (859) 0x43b33c B.LT	43b35c

        (859) 0x43b340 LDUR	D5, [X16, #504]

        (859) 0x43b344 FMUL	D6, D3, D5

        (859) 0x43b348 FCMP	D6, #0

        (859) 0x43b34c B.PL	43b35c

        (859) 0x43b350 LDR	D6, [X13, X18,LSL #3]

        (859) 0x43b354 FMADD	D5, D4, D5, D6

        (859) 0x43b358 STR	D5, [X13, X18,LSL #3]

        (859) 0x43b35c LDR	X17, [X15]

        (859) 0x43b360 LDR	X18, [X23, X17,LSL #3]

        (859) 0x43b364 CMP	X18, X9

        (859) 0x43b368 B.LT	43b320

        (859) 0x43b36c LDR	D5, [X16]

        (859) 0x43b370 FMUL	D6, D3, D5

        (859) 0x43b374 FCMP	D6, #0

        (859) 0x43b378 B.PL	43b320

        (859) 0x43b37c LDR	D6, [X13, X18,LSL #3]

        (859) 0x43b380 FMADD	D5, D4, D5, D6

        (859) 0x43b384 STR	D5, [X13, X18,LSL #3]

        (859) 0x43b388 B	43b320

    (850) 0x43b38c CMP	X19, #2

    (850) 0x43b390 B.LT	43b5c0

    (850) 0x43b394 LDR	X13, [SP, #104]

    (850) 0x43b398 LDR	X8, [X13, X27,LSL #3]

    (850) 0x43b39c LDR	X14, [X13, X30,LSL #3]

    (850) 0x43b3a0 CMP	X8, X14

    (850) 0x43b3a4 B.GE	43b5c0

    (850) 0x43b3a8 LDUR	X13, [X29, #360]

    (850) 0x43b3ac LDR	X19, [X28]

    (850) 0x43b3b0 LDR	X16, [X13]

    (850) 0x43b3b4 LDUR	X13, [X29, #400]

    (850) 0x43b3b8 LDR	X2, [X13]

    (850) 0x43b3bc LDUR	X13, [X29, #336]

    (850) 0x43b3c0 LDR	X3, [X13]

    (850) 0x43b3c4 LDR	X13, [SP, #144]

    (850) 0x43b3c8 LDR	X15, [X13]

    (850) 0x43b3cc LDR	X13, [SP, #152]

    (850) 0x43b3d0 LDR	X13, [X13]

    (850) 0x43b3d4 STP	X13, X15, [SP, #208]

    (850) 0x43b3d8 LDR	X13, [SP, #96]

    (850) 0x43b3dc LDR	X13, [X13]

    (850) 0x43b3e0 STR	X13, [SP, #200]

    (850) 0x43b3e4 LDP	X15, X13, [SP, #80]

    (850) 0x43b3e8 LDR	X21, [X15]

    (850) 0x43b3ec LDR	X30, [X13]

    (850) 0x43b3f0 ADD	X26, X21, #8

    (850) 0x43b3f4 B	43b41c

0x43b3f8 HINT	#0

0x43b3fc HINT	#0

      (855) 0x43b400 LDR	D3, [X16, X8,LSL #3]

      (855) 0x43b404 LDR	D4, [X2, X15,LSL #3]

      (855) 0x43b408 FADD	D3, D3, D4

      (855) 0x43b40c STR	D3, [X2, X15,LSL #3]

      (855) 0x43b410 ADD	X8, X8, #1

      (855) 0x43b414 CMP	X8, X14

      (855) 0x43b418 B.EQ	43b5c0

      (855) 0x43b41c LDUR	X13, [X29, #448]

      (855) 0x43b420 LDR	X13, [X13, X8,LSL #3]

      (855) 0x43b424 LDR	X15, [X23, X13,LSL #3]

      (855) 0x43b428 CMP	X15, X9

      (855) 0x43b42c B.GE	43b400

      (855) 0x43b430 CMP	X15, X7

      (855) 0x43b434 B.NE	43b4c0

      (855) 0x43b438 LDUR	X15, [X29, #496]

      (855) 0x43b43c LDR	X4, [X21, X13,LSL #3]

      (855) 0x43b440 LDR	X13, [X26, X13,LSL #3]

      (855) 0x43b444 LDR	D3, [X15]

      (855) 0x43b448 CMP	X13, X4

      (855) 0x43b44c B.LE	43b4f0

      (855) 0x43b450 LDUR	X17, [X29, #296]

      (855) 0x43b454 LDR	X15, [X24]

      (855) 0x43b458 ORR	X0, XZR, X4

      (855) 0x43b45c LDR	X18, [X17]

      (855) 0x43b460 B	43b478

        (857) 0x43b464 LDR	D4, [X18, X0,LSL #3]

        (857) 0x43b468 FADD	D3, D3, D4

        (857) 0x43b46c ADD	X0, X0, #1

        (857) 0x43b470 CMP	X13, X0

        (857) 0x43b474 B.EQ	43b4fc

        (857) 0x43b478 LDR	X17, [X30, X0,LSL #3]

        (857) 0x43b47c SUBS	X20, X17, X19

        (857) 0x43b480 CCMP	X17, X15, #0, #10

        (857) 0x43b484 B.LT	43b4a0

        (857) 0x43b488 ORN	X17, XZR, X17

        (857) 0x43b48c LDR	X17, [X23, X17,LSL #3]

        (857) 0x43b490 CMP	X17, X9

        (857) 0x43b494 B.GE	43b464

        (857) 0x43b498 B	43b46c

0x43b49c HINT	#0

        (857) 0x43b4a0 LDR	X17, [X22, X20,LSL #3]

        (857) 0x43b4a4 CMP	X20, X27

        (857) 0x43b4a8 CCMP	X17, X5, #0, #1

        (857) 0x43b4ac B.LT	43b46c

        (857) 0x43b4b0 B	43b464

0x43b4b4 HINT	#0

0x43b4b8 HINT	#0

0x43b4bc HINT	#0

      (855) 0x43b4c0 LDR	X15, [X3, X13,LSL #3]

      (855) 0x43b4c4 CMN	X15, #3

      (855) 0x43b4c8 B.EQ	43b410

      (855) 0x43b4cc LDR	X15, [SP, #216]

      (855) 0x43b4d0 CMP	X15, #1

      (855) 0x43b4d4 B.EQ	43b5b4

      (855) 0x43b4d8 LDP	X17, X15, [SP, #200]

      (855) 0x43b4dc LDR	X15, [X15, X27,LSL #3]

      (855) 0x43b4e0 LDR	X13, [X17, X13,LSL #3]

      (855) 0x43b4e4 CMP	X15, X13

      (855) 0x43b4e8 B.NE	43b410

      (855) 0x43b4ec B	43b5b4

      (855) 0x43b4f0 FCMP	D3, #0

      (855) 0x43b4f4 B.NE	43b410

      (855) 0x43b4f8 B	43b5b4

      (855) 0x43b4fc FCMP	D3, #0

      (855) 0x43b500 B.EQ	43b5b4

      (855) 0x43b504 SUBS	X13, X13, X4

      (855) 0x43b508 B.LE	43b410

      (855) 0x43b50c LDR	D4, [X16, X8,LSL #3]

      (855) 0x43b510 LDUR	X15, [X29, #296]

      (855) 0x43b514 LDUR	X18, [X29, #432]

      (855) 0x43b518 ADD	X20, X30, X4,LSL #3

      (855) 0x43b51c FDIV	D3, D4, D3

      (855) 0x43b520 LDR	X17, [X15]

      (855) 0x43b524 LDUR	X15, [X29, #400]

      (855) 0x43b528 LDR	X18, [X18]

      (855) 0x43b52c LDR	X15, [X15]

      (855) 0x43b530 ADD	X4, X17, X4,LSL #3

      (855) 0x43b534 B	43b54c

0x43b538 HINT	#0

0x43b53c HINT	#0

        (856) 0x43b540 ADD	X4, X4, #8

        (856) 0x43b544 SUBS	X13, X13, #1

        (856) 0x43b548 B.EQ	43b410

        (856) 0x43b54c LDR	X17, [X20], #8

        (856) 0x43b550 LDR	X25, [X24]

        (856) 0x43b554 SUBS	X0, X17, X19

        (856) 0x43b558 CCMP	X17, X25, #0, #10

        (856) 0x43b55c B.LT	43b584

        (856) 0x43b560 ORN	X17, XZR, X17

        (856) 0x43b564 LDR	X17, [X23, X17,LSL #3]

        (856) 0x43b568 CMP	X17, X9

        (856) 0x43b56c B.LT	43b540

        (856) 0x43b570 LDR	D4, [X4]

        (856) 0x43b574 LDR	D5, [X15, X17,LSL #3]

        (856) 0x43b578 FMADD	D4, D3, D4, D5

        (856) 0x43b57c STR	D4, [X15, X17,LSL #3]

        (856) 0x43b580 B	43b540

        (856) 0x43b584 LDR	X17, [X22, X0,LSL #3]

        (856) 0x43b588 CMP	X17, X5

        (856) 0x43b58c B.LT	43b5a0

        (856) 0x43b590 LDR	D4, [X4]

        (856) 0x43b594 LDR	D5, [X18, X17,LSL #3]

        (856) 0x43b598 FMADD	D4, D3, D4, D5

        (856) 0x43b59c STR	D4, [X18, X17,LSL #3]

        (856) 0x43b5a0 CMP	X0, X27

        (856) 0x43b5a4 B.NE	43b540

        (856) 0x43b5a8 LDR	D4, [X4]

        (856) 0x43b5ac FMADD	D2, D3, D4, D2

        (856) 0x43b5b0 B	43b540

      (855) 0x43b5b4 LDR	D3, [X16, X8,LSL #3]

      (855) 0x43b5b8 FADD	D2, D2, D3

      (855) 0x43b5bc B	43b410

    (850) 0x43b5c0 FCMP	D2, #0

    (850) 0x43b5c4 B.EQ	43b6e4

    (850) 0x43b5c8 LDUR	X19, [X29, #328]

    (850) 0x43b5cc LDUR	X26, [X29, #416]

    (850) 0x43b5d0 LDR	X17, [SP, #176]

    (850) 0x43b5d4 SUBS	X8, X6, X5

    (850) 0x43b5d8 B.LE	43b654

    (850) 0x43b5dc FNEG	D3, D2

    (850) 0x43b5e0 CMP	X8, #3

    (850) 0x43b5e4 B.LS	43b628

    (850) 0x43b5e8 LDR	X15, [SP, #64]

    (850) 0x43b5ec AND	X13, X8, #8062

    (850) 0x43b5f0 DUP	V4.2D, V3.D[0]

    (850) 0x43b5f4 ADD	X14, X5, X13

    (850) 0x43b5f8 ORR	X16, XZR, X13

    (850) 0x43b5fc ADD	X15, X15, X5,LSL #3

      (854) 0x43b600 LDP	Q5, Q6, [X15, #2032]

      (854) 0x43b604 SUBS	X16, X16, #4

      (854) 0x43b608 FDIV	V6.2D, V6.2D, V4.2D

      (854) 0x43b60c FDIV	V5.2D, V5.2D, V4.2D

      (854) 0x43b610 STP	Q5, Q6, [X15, #2032]

      (854) 0x43b614 ADD	X15, X15, #32

      (854) 0x43b618 B.NE	43b600

    (850) 0x43b61c ORR	X5, XZR, X14

    (850) 0x43b620 CMP	X8, X13

    (850) 0x43b624 B.EQ	43b654

    (850) 0x43b628 ADD	X8, X17, X5,LSL #3

    (850) 0x43b62c SUB	X13, X6, X5

    (850) 0x43b630 HINT	#0

    (850) 0x43b634 HINT	#0

    (850) 0x43b638 HINT	#0

    (850) 0x43b63c HINT	#0

      (853) 0x43b640 LDR	D4, [X8]

      (853) 0x43b644 SUBS	X13, X13, #1

      (853) 0x43b648 FDIV	D4, D4, D3

      (853) 0x43b64c STR	D4, [X8], #8

      (853) 0x43b650 B.NE	43b640

    (850) 0x43b654 SUBS	X8, X1, X9

    (850) 0x43b658 B.LE	43b6d4

    (850) 0x43b65c FNEG	D2, D2

    (850) 0x43b660 CMP	X8, #3

    (850) 0x43b664 B.LS	43b6a8

    (850) 0x43b668 LDR	X15, [SP, #56]

    (850) 0x43b66c AND	X13, X8, #8062

    (850) 0x43b670 DUP	V3.2D, V2.D[0]

    (850) 0x43b674 ADD	X14, X9, X13

    (850) 0x43b678 ADD	X9, X15, X9,LSL #3

    (850) 0x43b67c ORR	X15, XZR, X13

      (852) 0x43b680 LDP	Q4, Q5, [X9, #2032]

      (852) 0x43b684 SUBS	X15, X15, #4

      (852) 0x43b688 FDIV	V5.2D, V5.2D, V3.2D

      (852) 0x43b68c FDIV	V4.2D, V4.2D, V3.2D

      (852) 0x43b690 STP	Q4, Q5, [X9, #2032]

      (852) 0x43b694 ADD	X9, X9, #32

      (852) 0x43b698 B.NE	43b680

    (850) 0x43b69c ORR	X9, XZR, X14

    (850) 0x43b6a0 CMP	X8, X13

    (850) 0x43b6a4 B.EQ	43b6d4

    (850) 0x43b6a8 LDR	X8, [SP, #72]

    (850) 0x43b6ac ADD	X8, X8, X9,LSL #3

    (850) 0x43b6b0 SUB	X9, X1, X9

    (850) 0x43b6b4 HINT	#0

    (850) 0x43b6b8 HINT	#0

    (850) 0x43b6bc HINT	#0

      (851) 0x43b6c0 LDR	D3, [X8]

      (851) 0x43b6c4 SUBS	X9, X9, #1

      (851) 0x43b6c8 FDIV	D3, D3, D2

      (851) 0x43b6cc STR	D3, [X8], #8

      (851) 0x43b6d0 B.NE	43b6c0

    (850) 0x43b6d4 LDUR	X9, [X29, #320]

    (850) 0x43b6d8 LDUR	X13, [X29, #384]

    (850) 0x43b6dc LDR	X14, [SP, #192]

    (850) 0x43b6e0 B	43b6f8

    (850) 0x43b6e4 LDP	X9, X19, [X29, #832]

    (850) 0x43b6e8 LDUR	X13, [X29, #384]

    (850) 0x43b6ec LDR	X14, [SP, #192]

    (850) 0x43b6f0 LDUR	X26, [X29, #416]

    (850) 0x43b6f4 LDR	X17, [SP, #176]

    (850) 0x43b6f8 LDP	X18, X15, [SP, #160]

    (850) 0x43b6fc B	43ab7c

  (848) 0x43b700 ADD	SP, SP, #448

  (848) 0x43b704 LDP	X20, X19, [SP, #80]

  (848) 0x43b708 LDP	X22, X21, [SP, #64]

  (848) 0x43b70c LDP	X24, X23, [SP, #48]

  (848) 0x43b710 LDP	X26, X25, [SP, #32]

  (848) 0x43b714 LDP	X28, X27, [SP, #16]

  (848) 0x43b718 LDP	X29, X30, [SP], #96

  (848) 0x43b71c RET

  (848) 0x43b720 LDR	X13, [SP, #72]

  (848) 0x43b724 UBFM	X17, X1, #61, #60

  (848) 0x43b728 ADD	X15, X15, X25,LSL #3

  (848) 0x43b72c ADD	X3, X16, X25,LSL #3

  (848) 0x43b730 ADD	X17, X17, #8

  (848) 0x43b734 ADD	X1, X11, X17

  (848) 0x43b738 ADD	X2, X12, X17

  (848) 0x43b73c MADD	X13, X25, X13, XZR

  (848) 0x43b740 UBFM	X14, X13, #61, #60

  (848) 0x43b744 ADD	X13, X14, #8

  (848) 0x43b748 ADD	X0, X11, X13

  (848) 0x43b74c ADD	X13, X12, X13

  (848) 0x43b750 CMP	X0, X15

  (848) 0x43b754 CCMP	X9, X1, #2, #3

  (848) 0x43b758 CSINC	W18, WZR, WZR, #2

  (848) 0x43b75c CMP	X0, X3

  (848) 0x43b760 CCMP	X10, X1, #2, #3

  (848) 0x43b764 CSINC	W17, WZR, WZR, #2

  (848) 0x43b768 CMP	X13, X15

  (848) 0x43b76c CCMP	X9, X2, #2, #3

  (848) 0x43b770 CSINC	W16, WZR, WZR, #2

  (848) 0x43b774 CMP	X13, X3

  (848) 0x43b778 CCMP	X10, X2, #2, #3

  (848) 0x43b77c CSINC	W15, WZR, WZR, #2

  (848) 0x43b780 CMP	X13, X1

  (848) 0x43b784 LDUR	X1, [X29, #384]

  (848) 0x43b788 ORR	X13, XZR, X27

  (848) 0x43b78c CCMP	X0, X2, #2, #3

  (848) 0x43b790 B.CC	43a7a8

  (848) 0x43b794 ORR	X13, XZR, X27

  (848) 0x43b798 TBNZ	W18, #0, 43a7a8

  (848) 0x43b79c ORR	X13, XZR, X27

  (848) 0x43b7a0 TBNZ	W17, #0, 43a7a8

  (848) 0x43b7a4 ORR	X13, XZR, X27

  (848) 0x43b7a8 TBNZ	W16, #0, 43a7a8

  (848) 0x43b7ac ORR	X13, XZR, X27

  (848) 0x43b7b0 TBNZ	W15, #0, 43a7a8

  (848) 0x43b7b4 LD1R	{V0.2D}, [X9]

  (848) 0x43b7b8 LD1R	{V1.2D}, [X10]

  (848) 0x43b7bc AND	X15, X8, #8062

  (848) 0x43b7c0 ADD	X16, X14, #24

  (848) 0x43b7c4 ADD	X13, X27, X15

  (848) 0x43b7c8 ADD	X14, X12, X16

  (848) 0x43b7cc ADD	X16, X11, X16

  (848) 0x43b7d0 ORR	X17, XZR, X15

  (848) 0x43b7d4 HINT	#0

  (848) 0x43b7d8 HINT	#0

  (848) 0x43b7dc HINT	#0

    (849) 0x43b7e0 LDP	Q2, Q3, [X16, #2032]

    (849) 0x43b7e4 SUBS	X17, X17, #4

    (849) 0x43b7e8 ADD	V3.2D, V3.2D, V0.2D

    (849) 0x43b7ec ADD	V2.2D, V2.2D, V0.2D

    (849) 0x43b7f0 STP	Q2, Q3, [X16, #2032]

    (849) 0x43b7f4 LDP	Q2, Q3, [X14, #2032]

    (849) 0x43b7f8 ADD	X16, X16, #32

    (849) 0x43b7fc ADD	V3.2D, V3.2D, V1.2D

    (849) 0x43b800 ADD	V2.2D, V2.2D, V1.2D

    (849) 0x43b804 STP	Q2, Q3, [X14, #2032]

    (849) 0x43b808 ADD	X14, X14, #32

    (849) 0x43b80c B.NE	43b7e0

  (848) 0x43b810 CMP	X8, X15

  (848) 0x43b814 B.NE	43a7a8

  (848) 0x43b818 B	43a7e8

(847) 0x43b81c LDUR	X9, [X29, #408]

(847) 0x43b820 LDR	X11, [SP, #72]

(847) 0x43b824 LDR	X10, [X9]

(847) 0x43b828 LDR	X9, [X21]

(847) 0x43b82c MADD	X11, X25, X11, XZR

(847) 0x43b830 ADD	X9, X9, X25,LSL #3

(847) 0x43b834 ADD	X10, X10, X11,LSL #3

(847) 0x43b838 B	43b84c

0x43b83c HINT	#0

(847) 0x43b840 ADD	X10, X10, #8

(847) 0x43b844 SUBS	X8, X8, #1

(847) 0x43b848 B.EQ	43a7f0

(847) 0x43b84c LDR	X11, [X10]

(847) 0x43b850 TBNZ	X11, #63, 43b840

(847) 0x43b854 LDUR	X12, [X9, #504]

(847) 0x43b858 ADD	X11, X12, X11

(847) 0x43b85c STR	X11, [X10]

(847) 0x43b860 B	43b840

0x43b864 HINT	#0

0x43b868 HINT	#0

0x43b86c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_lr_interp.c:1196-1757
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1196,1219-1238,1244-1254,1262-1303,1311-1350,1363-1417,1423-1459,1467-1471,1480-1483,1491-1496,1503-1545,1553-1596,1607-1660,1667-1724,1733-1748,1754-1757.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 53.00 to 41.92 cycles (1.26x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 53.00 to 3.50 cycles (15.14x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 916 bytes. The binary function is storing 608 bytes.

General properties

nb instructions	288
loop length	1152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	12.50	12.50	12.00	12.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	53.00	53.00	53.00	32.00	32.00
cycles	12.50	12.50	12.00	12.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	53.00	53.00	53.00	32.00	32.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	30.63
Overall L1	53.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 53.00 cycles. At this rate:

18% of peak load performance is reached (17.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43a020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X7, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X6, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X21, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X28, X24, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X10, [X29, #816]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X11, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 43a1f8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43a194 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X26, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 43a20c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43a20c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
B 43a20c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X26, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X0, 43a1ac <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X19, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X27, X10, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X14, X8, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X14, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X14, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 43a370 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X28, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4ec25c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W28, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ec280>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W20, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X19, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 43a74c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43a74c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X9, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X11, X14, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W12, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X11, X15, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W13, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X9, X15, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 43a708 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W12, #0, 43a708 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W13, 43a708 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X9], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X11], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X10], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
B 43a74c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X16, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 43a400 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD X11, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <4ec74c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X1, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X25, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43a7f0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X1, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43a7f0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X13, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X16, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X16, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 43b720 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD SP, SP, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 4a91d0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_lr_interp.c:1196-1757
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 53.00 to 3.50 cycles (15.14x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 916 bytes. The binary function is storing 608 bytes.

General properties

nb instructions	288
loop length	1152
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	12.50	12.50	12.00	12.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	53.00	53.00	53.00	32.00	32.00
cycles	12.50	12.50	12.00	12.00	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	53.00	53.00	53.00	32.00	32.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	30.63
Overall L1	53.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 53.00 cycles. At this rate:

18% of peak load performance is reached (17.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43a020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X7, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X6, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X20, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X19, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X5, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X26, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X25, X21, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X27, X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X10, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X28, X24, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X10, [X29, #816]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X11, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 43a1f8 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43a194 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X26, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 43a20c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43a20c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
B 43a20c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STP X26, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBNZ X0, 43a1ac <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X9, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X19, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X26, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X27, X10, X21, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X10, X10, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X14, X8, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X14, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X14, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GT 43a370 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x350>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X28, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X0, <4ec25c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W28, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR W1, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4ec280>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1248	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X8, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W20, WZR, W28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X19, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X28, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBNZ X25, 43a74c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X12, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43a74c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X10, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X9, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X9, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X11, X14, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W12, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X10, X13	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X11, X15, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
CSINC W13, WZR, WZR, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CCMP X9, X15, #2, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	1	scal (50.0%)
B.CC 43a708 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
TBNZ W12, #0, 43a708 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBNZ W13, 43a708 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X9], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X11], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X10], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
B 43a74c <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X18, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X19, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X25, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X11, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X9, [X29, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X9, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STUR X16, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 43a400 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADD X11, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X10, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADRP X0, <4ec74c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X0, X0, #1272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 40f890 <@plt_start@+0x510>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X1, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X25, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43a7f0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUBS X8, X1, X27	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LE 43a7f0 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x7d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X9, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X13, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X16, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X9, X25, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X10, X9, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X9, X15, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X16, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #15	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.HI 43b720 <hypre_BoomerAMGBuildExtPIInterp.omp_outlined+0x1700>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD SP, SP, #448	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 4a91d0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildExtPIInterp.omp_outlined–	0.23	0.04
○Loop 885 - par_lr_interp.c:1224-1225 - exec	0.01	0.00
○Loop 873 - par_lr_interp.c:1378-1382 - exec	0.00	0.00
▼Loop 878 - par_lr_interp.c:1244-1350 - exec–	0.00	0.00
▼Loop 879 - par_lr_interp.c:1244-1350 - exec–	0.00	0.00
▼Loop 877 - par_lr_interp.c:1244-1341 - exec–	0.00	0.00
▼Loop 876 - par_lr_interp.c:1244-1341 - exec–	0.00	0.00
▼Loop 880 - par_lr_interp.c:1264-1303 - exec–	0.00	0.00
○Loop 883 - par_lr_interp.c:1277-1285 - exec	0.02	0.01
○Loop 882 - par_lr_interp.c:1291-1303 - exec	0.00	0.00
○Loop 881 - par_lr_interp.c:1291-1303 - exec	0.00	0.00
○Loop 875 - par_lr_interp.c:1244-1262 - exec	0.00	0.00
○Loop 874 - par_lr_interp.c:1378-1382 - exec	0.00	0.00
○Loop 884 - par_lr_interp.c:1230-1231 - exec	0.00	0.00
▼Loop 847 - par_lr_interp.c:1196-1757 - exec–	0.00	0.00
▼Loop 848 - par_lr_interp.c:1196-1757 - exec–	0.00	0.00
○Loop 870 - par_lr_interp.c:1455-1456 - exec	0.01	0.00
▼Loop 850 - par_lr_interp.c:1469-1748 - exec–	0.00	0.00
▼Loop 858 - par_lr_interp.c:1609-1675 - exec–	0.04	0.01
○Loop 862 - par_lr_interp.c:1624-1628 - exec	0.06	0.01
○Loop 860 - par_lr_interp.c:1644-1651 - exec	0.04	0.01
○Loop 861 - par_lr_interp.c:1632-1637 - exec	0.00	0.00
○Loop 859 - par_lr_interp.c:1655-1660 - exec	0.00	0.00
▼Loop 865 - par_lr_interp.c:1494-1545 - exec–	0.00	0.01
○Loop 868 - par_lr_interp.c:1516-1526 - exec	0.03	0.01
○Loop 867 - par_lr_interp.c:1532-1545 - exec	0.00	0.00
○Loop 866 - par_lr_interp.c:1532-1545 - exec	0.00	0.00
○Loop 854 - par_lr_interp.c:1743-1743 - exec	0.00	0.00
▼Loop 863 - par_lr_interp.c:1555-1596 - exec–	0.00	0.00
○Loop 864 - par_lr_interp.c:1573-1596 - exec	0.00	0.00
○Loop 851 - par_lr_interp.c:1744-1745 - exec	0.00	0.00
○Loop 852 - par_lr_interp.c:1745-1745 - exec	0.00	0.00
▼Loop 855 - par_lr_interp.c:1680-1735 - exec–	0.00	0.00
○Loop 856 - par_lr_interp.c:1707-1724 - exec	0.00	0.00
○Loop 857 - par_lr_interp.c:1688-1700 - exec	0.00	0.00
○Loop 853 - par_lr_interp.c:1742-1743 - exec	0.00	0.00
○Loop 849 - par_lr_interp.c:1393-1396 - exec	0.00	0.00
○Loop 846 - par_lr_interp.c:1393-1396 - exec	0.00	0.00
○Loop 872 - par_lr_interp.c:1444-1445 - exec	0.00	0.00
○Loop 871 - par_lr_interp.c:1451-1452 - exec	0.00	0.00
○Loop 869 - par_lr_interp.c:1458-1459 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code