OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.20	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage (incl. loops): 1.43% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x436b30 SUB	SP, SP, #480

0x436b34 STP	X29, X30, [SP, #384]

0x436b38 STP	X28, X27, [SP, #400]

0x436b3c STP	X26, X25, [SP, #416]

0x436b40 STP	X24, X23, [SP, #432]

0x436b44 STP	X22, X21, [SP, #448]

0x436b48 STP	X20, X19, [SP, #464]

0x436b4c ADD	X29, SP, #384

0x436b50 LDR	X8, [X29, #376]

0x436b54 STUR	X7, [X29, #424]

0x436b58 LDR	X0, [X2]

0x436b5c ORR	X22, XZR, X6

0x436b60 ORR	X26, XZR, X5

0x436b64 ORR	X21, XZR, X4

0x436b68 ORR	X24, XZR, X3

0x436b6c ORR	X25, XZR, X2

0x436b70 STR	X8, [SP, #136]

0x436b74 LDR	X8, [X29, #368]

0x436b78 STR	X8, [SP, #128]

0x436b7c LDR	X8, [X29, #360]

0x436b80 STR	X8, [SP, #120]

0x436b84 LDR	X8, [X29, #352]

0x436b88 STR	X8, [SP, #112]

0x436b8c LDR	X8, [X29, #344]

0x436b90 STR	X8, [SP, #104]

0x436b94 LDR	X8, [X29, #336]

0x436b98 STR	X8, [SP, #96]

0x436b9c LDR	X8, [X29, #328]

0x436ba0 STR	X8, [SP, #88]

0x436ba4 LDR	X8, [X29, #320]

0x436ba8 STR	X8, [SP, #80]

0x436bac LDR	X8, [X29, #312]

0x436bb0 STR	X8, [SP, #72]

0x436bb4 LDP	X8, X20, [X29, #296]

0x436bb8 STUR	X8, [X29, #488]

0x436bbc LDP	X8, X9, [X29, #280]

0x436bc0 STP	X8, X9, [X29, #944]

0x436bc4 LDR	X8, [X29, #272]

0x436bc8 STR	X8, [SP, #64]

0x436bcc LDR	X8, [X29, #264]

0x436bd0 STR	X8, [SP, #160]

0x436bd4 LDP	X10, X9, [X29, #248]

0x436bd8 STUR	X9, [X29, #496]

0x436bdc LDP	X11, X9, [X29, #232]

0x436be0 STP	X9, X10, [X29, #960]

0x436be4 LDP	X10, X9, [X29, #216]

0x436be8 STP	X11, X9, [X29, #856]

0x436bec LDP	X8, X9, [X29, #200]

0x436bf0 STUR	X8, [X29, #384]

0x436bf4 LDR	X8, [X29, #192]

0x436bf8 STP	X10, X9, [X29, #872]

0x436bfc STR	X8, [SP, #152]

0x436c00 LDP	X10, X9, [X29, #176]

0x436c04 STUR	X9, [X29, #472]

0x436c08 LDP	X8, X9, [X29, #160]

0x436c0c STP	X10, X8, [X29, #904]

0x436c10 LDR	X8, [X29, #152]

0x436c14 STUR	X9, [X29, #376]

0x436c18 STR	X8, [SP, #144]

0x436c1c LDP	X10, X9, [X29, #136]

0x436c20 LDP	X27, X23, [X29, #104]

0x436c24 LDR	X28, [X29, #96]

0x436c28 STUR	X9, [X29, #464]

0x436c2c LDP	X8, X9, [X29, #120]

0x436c30 STUR	X9, [X29, #336]

0x436c34 STP	X10, X8, [X29, #920]

0x436c38 CBZ	X0, 436c74

0x436c3c MOVZ	W1, #8

0x436c40 BL	4a90d0

0x436c44 ORR	X19, XZR, X0

0x436c48 LDR	X0, [X24]

0x436c4c CBZ	X0, 436c58

0x436c50 MOVZ	W1, #8

0x436c54 BL	4a90d0

0x436c58 STUR	X0, [X29, #480]

0x436c5c LDR	X0, [X21]

0x436c60 CBZ	X0, 436c84

0x436c64 MOVZ	W1, #8

0x436c68 BL	4a90d0

0x436c6c ORR	X21, XZR, X0

0x436c70 B	436c88

0x436c74 ORR	X19, XZR, XZR

0x436c78 LDR	X0, [X24]

0x436c7c CBNZ	X0, 436c50

0x436c80 B	436c58

0x436c84 ORR	X21, XZR, XZR

0x436c88 LDR	X8, [X26]

0x436c8c LDR	X9, [X22]

0x436c90 MOVZ	W1, #8

0x436c94 CMP	X8, X9

0x436c98 CSEL	X0, X8, X9, #12

0x436c9c BL	4a90d0

0x436ca0 LDR	X8, [X25]

0x436ca4 ORR	X22, XZR, X0

0x436ca8 CMP	X8, #1

0x436cac B.LT	436cd4

0x436cb0 MOVN	X9, #0

0x436cb4 ORR	X8, XZR, XZR

0x436cb8 HINT	#0

0x436cbc HINT	#0

(778) 0x436cc0 STR	X9, [X19, X8,LSL #3]

(778) 0x436cc4 ADD	X8, X8, #1

(778) 0x436cc8 LDR	X10, [X25]

(778) 0x436ccc CMP	X8, X10

(778) 0x436cd0 B.LT	436cc0

0x436cd4 LDR	X8, [X24]

0x436cd8 LDUR	X11, [X29, #480]

0x436cdc CMP	X8, #1

0x436ce0 B.LT	436d00

0x436ce4 MOVN	X9, #0

0x436ce8 ORR	X8, XZR, XZR

(777) 0x436cec STR	X9, [X11, X8,LSL #3]

(777) 0x436cf0 ADD	X8, X8, #1

(777) 0x436cf4 LDR	X10, [X24]

(777) 0x436cf8 CMP	X8, X10

(777) 0x436cfc B.LT	436cec

0x436d00 BL	4aae50

0x436d04 ORR	X24, XZR, X0

0x436d08 BL	4aae30

0x436d0c LDR	X9, [X27]

0x436d10 SUB	X11, X0, #1

0x436d14 CMP	X24, X11

0x436d18 SDIV	X10, X9, X0

0x436d1c MADD	X8, X10, X24, XZR

0x436d20 ADD	X10, X10, X8

0x436d24 CSEL	X9, X9, X10, #0

0x436d28 CMP	X8, X9

0x436d2c B.GE	437578

0x436d30 LDUR	X10, [X29, #424]

0x436d34 LDUR	X12, [X29, #464]

0x436d38 LDR	X11, [X28]

0x436d3c LDR	X10, [X10]

0x436d40 LDR	X13, [X12]

0x436d44 LDR	X12, [SP, #144]

0x436d48 LDR	X15, [X12]

0x436d4c LDUR	X12, [X29, #472]

0x436d50 LDR	X10, [X10, X11,LSL #3]

0x436d54 LDR	X11, [X23]

0x436d58 LDR	X16, [X12]

0x436d5c LDR	X12, [SP, #152]

0x436d60 STUR	X11, [X29, #424]

0x436d64 LDUR	X11, [X29, #416]

0x436d68 ADD	X9, X9, X10

0x436d6c LDR	X11, [X11]

0x436d70 LDR	X12, [X12]

0x436d74 STUR	X11, [X29, #416]

0x436d78 LDUR	X11, [X29, #336]

0x436d7c LDR	X14, [X11]

0x436d80 LDUR	X11, [X29, #408]

0x436d84 LDR	X0, [X11]

0x436d88 LDUR	X11, [X29, #400]

0x436d8c LDR	X11, [X11]

0x436d90 STUR	X11, [X29, #400]

0x436d94 LDUR	X11, [X29, #376]

0x436d98 STUR	X9, [X29, #376]

0x436d9c ADD	X9, X8, X10

0x436da0 LDP	X8, X10, [X29, #872]

0x436da4 LDR	X3, [X10]

0x436da8 LDR	X4, [X8]

0x436dac LDP	X8, X10, [X29, #856]

0x436db0 LDR	X17, [X11]

0x436db4 LDUR	X11, [X29, #392]

0x436db8 LDR	X5, [X10]

0x436dbc LDR	X6, [X8]

0x436dc0 LDP	X10, X8, [X29, #960]

0x436dc4 LDR	X1, [X11]

0x436dc8 LDUR	X11, [X29, #384]

0x436dcc LDR	X8, [X8]

0x436dd0 LDR	X2, [X11]

0x436dd4 LDR	X7, [X10]

0x436dd8 ADD	X10, X13, #8

0x436ddc STUR	X8, [X29, #328]

0x436de0 LDUR	X8, [X29, #496]

0x436de4 LDR	X8, [X8]

0x436de8 STUR	X8, [X29, #496]

0x436dec LDUR	X8, [X29, #488]

0x436df0 LDR	X8, [X8]

0x436df4 STR	X8, [SP, #192]

0x436df8 LDR	X8, [X20]

0x436dfc STUR	X8, [X29, #488]

0x436e00 LDR	X8, [SP, #160]

0x436e04 STP	X12, X15, [SP, #48]

0x436e08 STR	X16, [SP, #168]

0x436e0c LDR	X8, [X8]

0x436e10 STP	X13, X8, [SP, #176]

0x436e14 ADD	X8, X15, #8

0x436e18 STP	X8, X10, [SP, #32]

0x436e1c ADD	X10, X16, #8

0x436e20 ADD	X8, X12, #8

0x436e24 STP	X8, X10, [SP, #16]

0x436e28 ADD	X10, X13, #16

0x436e2c ADD	X8, X16, #16

0x436e30 STP	X8, X10, [SP]

0x436e34 STUR	X0, [X29, #408]

0x436e38 STP	X2, X1, [X29, #896]

0x436e3c STP	X4, X3, [X29, #872]

0x436e40 STP	X6, X5, [X29, #856]

0x436e44 STUR	X7, [X29, #336]

0x436e48 B	436e60

    (762) 0x436e4c LDUR	X9, [X29, #456]

    (762) 0x436e50 LDUR	X8, [X29, #376]

    (762) 0x436e54 ADD	X9, X9, #1

    (762) 0x436e58 CMP	X9, X8

    (762) 0x436e5c B.GE	437578

    (762) 0x436e60 LDP	X8, X10, [X29, #928]

    (762) 0x436e64 STUR	X9, [X29, #456]

    (762) 0x436e68 LDR	X11, [X10, X9,LSL #3]

    (762) 0x436e6c LDR	X9, [X8, X11,LSL #3]

    (762) 0x436e70 ADD	X8, X11, #1

    (762) 0x436e74 LDR	X12, [X14, X11,LSL #3]

    (762) 0x436e78 LDR	X13, [X14, X8,LSL #3]

    (762) 0x436e7c ADD	X10, X13, X9

    (762) 0x436e80 SUB	X10, X10, X12

    (762) 0x436e84 CMP	X9, X10

    (762) 0x436e88 B.GE	436f28

    (762) 0x436e8c SUB	W16, W13, W12

    (762) 0x436e90 ADD	X15, X12, #1

    (762) 0x436e94 TBZ	W16, #0, 436ec0

    (762) 0x436e98 LDR	X16, [X28]

    (762) 0x436e9c LDR	X18, [SP, #176]

    (762) 0x436ea0 LDR	X16, [X0, X16,LSL #3]

    (762) 0x436ea4 STR	XZR, [X18, X12,LSL #3]

    (762) 0x436ea8 LDR	X18, [SP, #56]

    (762) 0x436eac LDR	X16, [X16, X9,LSL #3]

    (762) 0x436eb0 ADD	X9, X9, #1

    (762) 0x436eb4 STR	X12, [X21, X16,LSL #3]

    (762) 0x436eb8 STR	X16, [X18, X12,LSL #3]

    (762) 0x436ebc ORR	X12, XZR, X15

    (762) 0x436ec0 CMP	X13, X15

    (762) 0x436ec4 B.EQ	436f28

    (762) 0x436ec8 LDP	X15, X13, [SP, #32]

    (762) 0x436ecc ADD	X13, X13, X12,LSL #3

    (762) 0x436ed0 ADD	X16, X15, X12,LSL #3

    (762) 0x436ed4 HINT	#0

    (762) 0x436ed8 HINT	#0

    (762) 0x436edc HINT	#0

      (772) 0x436ee0 LDR	X15, [X28]

      (772) 0x436ee4 ADD	X18, X12, #1

      (772) 0x436ee8 LDR	X15, [X0, X15,LSL #3]

      (772) 0x436eec LDR	X15, [X15, X9,LSL #3]

      (772) 0x436ef0 STR	X12, [X21, X15,LSL #3]

      (772) 0x436ef4 STP	XZR, XZR, [X13, #1016]

      (772) 0x436ef8 STUR	X15, [X16, #504]

      (772) 0x436efc ADD	X13, X13, #16

      (772) 0x436f00 ADD	X12, X12, #2

      (772) 0x436f04 LDR	X15, [X28]

      (772) 0x436f08 LDR	X15, [X0, X15,LSL #3]

      (772) 0x436f0c ADD	X15, X15, X9,LSL #3

      (772) 0x436f10 ADD	X9, X9, #2

      (772) 0x436f14 LDR	X15, [X15, #8]

      (772) 0x436f18 STR	X18, [X21, X15,LSL #3]

      (772) 0x436f1c STR	X15, [X16], #16

      (772) 0x436f20 CMP	X10, X9

      (772) 0x436f24 B.NE	436ee0

    (762) 0x436f28 LDUR	X9, [X29, #400]

    (762) 0x436f2c LDR	X13, [X17, X8,LSL #3]

    (762) 0x436f30 LDR	X12, [X17, X11,LSL #3]

    (762) 0x436f34 LDR	X9, [X9, X11,LSL #3]

    (762) 0x436f38 ADD	X10, X13, X9

    (762) 0x436f3c SUB	X10, X10, X12

    (762) 0x436f40 CMP	X9, X10

    (762) 0x436f44 B.GE	436fe8

    (762) 0x436f48 SUB	W16, W13, W12

    (762) 0x436f4c ADD	X15, X12, #1

    (762) 0x436f50 TBZ	W16, #0, 436f7c

    (762) 0x436f54 LDR	X16, [X28]

    (762) 0x436f58 LDR	X18, [SP, #168]

    (762) 0x436f5c LDR	X16, [X1, X16,LSL #3]

    (762) 0x436f60 STR	XZR, [X18, X12,LSL #3]

    (762) 0x436f64 LDR	X18, [SP, #48]

    (762) 0x436f68 LDR	X16, [X16, X9,LSL #3]

    (762) 0x436f6c ADD	X9, X9, #1

    (762) 0x436f70 STR	X12, [X22, X16,LSL #3]

    (762) 0x436f74 STR	X16, [X18, X12,LSL #3]

    (762) 0x436f78 ORR	X12, XZR, X15

    (762) 0x436f7c CMP	X13, X15

    (762) 0x436f80 B.EQ	436fe8

    (762) 0x436f84 LDP	X15, X13, [SP, #16]

    (762) 0x436f88 ADD	X13, X13, X12,LSL #3

    (762) 0x436f8c ADD	X16, X15, X12,LSL #3

    (762) 0x436f90 HINT	#0

    (762) 0x436f94 HINT	#0

    (762) 0x436f98 HINT	#0

    (762) 0x436f9c HINT	#0

      (771) 0x436fa0 LDR	X15, [X28]

      (771) 0x436fa4 ADD	X18, X12, #1

      (771) 0x436fa8 LDR	X15, [X1, X15,LSL #3]

      (771) 0x436fac LDR	X15, [X15, X9,LSL #3]

      (771) 0x436fb0 STR	X12, [X22, X15,LSL #3]

      (771) 0x436fb4 STP	XZR, XZR, [X13, #1016]

      (771) 0x436fb8 STUR	X15, [X16, #504]

      (771) 0x436fbc ADD	X13, X13, #16

      (771) 0x436fc0 ADD	X12, X12, #2

      (771) 0x436fc4 LDR	X15, [X28]

      (771) 0x436fc8 LDR	X15, [X1, X15,LSL #3]

      (771) 0x436fcc ADD	X15, X15, X9,LSL #3

      (771) 0x436fd0 ADD	X9, X9, #2

      (771) 0x436fd4 LDR	X15, [X15, #8]

      (771) 0x436fd8 STR	X18, [X22, X15,LSL #3]

      (771) 0x436fdc STR	X15, [X16], #16

      (771) 0x436fe0 CMP	X10, X9

      (771) 0x436fe4 B.NE	436fa0

    (762) 0x436fe8 LDR	X9, [X2, X11,LSL #3]

    (762) 0x436fec LDR	X10, [X2, X8,LSL #3]

    (762) 0x436ff0 LDUR	X16, [X29, #480]

    (762) 0x436ff4 CMP	X9, X10

    (762) 0x436ff8 B.LT	43704c

    (762) 0x436ffc LDR	X9, [X5, X11,LSL #3]

    (762) 0x437000 LDR	X10, [X5, X8,LSL #3]

    (762) 0x437004 B	43700c

      (769) 0x437008 ADD	X9, X9, #1

      (769) 0x43700c CMP	X9, X10

      (769) 0x437010 B.GE	437080

      (769) 0x437014 LDR	X12, [X6, X9,LSL #3]

      (769) 0x437018 LDR	X15, [X28]

      (769) 0x43701c LDR	X13, [X7, X12,LSL #3]

      (769) 0x437020 SUB	X15, X15, #1

      (769) 0x437024 CMP	X13, X15

      (769) 0x437028 B.NE	437008

      (769) 0x43702c STR	X11, [X16, X12,LSL #3]

      (769) 0x437030 LDR	X10, [X5, X8,LSL #3]

      (769) 0x437034 B	437008

0x437038 HINT	#0

0x43703c HINT	#0

      (770) 0x437040 ADD	X9, X9, #1

      (770) 0x437044 CMP	X9, X10

      (770) 0x437048 B.GE	436ffc

      (770) 0x43704c LDR	X12, [X3, X9,LSL #3]

      (770) 0x437050 LDR	X15, [X28]

      (770) 0x437054 LDR	X13, [X4, X12,LSL #3]

      (770) 0x437058 SUB	X15, X15, #1

      (770) 0x43705c CMP	X13, X15

      (770) 0x437060 B.NE	437040

      (770) 0x437064 STR	X11, [X19, X12,LSL #3]

      (770) 0x437068 LDR	X10, [X2, X8,LSL #3]

      (770) 0x43706c B	437040

0x437070 HINT	#0

0x437074 HINT	#0

0x437078 HINT	#0

0x43707c HINT	#0

    (762) 0x437080 LDUR	X9, [X29, #328]

    (762) 0x437084 MOVI	D2, #0

    (762) 0x437088 LDR	X10, [X9, X11,LSL #3]

    (762) 0x43708c LDR	X12, [X9, X8,LSL #3]

    (762) 0x437090 ADD	X13, X10, #1

    (762) 0x437094 STUR	X10, [X29, #448]

    (762) 0x437098 CMP	X13, X12

    (762) 0x43709c B.GE	4372e0

    (762) 0x4370a0 LDR	X9, [SP, #64]

    (762) 0x4370a4 MOVI	D1, #0

    (762) 0x4370a8 LDR	X16, [X9]

    (762) 0x4370ac LDP	X10, X9, [X29, #944]

    (762) 0x4370b0 LDR	X1, [X10]

    (762) 0x4370b4 LDR	X10, [SP, #160]

    (762) 0x4370b8 LDR	X9, [X9]

    (762) 0x4370bc LDR	X24, [X10]

    (762) 0x4370c0 LDR	X10, [SP, #144]

    (762) 0x4370c4 LDR	X4, [X10]

    (762) 0x4370c8 LDUR	X10, [X29, #464]

    (762) 0x4370cc LDR	X23, [X10]

    (762) 0x4370d0 LDR	X10, [SP, #152]

    (762) 0x4370d4 ADD	X6, X4, #8

    (762) 0x4370d8 LDR	X27, [X10]

    (762) 0x4370dc LDUR	X10, [X29, #472]

    (762) 0x4370e0 ADD	X7, X23, #8

    (762) 0x4370e4 LDR	X10, [X10]

    (762) 0x4370e8 ADD	X20, X27, #8

    (762) 0x4370ec ADD	X25, X10, #8

    (762) 0x4370f0 B	43710c

      (766) 0x4370f4 LDR	D3, [X24, X13,LSL #3]

      (766) 0x4370f8 FADD	D1, D1, D3

      (766) 0x4370fc HINT	#0

      (766) 0x437100 ADD	X13, X13, #1

      (766) 0x437104 CMP	X13, X12

      (766) 0x437108 B.EQ	4372e4

      (766) 0x43710c LDUR	X15, [X29, #496]

      (766) 0x437110 LDR	X2, [X15, X13,LSL #3]

      (766) 0x437114 LDR	X15, [X19, X2,LSL #3]

      (766) 0x437118 CMP	X15, X11

      (766) 0x43711c B.NE	43714c

      (766) 0x437120 ADD	X0, X2, #1

      (766) 0x437124 LDR	X26, [X14, X2,LSL #3]

      (766) 0x437128 LDR	X3, [X14, X0,LSL #3]

      (766) 0x43712c CMP	X3, X26

      (766) 0x437130 B.LE	437218

      (766) 0x437134 SUB	W18, W3, W26

      (766) 0x437138 ADD	X15, X26, #1

      (766) 0x43713c TBNZ	W18, #0, 437174

      (766) 0x437140 CMP	X3, X15

      (766) 0x437144 B.NE	4371a8

      (766) 0x437148 B	437218

      (766) 0x43714c LDR	X15, [X16, X2,LSL #3]

      (766) 0x437150 CMN	X15, #3

      (766) 0x437154 B.EQ	437100

      (766) 0x437158 CMP	X1, #1

      (766) 0x43715c B.EQ	4370f4

      (766) 0x437160 LDR	X15, [X9, X11,LSL #3]

      (766) 0x437164 LDR	X18, [X9, X2,LSL #3]

      (766) 0x437168 CMP	X15, X18

      (766) 0x43716c B.EQ	4370f4

      (766) 0x437170 B	437100

      (766) 0x437174 LDR	X18, [X4, X26,LSL #3]

      (766) 0x437178 LDR	D0, [X24, X13,LSL #3]

      (766) 0x43717c LDR	D3, [X23, X26,LSL #3]

      (766) 0x437180 ORR	X26, XZR, X15

      (766) 0x437184 FMUL	D0, D0, D3

      (766) 0x437188 LDR	X18, [X21, X18,LSL #3]

      (766) 0x43718c LDR	D3, [X23, X18,LSL #3]

      (766) 0x437190 FADD	D2, D2, D0

      (766) 0x437194 FADD	D1, D1, D0

      (766) 0x437198 FADD	D3, D0, D3

      (766) 0x43719c STR	D3, [X23, X18,LSL #3]

      (766) 0x4371a0 CMP	X3, X15

      (766) 0x4371a4 B.EQ	437218

      (766) 0x4371a8 SUB	X3, X3, X26

      (766) 0x4371ac ADD	X5, X6, X26,LSL #3

      (766) 0x4371b0 ADD	X26, X7, X26,LSL #3

      (766) 0x4371b4 HINT	#0

      (766) 0x4371b8 HINT	#0

      (766) 0x4371bc HINT	#0

        (768) 0x4371c0 LDP	X15, X18, [X5, #1016]

        (768) 0x4371c4 LDR	D0, [X24, X13,LSL #3]

        (768) 0x4371c8 LDUR	D3, [X26, #504]

        (768) 0x4371cc SUBS	X3, X3, #2

        (768) 0x4371d0 ADD	X5, X5, #16

        (768) 0x4371d4 FMUL	D0, D0, D3

        (768) 0x4371d8 LDR	X15, [X21, X15,LSL #3]

        (768) 0x4371dc LDR	D3, [X23, X15,LSL #3]

        (768) 0x4371e0 FADD	D2, D2, D0

        (768) 0x4371e4 FADD	D1, D1, D0

        (768) 0x4371e8 FADD	D3, D0, D3

        (768) 0x4371ec STR	D3, [X23, X15,LSL #3]

        (768) 0x4371f0 LDR	X15, [X21, X18,LSL #3]

        (768) 0x4371f4 LDR	D0, [X24, X13,LSL #3]

        (768) 0x4371f8 LDR	D3, [X26], #16

        (768) 0x4371fc FMUL	D0, D0, D3

        (768) 0x437200 LDR	D3, [X23, X15,LSL #3]

        (768) 0x437204 FADD	D2, D2, D0

        (768) 0x437208 FADD	D1, D1, D0

        (768) 0x43720c FADD	D3, D0, D3

        (768) 0x437210 STR	D3, [X23, X15,LSL #3]

        (768) 0x437214 B.NE	4371c0

      (766) 0x437218 LDR	X3, [X17, X2,LSL #3]

      (766) 0x43721c LDR	X0, [X17, X0,LSL #3]

      (766) 0x437220 CMP	X0, X3

      (766) 0x437224 B.LE	437100

      (766) 0x437228 SUB	W18, W0, W3

      (766) 0x43722c ADD	X15, X3, #1

      (766) 0x437230 TBNZ	W18, #0, 437240

      (766) 0x437234 CMP	X0, X15

      (766) 0x437238 B.EQ	437100

      (766) 0x43723c B	437274

      (766) 0x437240 LDR	X18, [X27, X3,LSL #3]

      (766) 0x437244 LDR	D0, [X24, X13,LSL #3]

      (766) 0x437248 LDR	D3, [X10, X3,LSL #3]

      (766) 0x43724c ORR	X3, XZR, X15

      (766) 0x437250 FMUL	D0, D0, D3

      (766) 0x437254 LDR	X18, [X22, X18,LSL #3]

      (766) 0x437258 LDR	D3, [X10, X18,LSL #3]

      (766) 0x43725c FADD	D2, D2, D0

      (766) 0x437260 FADD	D1, D1, D0

      (766) 0x437264 FADD	D3, D0, D3

      (766) 0x437268 STR	D3, [X10, X18,LSL #3]

      (766) 0x43726c CMP	X0, X15

      (766) 0x437270 B.EQ	437100

      (766) 0x437274 SUB	X0, X0, X3

      (766) 0x437278 ADD	X2, X20, X3,LSL #3

      (766) 0x43727c ADD	X3, X25, X3,LSL #3

        (767) 0x437280 LDP	X15, X18, [X2, #1016]

        (767) 0x437284 LDR	D0, [X24, X13,LSL #3]

        (767) 0x437288 LDUR	D3, [X3, #504]

        (767) 0x43728c SUBS	X0, X0, #2

        (767) 0x437290 ADD	X2, X2, #16

        (767) 0x437294 FMUL	D0, D0, D3

        (767) 0x437298 LDR	X15, [X22, X15,LSL #3]

        (767) 0x43729c LDR	D3, [X10, X15,LSL #3]

        (767) 0x4372a0 FADD	D2, D2, D0

        (767) 0x4372a4 FADD	D1, D1, D0

        (767) 0x4372a8 FADD	D3, D0, D3

        (767) 0x4372ac STR	D3, [X10, X15,LSL #3]

        (767) 0x4372b0 LDR	X15, [X22, X18,LSL #3]

        (767) 0x4372b4 LDR	D0, [X24, X13,LSL #3]

        (767) 0x4372b8 LDR	D3, [X3], #16

        (767) 0x4372bc FMUL	D0, D0, D3

        (767) 0x4372c0 LDR	D3, [X10, X15,LSL #3]

        (767) 0x4372c4 FADD	D2, D2, D0

        (767) 0x4372c8 FADD	D1, D1, D0

        (767) 0x4372cc FADD	D3, D0, D3

        (767) 0x4372d0 STR	D3, [X10, X15,LSL #3]

        (767) 0x4372d4 B.NE	437280

      (766) 0x4372d8 B	437100

0x4372dc HINT	#0

    (762) 0x4372e0 MOVI	D1, #0

    (762) 0x4372e4 LDR	X10, [SP, #192]

    (762) 0x4372e8 LDR	X9, [X10, X11,LSL #3]

    (762) 0x4372ec LDR	X10, [X10, X8,LSL #3]

    (762) 0x4372f0 CMP	X9, X10

    (762) 0x4372f4 B.GE	437448

  (764) 0x4372f8 LDR	X15, [SP, #128]

  (764) 0x4372fc LDP	X12, X13, [SP, #72]

  (764) 0x437300 LDR	X5, [X28]

  (764) 0x437304 LDR	X16, [X15]

  (764) 0x437308 LDUR	X15, [X29, #432]

  (764) 0x43730c LDR	X12, [X12]

  (764) 0x437310 LDR	X13, [X13]

  (764) 0x437314 LDR	X1, [X15]

  (764) 0x437318 LDR	X15, [SP, #136]

  (764) 0x43731c LDR	X23, [X15]

  (764) 0x437320 LDUR	X15, [X29, #440]

  (764) 0x437324 LDR	X24, [X15]

  (764) 0x437328 LDR	X15, [SP, #112]

  (764) 0x43732c LDR	X2, [X15]

  (764) 0x437330 LDR	X15, [SP, #88]

  (764) 0x437334 LDR	X26, [X15]

  (764) 0x437338 LDR	X15, [SP, #96]

  (764) 0x43733c LDR	X15, [X15]

  (764) 0x437340 ADD	X27, X15, #8

  (764) 0x437344 LDR	X15, [SP, #104]

  (764) 0x437348 LDR	X0, [X15]

  (764) 0x43734c LDR	X15, [SP, #120]

  (764) 0x437350 LDR	X3, [X15]

  (764) 0x437354 B	437374

0x437358 HINT	#0

0x43735c HINT	#0

(763) 0x437360 LDR	D3, [X2, X9,LSL #3]

(763) 0x437364 FADD	D1, D1, D3

  (764) 0x437368 ADD	X9, X9, #1

  (764) 0x43736c CMP	X9, X10

  (764) 0x437370 B.EQ	437448

  (764) 0x437374 LDUR	X18, [X29, #488]

  (764) 0x437378 ADD	X15, X13, X9,LSL #3

  (764) 0x43737c CBZ	X18, 437388

  (764) 0x437380 LDR	X15, [X15]

  (764) 0x437384 ADD	X15, X12, X15,LSL #3

  (764) 0x437388 LDR	X15, [X15]

  (764) 0x43738c TBNZ	X15, #63, 437420

  (764) 0x437390 LDUR	X18, [X29, #480]

  (764) 0x437394 LDR	X18, [X18, X15,LSL #3]

  (764) 0x437398 CMP	X18, X11

  (764) 0x43739c B.NE	437420

  (764) 0x4373a0 LDR	X18, [X27, X15,LSL #3]

  (764) 0x4373a4 CMP	X18, #1

  (764) 0x4373a8 B.LT	437368

  (764) 0x4373ac LDR	X4, [X26, X15,LSL #3]

  (764) 0x4373b0 LDR	X6, [X0, X5,LSL #3]

  (764) 0x4373b4 ADD	X15, X18, X4

  (764) 0x4373b8 LDUR	X18, [X29, #472]

  (764) 0x4373bc LDR	X7, [X18]

  (764) 0x4373c0 LDUR	X18, [X29, #464]

  (764) 0x4373c4 LDR	X18, [X18]

    (765) 0x4373c8 LDR	X25, [X6, X4,LSL #3]

    (765) 0x4373cc LDR	D0, [X2, X9,LSL #3]

    (765) 0x4373d0 LDR	D3, [X3, X4,LSL #3]

    (765) 0x4373d4 ADD	X4, X4, #1

    (765) 0x4373d8 ORN	X20, XZR, X25

    (765) 0x4373dc ADD	X30, X22, X25,LSL #3

    (765) 0x4373e0 CMP	X25, #0

    (765) 0x4373e4 ADD	X20, X21, X20,LSL #3

    (765) 0x4373e8 CSEL	X25, X18, X7, #11

    (765) 0x4373ec CSEL	X20, X20, X30, #11

    (765) 0x4373f0 FMUL	D0, D0, D3

    (765) 0x4373f4 LDR	X20, [X20]

    (765) 0x4373f8 FADD	D2, D2, D0

    (765) 0x4373fc FADD	D1, D1, D0

    (765) 0x437400 LDR	D3, [X25, X20,LSL #3]

    (765) 0x437404 FADD	D3, D0, D3

    (765) 0x437408 STR	D3, [X25, X20,LSL #3]

    (765) 0x43740c CMP	X4, X15

    (765) 0x437410 B.LT	4373c8

  (764) 0x437414 B	437368

0x437418 HINT	#0

0x43741c HINT	#0

(763) 0x437420 LDR	X18, [X16, X15,LSL #3]

(763) 0x437424 CMN	X18, #3

(763) 0x437428 B.EQ	437368

(763) 0x43742c CMP	X1, #1

(763) 0x437430 B.EQ	437360

(763) 0x437434 LDR	X15, [X23, X15,LSL #3]

(763) 0x437438 LDR	X18, [X24, X11,LSL #3]

(763) 0x43743c CMP	X15, X18

(763) 0x437440 B.EQ	437360

(763) 0x437444 B	437368

    (762) 0x437448 LDR	X9, [SP, #184]

    (762) 0x43744c LDUR	X10, [X29, #448]

    (762) 0x437450 LDR	D3, [X9, X10,LSL #3]

    (762) 0x437454 FMUL	D2, D2, D3

    (762) 0x437458 FCMP	D2, #0

    (762) 0x43745c B.EQ	437468

    (762) 0x437460 FNEG	D0, D1

    (762) 0x437464 FDIV	D0, D0, D2

    (762) 0x437468 LDR	X15, [X14, X11,LSL #3]

    (762) 0x43746c LDR	X9, [X14, X8,LSL #3]

    (762) 0x437470 LDUR	X0, [X29, #408]

    (762) 0x437474 SUBS	X10, X9, X15

    (762) 0x437478 LDP	X2, X1, [X29, #896]

    (762) 0x43747c LDP	X4, X3, [X29, #872]

    (762) 0x437480 LDP	X6, X5, [X29, #856]

    (762) 0x437484 LDUR	X7, [X29, #336]

    (762) 0x437488 B.LE	4374f4

    (762) 0x43748c ORR	X12, XZR, X15

    (762) 0x437490 CMP	X10, #4

    (762) 0x437494 B.CC	4374d0

    (762) 0x437498 LDR	X16, [SP, #8]

    (762) 0x43749c AND	X13, X10, #8062

    (762) 0x4374a0 ADD	X12, X15, X13

    (762) 0x4374a4 ADD	X15, X16, X15,LSL #3

    (762) 0x4374a8 ORR	X16, XZR, X13

      (776) 0x4374ac LDP	Q1, Q2, [X15, #2032]

      (776) 0x4374b0 SUBS	X16, X16, #4

      (776) 0x4374b4 FMUL	V2.2D, V2.2D, V0.D[0]

      (776) 0x4374b8 FMUL	V1.2D, V1.2D, V0.D[0]

      (776) 0x4374bc STP	Q1, Q2, [X15, #2032]

      (776) 0x4374c0 ADD	X15, X15, #32

      (776) 0x4374c4 B.NE	4374ac

    (762) 0x4374c8 CMP	X10, X13

    (762) 0x4374cc B.EQ	4374f4

    (762) 0x4374d0 LDR	X10, [SP, #176]

    (762) 0x4374d4 SUB	X9, X9, X12

    (762) 0x4374d8 ADD	X10, X10, X12,LSL #3

    (762) 0x4374dc HINT	#0

      (775) 0x4374e0 LDR	D1, [X10]

      (775) 0x4374e4 SUBS	X9, X9, #1

      (775) 0x4374e8 FMUL	D1, D0, D1

      (775) 0x4374ec STR	D1, [X10], #8

      (775) 0x4374f0 B.NE	4374e0

    (762) 0x4374f4 LDR	X12, [X17, X11,LSL #3]

    (762) 0x4374f8 LDR	X8, [X17, X8,LSL #3]

    (762) 0x4374fc SUBS	X9, X8, X12

    (762) 0x437500 B.LE	436e4c

    (762) 0x437504 ORR	X10, XZR, X12

    (762) 0x437508 CMP	X9, #4

    (762) 0x43750c B.CC	437548

    (762) 0x437510 LDR	X13, [SP]

    (762) 0x437514 AND	X11, X9, #8062

    (762) 0x437518 ADD	X10, X12, X11

    (762) 0x43751c ADD	X12, X13, X12,LSL #3

    (762) 0x437520 ORR	X13, XZR, X11

      (774) 0x437524 LDP	Q1, Q2, [X12, #2032]

      (774) 0x437528 SUBS	X13, X13, #4

      (774) 0x43752c FMUL	V2.2D, V2.2D, V0.D[0]

      (774) 0x437530 FMUL	V1.2D, V1.2D, V0.D[0]

      (774) 0x437534 STP	Q1, Q2, [X12, #2032]

      (774) 0x437538 ADD	X12, X12, #32

      (774) 0x43753c B.NE	437524

    (762) 0x437540 CMP	X9, X11

    (762) 0x437544 B.EQ	436e4c

    (762) 0x437548 LDR	X9, [SP, #168]

    (762) 0x43754c SUB	X8, X8, X10

    (762) 0x437550 ADD	X9, X9, X10,LSL #3

    (762) 0x437554 HINT	#0

    (762) 0x437558 HINT	#0

    (762) 0x43755c HINT	#0

      (773) 0x437560 LDR	D1, [X9]

      (773) 0x437564 SUBS	X8, X8, #1

      (773) 0x437568 FMUL	D1, D0, D1

      (773) 0x43756c STR	D1, [X9], #8

      (773) 0x437570 B.NE	437560

    (762) 0x437574 B	436e4c

0x437578 ORR	X0, XZR, X19

0x43757c BL	4a91d0

0x437580 LDUR	X0, [X29, #480]

0x437584 BL	4a91d0

0x437588 ORR	X0, XZR, X21

0x43758c BL	4a91d0

0x437590 ORR	X0, XZR, X22

0x437594 LDP	X20, X19, [SP, #464]

0x437598 LDP	X22, X21, [SP, #448]

0x43759c LDP	X24, X23, [SP, #432]

0x4375a0 LDP	X26, X25, [SP, #416]

0x4375a4 LDP	X28, X27, [SP, #400]

0x4375a8 LDP	X29, X30, [SP, #384]

0x4375ac ADD	SP, SP, #480

0x4375b0 B	4a91d0

0x4375b4 HINT	#0

0x4375b8 HINT	#0

0x4375bc HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 59% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 46.17 to 37.42 cycles (1.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 46.17 to 4.50 cycles (10.26x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 840 bytes. The binary function is storing 584 bytes.

General properties

nb instructions	218
loop length	872
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.00	10.00	8.83	8.83	8.83	8.83	8.83	8.83	0.00	0.00	0.00	0.00	46.17	45.83	46.00	26.50	26.50
cycles	10.00	10.00	8.83	8.83	8.83	8.83	8.83	8.83	0.00	0.00	0.00	0.00	46.17	45.83	46.00	26.50	26.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.25
Overall L1	46.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.17 cycles. At this rate:

18% of peak load performance is reached (18.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 436b30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X20, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X10, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X10, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X11, X9, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X10, X8, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X23, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CBZ X0, 436c74 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 436c58 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 436c84 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 436c88 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X0, 436c50 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 436c58 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X0, X8, X9, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 436cd4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 436d00 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X11, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X24, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X9, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X8, X10, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X9, X9, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 437578 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X8, X10, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X8, X10, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X10, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X16, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X13, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X16, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X1, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X3, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X5, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X7, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 436e60 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a91d0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a91d0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a91d0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a91d0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 46.17 to 4.50 cycles (10.26x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 840 bytes. The binary function is storing 584 bytes.

General properties

nb instructions	218
loop length	872
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	10.00	10.00	8.83	8.83	8.83	8.83	8.83	8.83	0.00	0.00	0.00	0.00	46.17	45.83	46.00	26.50	26.50
cycles	10.00	10.00	8.83	8.83	8.83	8.83	8.83	8.83	0.00	0.00	0.00	0.00	46.17	45.83	46.00	26.50	26.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.25
Overall L1	46.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.17 cycles. At this rate:

18% of peak load performance is reached (18.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.65 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 436b30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X7, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X24, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X20, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X9, X10, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X10, X9, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X11, X9, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X8, X9, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X10, X9, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X10, X8, [X29, #904]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X10, X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X23, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X8, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CBZ X0, 436c74 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 436c58 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STUR X0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 436c84 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 436c88 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X0, 436c50 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 436c58 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
CSEL X0, X8, X9, #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 436cd4 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 436d00 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SUB X11, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X24, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X9, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X8, X10, X24, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X9, X9, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 437578 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0xa48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X12, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X12, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X23]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X11, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X11, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X9, X8, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X8, X10, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X3, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X8, X10, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X10, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X1, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X11, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X13, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X20]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X15, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X16, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X13, X8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X8, X15, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X12, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X10, X13, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X16, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X1, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X4, X3, [X29, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X6, X5, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X7, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 436e60 <hypre_BoomerAMGBuildMultipass.omp_outlined.20+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a91d0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X0, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 4a91d0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a91d0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X20, X19, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a91d0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.20–	1.43	0.26
○Loop 778 - par_multi_interp.c:1760-1761 - exec	0.37	0.06
○Loop 777 - par_multi_interp.c:1762-1763 - exec	0.00	0.00
▼Loop 763 - par_multi_interp.c:1774-1876 - exec–	0.00	0.00
▼Loop 764 - par_multi_interp.c:1774-1876 - exec–	0.00	0.00
▼Loop 762 - par_multi_interp.c:1774-1876 - exec–	0.19	0.03
▼Loop 766 - par_multi_interp.c:1811-1837 - exec–	0.58	0.09
○Loop 768 - par_multi_interp.c:1816-1822 - exec	0.03	0.01
○Loop 767 - par_multi_interp.c:1824-1830 - exec	0.00	0.00
○Loop 770 - par_multi_interp.c:1799-1803 - exec	0.25	0.04
○Loop 772 - par_multi_interp.c:1782-1787 - exec	0.01	0.00
○Loop 775 - par_multi_interp.c:1873-1874 - exec	0.00	0.00
○Loop 769 - par_multi_interp.c:1805-1809 - exec	0.00	0.00
○Loop 773 - par_multi_interp.c:1875-1876 - exec	0.00	0.00
○Loop 776 - par_multi_interp.c:1874-1874 - exec	0.00	0.00
○Loop 771 - par_multi_interp.c:1792-1797 - exec	0.00	0.00
○Loop 774 - par_multi_interp.c:1876-1876 - exec	0.00	0.00
○Loop 765 - par_multi_interp.c:1851-1860 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code