OV - exec - Function hypre_BoomerAMGBuildMultipass.omp

	Function: hypre_BoomerAMGBuildMultipass.omp_outlined.18	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage (incl. loops): 0.44% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x436410 SUB	SP, SP, #304

0x436414 STP	X29, X30, [SP, #208]

0x436418 STP	X28, X27, [SP, #224]

0x43641c STP	X26, X25, [SP, #240]

0x436420 STP	X24, X23, [SP, #256]

0x436424 STP	X22, X21, [SP, #272]

0x436428 STP	X20, X19, [SP, #288]

0x43642c ADD	X29, SP, #208

0x436430 LDP	X8, X9, [X29, #288]

0x436434 STP	X7, X6, [X29, #992]

0x436438 STUR	X4, [X29, #472]

0x43643c LDR	X0, [X2]

0x436440 ORR	X24, XZR, X5

0x436444 ORR	X25, XZR, X3

0x436448 ORR	X26, XZR, X2

0x43644c STUR	X9, [X29, #416]

0x436450 STR	X8, [SP, #104]

0x436454 LDP	X8, X9, [X29, #272]

0x436458 STUR	X9, [X29, #440]

0x43645c STR	X8, [SP, #96]

0x436460 LDR	X8, [X29, #264]

0x436464 STR	X8, [SP, #88]

0x436468 LDP	X8, X21, [X29, #248]

0x43646c STR	X8, [SP, #80]

0x436470 LDR	X8, [X29, #240]

0x436474 STR	X8, [SP, #72]

0x436478 LDP	X8, X28, [X29, #208]

0x43647c LDP	X27, X22, [X29, #224]

0x436480 STUR	X8, [X29, #448]

0x436484 LDR	X8, [X29, #200]

0x436488 STR	X8, [SP, #40]

0x43648c LDP	X8, X9, [X29, #184]

0x436490 STUR	X9, [X29, #456]

0x436494 STR	X8, [SP, #64]

0x436498 LDR	X8, [X29, #176]

0x43649c STR	X8, [SP, #56]

0x4364a0 LDP	X8, X9, [X29, #160]

0x4364a4 STP	X8, X9, [X29, #936]

0x4364a8 LDP	X23, X8, [X29, #144]

0x4364ac STUR	X8, [X29, #496]

0x4364b0 LDR	X8, [X29, #136]

0x4364b4 STR	X8, [SP, #32]

0x4364b8 LDR	X8, [X29, #128]

0x4364bc STR	X8, [SP, #24]

0x4364c0 LDR	X8, [X29, #120]

0x4364c4 STR	X8, [SP, #16]

0x4364c8 LDR	X8, [X29, #112]

0x4364cc STR	X8, [SP, #8]

0x4364d0 LDP	X8, X9, [X29, #96]

0x4364d4 STUR	X9, [X29, #464]

0x4364d8 STR	X8, [SP, #48]

0x4364dc CBZ	X0, 436510

0x4364e0 MOVZ	W1, #8

0x4364e4 BL	4a90d0

0x4364e8 ORR	X19, XZR, X0

0x4364ec LDR	X0, [X25]

0x4364f0 CBZ	X0, 43651c

0x4364f4 MOVZ	W1, #8

0x4364f8 BL	4a90d0

0x4364fc ORR	X20, XZR, X0

0x436500 LDR	X8, [X26]

0x436504 CMP	X8, #1

0x436508 B.GE	43652c

0x43650c B	436554

0x436510 ORR	X19, XZR, XZR

0x436514 LDR	X0, [X25]

0x436518 CBNZ	X0, 4364f4

0x43651c ORR	X20, XZR, XZR

0x436520 LDR	X8, [X26]

0x436524 CMP	X8, #1

0x436528 B.LT	436554

0x43652c MOVN	X9, #0

0x436530 ORR	X8, XZR, XZR

0x436534 HINT	#0

0x436538 HINT	#0

0x43653c HINT	#0

(760) 0x436540 STR	X9, [X19, X8,LSL #3]

(760) 0x436544 ADD	X8, X8, #1

(760) 0x436548 LDR	X10, [X26]

(760) 0x43654c CMP	X8, X10

(760) 0x436550 B.LT	436540

0x436554 LDR	X8, [X25]

0x436558 CMP	X8, #1

0x43655c B.LT	43657c

0x436560 MOVN	X9, #0

0x436564 ORR	X8, XZR, XZR

(761) 0x436568 STR	X9, [X20, X8,LSL #3]

(761) 0x43656c ADD	X8, X8, #1

(761) 0x436570 LDR	X10, [X25]

(761) 0x436574 CMP	X8, X10

(761) 0x436578 B.LT	436568

0x43657c BL	4aae50

0x436580 ORR	X25, XZR, X0

0x436584 BL	4aae30

0x436588 LDR	X9, [X24]

0x43658c SUB	X11, X0, #1

0x436590 CMP	X25, X11

0x436594 SDIV	X10, X9, X0

0x436598 MADD	X8, X10, X25, XZR

0x43659c ADD	X10, X10, X8

0x4365a0 CSEL	X9, X9, X10, #0

0x4365a4 CMP	X8, X9

0x4365a8 B.GE	436af8

0x4365ac LDP	X12, X10, [X29, #976]

0x4365b0 LDR	X2, [X28]

0x4365b4 LDR	X3, [X27]

0x4365b8 LDR	X4, [X22]

0x4365bc LDR	X5, [X21]

0x4365c0 LDR	X11, [X10]

0x4365c4 LDUR	X10, [X29, #488]

0x4365c8 LDR	X12, [X12]

0x4365cc LDR	X10, [X10]

0x4365d0 LDR	X11, [X11, #8]

0x4365d4 STUR	X10, [X29, #488]

0x4365d8 LDUR	X10, [X29, #480]

0x4365dc ADD	X9, X9, X11

0x4365e0 ADD	X13, X8, X11

0x4365e4 LDR	X10, [X10]

0x4365e8 STUR	X10, [X29, #480]

0x4365ec LDR	X10, [SP, #48]

0x4365f0 STR	X12, [SP, #48]

0x4365f4 STUR	X9, [X29, #464]

0x4365f8 LDP	X9, X8, [SP, #8]

0x4365fc LDR	X10, [X10]

0x436600 LDR	X14, [X9]

0x436604 LDR	X15, [X8]

0x436608 LDP	X9, X8, [SP, #24]

0x43660c LDR	X17, [X8]

0x436610 LDUR	X8, [X29, #456]

0x436614 LDR	X16, [X9]

0x436618 LDR	X8, [X8]

0x43661c STUR	X8, [X29, #456]

0x436620 LDR	X8, [SP, #40]

0x436624 LDR	X0, [X8]

0x436628 LDUR	X8, [X29, #448]

0x43662c LDR	X8, [X8]

0x436630 STR	X8, [SP, #40]

0x436634 LDUR	X8, [X29, #424]

0x436638 LDR	X8, [X8]

0x43663c STUR	X8, [X29, #448]

0x436640 LDP	X11, X8, [X29, #944]

0x436644 LDR	X9, [X11]

0x436648 LDR	X8, [X8]

0x43664c STP	X8, X9, [SP, #24]

0x436650 ADD	X9, X9, #16

0x436654 ADD	X8, X8, #16

0x436658 STP	X8, X9, [SP, #8]

0x43665c STUR	X10, [X29, #472]

0x436660 B	436674

  (749) 0x436664 LDUR	X8, [X29, #464]

  (749) 0x436668 ADD	X13, X13, #1

  (749) 0x43666c CMP	X13, X8

  (749) 0x436670 B.GE	436af8

  (749) 0x436674 LDP	X8, X9, [X29, #992]

  (749) 0x436678 LDR	X30, [X9, X13,LSL #3]

  (749) 0x43667c ADD	X26, X30, #1

  (749) 0x436680 LDR	X8, [X8, X30,LSL #3]

  (749) 0x436684 LDR	X25, [X10, X30,LSL #3]

  (749) 0x436688 LDR	X9, [X10, X26,LSL #3]

  (749) 0x43668c ADD	X11, X9, X8

  (749) 0x436690 SUB	X11, X11, X25

  (749) 0x436694 CMP	X8, X11

  (749) 0x436698 B.GE	43674c

  (749) 0x43669c LDR	X11, [SP, #48]

  (749) 0x4366a0 SUB	W12, W9, W25

  (749) 0x4366a4 ANDS	X18, X12, #4160

  (749) 0x4366a8 LDR	X11, [X11, #8]

  (749) 0x4366ac B.EQ	4366e8

  (749) 0x4366b0 ORR	X12, XZR, X8

  (749) 0x4366b4 HINT	#0

  (749) 0x4366b8 HINT	#0

  (749) 0x4366bc HINT	#0

    (755) 0x4366c0 LDR	X1, [X11, X12,LSL #3]

    (755) 0x4366c4 ADD	X12, X12, #1

    (755) 0x4366c8 SUBS	X18, X18, #1

    (755) 0x4366cc LDR	X1, [X14, X1,LSL #3]

    (755) 0x4366d0 STR	X30, [X19, X1,LSL #3]

    (755) 0x4366d4 B.NE	4366c0

  (749) 0x4366d8 SUB	X18, X25, X9

  (749) 0x4366dc CMN	X18, #4

  (749) 0x4366e0 B.LS	4366f8

  (749) 0x4366e4 B	436748

  (749) 0x4366e8 ORR	X12, XZR, X8

  (749) 0x4366ec SUB	X18, X25, X9

  (749) 0x4366f0 CMN	X18, #4

  (749) 0x4366f4 B.HI	436748

  (749) 0x4366f8 ADD	X8, X9, X8

  (749) 0x4366fc ADD	X11, X11, X12,LSL #3

  (749) 0x436700 SUB	X8, X8, X12

  (749) 0x436704 ADD	X9, X11, #16

  (749) 0x436708 SUB	X8, X8, X25

    (754) 0x43670c LDUR	X11, [X9, #496]

    (754) 0x436710 SUBS	X8, X8, #4

    (754) 0x436714 LDR	X11, [X14, X11,LSL #3]

    (754) 0x436718 STR	X30, [X19, X11,LSL #3]

    (754) 0x43671c LDUR	X11, [X9, #504]

    (754) 0x436720 LDR	X11, [X14, X11,LSL #3]

    (754) 0x436724 STR	X30, [X19, X11,LSL #3]

    (754) 0x436728 LDR	X11, [X9]

    (754) 0x43672c LDR	X11, [X14, X11,LSL #3]

    (754) 0x436730 STR	X30, [X19, X11,LSL #3]

    (754) 0x436734 LDR	X11, [X9, #8]

    (754) 0x436738 ADD	X9, X9, #32

    (754) 0x43673c LDR	X11, [X14, X11,LSL #3]

    (754) 0x436740 STR	X30, [X19, X11,LSL #3]

    (754) 0x436744 B.NE	43670c

  (749) 0x436748 LDR	X25, [X10, X30,LSL #3]

  (749) 0x43674c LDR	X8, [X15, X30,LSL #3]

  (749) 0x436750 LDR	X12, [X15, X26,LSL #3]

  (749) 0x436754 MOVI	D2, #0

  (749) 0x436758 ADD	X8, X8, #1

  (749) 0x43675c CMP	X8, X12

  (749) 0x436760 B.GE	436820

  (749) 0x436764 LDUR	X10, [X29, #424]

  (749) 0x436768 LDUR	X9, [X29, #496]

  (749) 0x43676c MOVI	D1, #0

  (749) 0x436770 LDR	X11, [X10]

  (749) 0x436774 LDUR	X10, [X29, #432]

  (749) 0x436778 LDR	X9, [X9]

  (749) 0x43677c LDR	X1, [X10]

  (749) 0x436780 LDR	X10, [SP, #64]

  (749) 0x436784 LDR	X7, [X10]

  (749) 0x436788 LDR	X10, [SP, #56]

  (749) 0x43678c LDR	X21, [X10]

  (749) 0x436790 B	4367ac

0x436794 HINT	#0

0x436798 HINT	#0

0x43679c HINT	#0

    (753) 0x4367a0 ADD	X8, X8, #1

    (753) 0x4367a4 CMP	X8, X12

    (753) 0x4367a8 B.GE	436824

    (753) 0x4367ac LDR	X22, [X16, X8,LSL #3]

    (753) 0x4367b0 LDR	X18, [X17, X22,LSL #3]

    (753) 0x4367b4 CMN	X18, #3

    (753) 0x4367b8 B.EQ	4367e0

    (753) 0x4367bc LDR	X18, [X23]

    (753) 0x4367c0 CMP	X18, #1

    (753) 0x4367c4 B.EQ	4367d8

    (753) 0x4367c8 LDR	X18, [X9, X30,LSL #3]

    (753) 0x4367cc LDR	X24, [X9, X22,LSL #3]

    (753) 0x4367d0 CMP	X18, X24

    (753) 0x4367d4 B.NE	4367e0

    (753) 0x4367d8 LDR	D3, [X11, X8,LSL #3]

    (753) 0x4367dc FADD	D1, D1, D3

    (753) 0x4367e0 CMN	X22, #1

    (753) 0x4367e4 B.EQ	4367a0

    (753) 0x4367e8 LDR	X18, [X19, X22,LSL #3]

    (753) 0x4367ec CMP	X18, X30

    (753) 0x4367f0 B.NE	4367a0

    (753) 0x4367f4 LDR	X12, [X7, X22,LSL #3]

    (753) 0x4367f8 LDR	D3, [X11, X8,LSL #3]

    (753) 0x4367fc STR	X12, [X21, X25,LSL #3]

    (753) 0x436800 LDR	X12, [X15, X26,LSL #3]

    (753) 0x436804 FADD	D2, D2, D3

    (753) 0x436808 STR	D3, [X1, X25,LSL #3]

    (753) 0x43680c ADD	X25, X25, #1

    (753) 0x436810 B	4367a0

0x436814 HINT	#0

0x436818 HINT	#0

0x43681c HINT	#0

  (749) 0x436820 MOVI	D1, #0

  (749) 0x436824 LDUR	X8, [X29, #456]

  (749) 0x436828 LDR	X9, [X0, X26,LSL #3]

  (749) 0x43682c LDR	X7, [X0, X30,LSL #3]

  (749) 0x436830 LDR	X8, [X8, X30,LSL #3]

  (749) 0x436834 ADD	X11, X9, X8

  (749) 0x436838 SUB	X11, X11, X7

  (749) 0x43683c CMP	X8, X11

  (749) 0x436840 B.GE	4368ec

  (749) 0x436844 LDR	X10, [SP, #40]

  (749) 0x436848 SUB	W12, W9, W7

  (749) 0x43684c ANDS	X18, X12, #4160

  (749) 0x436850 LDR	X11, [X10, #8]

  (749) 0x436854 B.EQ	436888

  (749) 0x436858 ORR	X12, XZR, X8

  (749) 0x43685c HINT	#0

    (752) 0x436860 LDR	X1, [X11, X12,LSL #3]

    (752) 0x436864 ADD	X12, X12, #1

    (752) 0x436868 SUBS	X18, X18, #1

    (752) 0x43686c LDR	X1, [X2, X1,LSL #3]

    (752) 0x436870 STR	X30, [X20, X1,LSL #3]

    (752) 0x436874 B.NE	436860

  (749) 0x436878 SUB	X18, X7, X9

  (749) 0x43687c CMN	X18, #4

  (749) 0x436880 B.LS	436898

  (749) 0x436884 B	4368e8

  (749) 0x436888 ORR	X12, XZR, X8

  (749) 0x43688c SUB	X18, X7, X9

  (749) 0x436890 CMN	X18, #4

  (749) 0x436894 B.HI	4368e8

  (749) 0x436898 ADD	X8, X9, X8

  (749) 0x43689c ADD	X11, X11, X12,LSL #3

  (749) 0x4368a0 SUB	X8, X8, X12

  (749) 0x4368a4 ADD	X9, X11, #16

  (749) 0x4368a8 SUB	X8, X8, X7

    (751) 0x4368ac LDUR	X11, [X9, #496]

    (751) 0x4368b0 SUBS	X8, X8, #4

    (751) 0x4368b4 LDR	X11, [X2, X11,LSL #3]

    (751) 0x4368b8 STR	X30, [X20, X11,LSL #3]

    (751) 0x4368bc LDUR	X11, [X9, #504]

    (751) 0x4368c0 LDR	X11, [X2, X11,LSL #3]

    (751) 0x4368c4 STR	X30, [X20, X11,LSL #3]

    (751) 0x4368c8 LDR	X11, [X9]

    (751) 0x4368cc LDR	X11, [X2, X11,LSL #3]

    (751) 0x4368d0 STR	X30, [X20, X11,LSL #3]

    (751) 0x4368d4 LDR	X11, [X9, #8]

    (751) 0x4368d8 ADD	X9, X9, #32

    (751) 0x4368dc LDR	X11, [X2, X11,LSL #3]

    (751) 0x4368e0 STR	X30, [X20, X11,LSL #3]

    (751) 0x4368e4 B.NE	4368ac

  (749) 0x4368e8 LDR	X7, [X0, X30,LSL #3]

  (749) 0x4368ec LDR	X24, [X3, X30,LSL #3]

  (749) 0x4368f0 LDR	X28, [X3, X26,LSL #3]

  (749) 0x4368f4 CMP	X24, X28

  (749) 0x4368f8 B.GE	4369c8

(750) 0x4368fc LDP	X9, X8, [SP, #72]

(750) 0x436900 LDR	X12, [X8]

(750) 0x436904 LDUR	X8, [X29, #496]

(750) 0x436908 LDR	X21, [X9]

(750) 0x43690c LDR	X27, [X8]

(750) 0x436910 LDP	X9, X8, [SP, #88]

(750) 0x436914 ADD	X12, X12, X24,LSL #3

(750) 0x436918 LDR	X1, [X8]

(750) 0x43691c LDUR	X8, [X29, #440]

(750) 0x436920 LDR	X11, [X9]

(750) 0x436924 LDR	X9, [SP, #104]

(750) 0x436928 LDR	X22, [X8]

(750) 0x43692c LDUR	X8, [X29, #416]

(750) 0x436930 LDR	X9, [X9]

(750) 0x436934 LDR	X8, [X8]

(750) 0x436938 B	436950

0x43693c HINT	#0

(750) 0x436940 ADD	X24, X24, #1

(750) 0x436944 ADD	X12, X12, #8

(750) 0x436948 CMP	X24, X28

(750) 0x43694c B.GE	4369c8

(750) 0x436950 ORR	X18, XZR, X12

(750) 0x436954 CBZ	X4, 436960

(750) 0x436958 LDR	X18, [X12]

(750) 0x43695c ADD	X18, X21, X18,LSL #3

(750) 0x436960 LDR	X18, [X18]

(750) 0x436964 LDR	X6, [X5, X18,LSL #3]

(750) 0x436968 CMN	X6, #3

(750) 0x43696c B.EQ	436994

(750) 0x436970 LDR	X6, [X23]

(750) 0x436974 CMP	X6, #1

(750) 0x436978 B.EQ	43698c

(750) 0x43697c LDR	X6, [X27, X30,LSL #3]

(750) 0x436980 LDR	X10, [X11, X18,LSL #3]

(750) 0x436984 CMP	X6, X10

(750) 0x436988 B.NE	436994

(750) 0x43698c LDR	D3, [X1, X24,LSL #3]

(750) 0x436990 FADD	D1, D1, D3

(750) 0x436994 CMN	X18, #1

(750) 0x436998 B.EQ	436940

(750) 0x43699c LDR	X10, [X20, X18,LSL #3]

(750) 0x4369a0 CMP	X10, X30

(750) 0x4369a4 B.NE	436940

(750) 0x4369a8 LDR	X10, [X8, X18,LSL #3]

(750) 0x4369ac LDR	D3, [X1, X24,LSL #3]

(750) 0x4369b0 STR	X10, [X9, X7,LSL #3]

(750) 0x4369b4 LDR	X28, [X3, X26,LSL #3]

(750) 0x4369b8 FADD	D2, D2, D3

(750) 0x4369bc STR	D3, [X22, X7,LSL #3]

(750) 0x4369c0 ADD	X7, X7, #1

(750) 0x4369c4 B	436940

  (749) 0x4369c8 LDR	X8, [X15, X30,LSL #3]

  (749) 0x4369cc LDUR	X9, [X29, #448]

  (749) 0x4369d0 LDR	D3, [X9, X8,LSL #3]

  (749) 0x4369d4 FMUL	D2, D2, D3

  (749) 0x4369d8 FCMP	D2, #0

  (749) 0x4369dc B.EQ	4369e8

  (749) 0x4369e0 FNEG	D0, D1

  (749) 0x4369e4 FDIV	D0, D0, D2

  (749) 0x4369e8 LDUR	X10, [X29, #472]

  (749) 0x4369ec LDR	X12, [X10, X30,LSL #3]

  (749) 0x4369f0 SUBS	X8, X25, X12

  (749) 0x4369f4 B.LE	436a74

  (749) 0x4369f8 ORR	X9, XZR, X12

  (749) 0x4369fc CMP	X8, #4

  (749) 0x436a00 B.CC	436a44

  (749) 0x436a04 LDR	X18, [SP, #16]

  (749) 0x436a08 AND	X11, X8, #8062

  (749) 0x436a0c ADD	X9, X12, X11

  (749) 0x436a10 ADD	X12, X18, X12,LSL #3

  (749) 0x436a14 ORR	X18, XZR, X11

  (749) 0x436a18 HINT	#0

  (749) 0x436a1c HINT	#0

    (759) 0x436a20 LDP	Q1, Q2, [X12, #2032]

    (759) 0x436a24 SUBS	X18, X18, #4

    (759) 0x436a28 FMUL	V2.2D, V2.2D, V0.D[0]

    (759) 0x436a2c FMUL	V1.2D, V1.2D, V0.D[0]

    (759) 0x436a30 STP	Q1, Q2, [X12, #2032]

    (759) 0x436a34 ADD	X12, X12, #32

    (759) 0x436a38 B.NE	436a20

  (749) 0x436a3c CMP	X8, X11

  (749) 0x436a40 B.EQ	436a74

  (749) 0x436a44 LDR	X8, [SP, #32]

  (749) 0x436a48 ADD	X8, X8, X9,LSL #3

  (749) 0x436a4c SUB	X9, X25, X9

  (749) 0x436a50 HINT	#0

  (749) 0x436a54 HINT	#0

  (749) 0x436a58 HINT	#0

  (749) 0x436a5c HINT	#0

    (758) 0x436a60 LDR	D1, [X8]

    (758) 0x436a64 SUBS	X9, X9, #1

    (758) 0x436a68 FMUL	D1, D0, D1

    (758) 0x436a6c STR	D1, [X8], #8

    (758) 0x436a70 B.NE	436a60

  (749) 0x436a74 LDR	X12, [X0, X30,LSL #3]

  (749) 0x436a78 SUBS	X8, X7, X12

  (749) 0x436a7c B.LE	436664

  (749) 0x436a80 ORR	X9, XZR, X12

  (749) 0x436a84 CMP	X8, #4

  (749) 0x436a88 B.CC	436ac4

  (749) 0x436a8c LDR	X18, [SP, #8]

  (749) 0x436a90 AND	X11, X8, #8062

  (749) 0x436a94 ADD	X9, X12, X11

  (749) 0x436a98 ADD	X12, X18, X12,LSL #3

  (749) 0x436a9c ORR	X18, XZR, X11

    (757) 0x436aa0 LDP	Q1, Q2, [X12, #2032]

    (757) 0x436aa4 SUBS	X18, X18, #4

    (757) 0x436aa8 FMUL	V2.2D, V2.2D, V0.D[0]

    (757) 0x436aac FMUL	V1.2D, V1.2D, V0.D[0]

    (757) 0x436ab0 STP	Q1, Q2, [X12, #2032]

    (757) 0x436ab4 ADD	X12, X12, #32

    (757) 0x436ab8 B.NE	436aa0

  (749) 0x436abc CMP	X8, X11

  (749) 0x436ac0 B.EQ	436664

  (749) 0x436ac4 LDR	X8, [SP, #24]

  (749) 0x436ac8 ADD	X8, X8, X9,LSL #3

  (749) 0x436acc SUB	X9, X7, X9

  (749) 0x436ad0 HINT	#0

  (749) 0x436ad4 HINT	#0

  (749) 0x436ad8 HINT	#0

  (749) 0x436adc HINT	#0

    (756) 0x436ae0 LDR	D1, [X8]

    (756) 0x436ae4 SUBS	X9, X9, #1

    (756) 0x436ae8 FMUL	D1, D0, D1

    (756) 0x436aec STR	D1, [X8], #8

    (756) 0x436af0 B.NE	436ae0

  (749) 0x436af4 B	436664

0x436af8 ORR	X0, XZR, X19

0x436afc BL	4a91d0

0x436b00 ORR	X0, XZR, X20

0x436b04 LDP	X20, X19, [SP, #288]

0x436b08 LDP	X22, X21, [SP, #272]

0x436b0c LDP	X24, X23, [SP, #256]

0x436b10 LDP	X26, X25, [SP, #240]

0x436b14 LDP	X28, X27, [SP, #224]

0x436b18 LDP	X29, X30, [SP, #208]

0x436b1c ADD	SP, SP, #304

0x436b20 B	4a91d0

0x436b24 HINT	#0

0x436b28 HINT	#0

0x436b2c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 33.00 to 26.50 cycles (1.25x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 33.00 to 2.50 cycles (13.20x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 640 bytes. The binary function is storing 384 bytes.

General properties

nb instructions	160
loop length	640
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	7.50	7.50	6.33	6.33	6.33	6.33	6.33	6.33	0.00	0.00	0.00	0.00	33.00	33.00	33.00	19.00	19.00
cycles	7.50	7.50	6.33	6.33	6.33	6.33	6.33	6.33	0.00	0.00	0.00	0.00	33.00	33.00	33.00	19.00	19.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.38
Overall L1	33.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 33.00 cycles. At this rate:

20% of peak load performance is reached (19.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 436410

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X7, X6, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X4, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X21, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X28, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X22, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 436510 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 43651c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 43652c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 436554 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X0, 4364f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 436554 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43657c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X25, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X9, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X8, X10, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X9, X9, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 436af8 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X10, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X2, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X8, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X9, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X8, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X9, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 436674 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a91d0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a91d0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-161-6712/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 33.00 to 2.50 cycles (13.20x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 640 bytes. The binary function is storing 384 bytes.

General properties

nb instructions	160
loop length	640
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

18.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	7.50	7.50	6.33	6.33	6.33	6.33	6.33	6.33	0.00	0.00	0.00	0.00	33.00	33.00	33.00	19.00	19.00
cycles	7.50	7.50	6.33	6.33	6.33	6.33	6.33	6.33	0.00	0.00	0.00	0.00	33.00	33.00	33.00	19.00	19.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	18.38
Overall L1	33.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 33.00 cycles. At this rate:

20% of peak load performance is reached (19.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.64 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 436410

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X7, X6, [X29, #992]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X4, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X9, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X21, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X28, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X27, X22, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STP X8, X9, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X8, X9, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X0, 436510 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x100>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X0, 43651c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 4a90d0 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 43652c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 436554 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBNZ X0, 4364f4 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 436554 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LT 43657c <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN X9, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae50 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X25, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4aae30 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X11, X0, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X25, X11	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
SDIV X10, X9, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
MADD X8, X10, X25, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X10, X10, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CSEL X9, X9, X10, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X8, X9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.GE 436af8 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x6e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X10, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X2, [X28]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X27]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X22]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X9, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X8, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X9, X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X9, X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X9]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X11, X8, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [X11]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X9, X9, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X8, X8, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X8, X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 436674 <hypre_BoomerAMGBuildMultipass.omp_outlined.18+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4a91d0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X20, X19, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X22, X21, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X24, X23, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X26, X25, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X28, X27, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X29, X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
B 4a91d0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass.omp_outlined.18–	0.44	0.08
○Loop 760 - par_multi_interp.c:1590-1591 - exec	0.19	0.03
▼Loop 750 - par_multi_interp.c:1605-1660 - exec–	0.00	0.00
▼Loop 749 - par_multi_interp.c:1605-1660 - exec–	0.05	0.01
○Loop 753 - par_multi_interp.c:1618-1628 - exec	0.20	0.03
○Loop 755 - par_multi_interp.c:1612-1615 - exec	0.00	0.01
○Loop 758 - par_multi_interp.c:1657-1658 - exec	0.00	0.00
○Loop 752 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 759 - par_multi_interp.c:1658-1658 - exec	0.00	0.00
○Loop 751 - par_multi_interp.c:1633-1636 - exec	0.00	0.00
○Loop 757 - par_multi_interp.c:1660-1660 - exec	0.00	0.00
○Loop 754 - par_multi_interp.c:1612-1615 - exec	0.00	0.00
○Loop 756 - par_multi_interp.c:1659-1660 - exec	0.00	0.00
○Loop 761 - par_multi_interp.c:1592-1593 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code