OV - exec - Loop 903

	Loop Id: 903	Module: exec	Source: par_multi_interp.c:385-410	Coverage: 0.13%

0x44eed8 CMN	X6, #1

0x44eedc B.EQ	452aac

0x44eee0 STR	XZR, [X15, X0,LSL #3]    [12]

0x44eee4 STR	XZR, [X18, X0,LSL #3]    [6]

0x44eee8 STR	X16, [X20, X0,LSL #3]    [15]

0x44eeec STR	X16, [X27, X0,LSL #3]    [27]

0x44eef0 ADD	X0, X0, #1

0x44eef4 LDR	X11, [X3, X0,LSL #3]    [10]

0x44eef8 CMP	X11, #1

0x44eefc B.EQ	44efac

0x44ef00 CMN	X11, #1

0x44ef04 B.EQ	452a90

0x44ef08 STR	XZR, [X15, X0,LSL #3]    [40]

0x44ef0c STR	XZR, [X18, X0,LSL #3]    [31]

0x44ef10 STR	X16, [X20, X0,LSL #3]    [42]

0x44ef14 STR	X16, [X27, X0,LSL #3]    [9]

0x44ef18 ADD	X7, X0, #1

0x44ef1c LDR	X8, [X3, X7,LSL #3]    [11]

0x44ef20 CMP	X8, #1

0x44ef24 B.EQ	44efd4

0x44ef28 CMN	X8, #1

0x44ef2c B.EQ	452a74

0x44ef30 STR	XZR, [X15, X7,LSL #3]    [38]

0x44ef34 STR	XZR, [X18, X7,LSL #3]    [17]

0x44ef38 STR	X16, [X20, X7,LSL #3]    [25]

0x44ef3c STR	X16, [X27, X7,LSL #3]    [5]

0x44ef40 ADD	X4, X0, #2

0x44ef44 LDR	X12, [X3, X4,LSL #3]    [28]

0x44ef48 CMP	X12, #1

0x44ef4c B.EQ	44effc

0x44ef50 CMN	X12, #1

0x44ef54 B.EQ	452a58

0x44ef58 STR	XZR, [X15, X4,LSL #3]    [33]

0x44ef5c STR	XZR, [X18, X4,LSL #3]    [14]

0x44ef60 STR	X16, [X20, X4,LSL #3]    [23]

0x44ef64 STR	X16, [X27, X4,LSL #3]    [2]

0x44ef68 LDR	X13, [SP, #312]    [26]

0x44ef6c ADD	X0, X0, #3

0x44ef70 CMP	X13, X0

0x44ef74 B.EQ	44f024

0x44ef78 LDR	X6, [X3, X0,LSL #3]    [29]

0x44ef7c CMP	X6, #1

0x44ef80 B.NE	44eed8

0x44ef84 STR	X1, [X27, X0,LSL #3]    [27]

0x44ef88 STR	X0, [X9, X1,LSL #3]    [7]

0x44ef8c ADD	X1, X1, #1

0x44ef90 STR	XZR, [X20, X0,LSL #3]    [15]

0x44ef94 STR	X6, [X15, X0,LSL #3]    [12]

0x44ef98 STR	XZR, [X18, X0,LSL #3]    [6]

0x44ef9c ADD	X0, X0, #1

0x44efa0 LDR	X11, [X3, X0,LSL #3]    [10]

0x44efa4 CMP	X11, #1

0x44efa8 B.NE	44ef00

0x44efac STR	X1, [X27, X0,LSL #3]    [8]

0x44efb0 ADD	X7, X0, #1

0x44efb4 STR	X0, [X9, X1,LSL #3]    [34]

0x44efb8 ADD	X1, X1, #1

0x44efbc STR	XZR, [X20, X0,LSL #3]    [41]

0x44efc0 STR	X11, [X15, X0,LSL #3]    [39]

0x44efc4 STR	XZR, [X18, X0,LSL #3]    [30]

0x44efc8 LDR	X8, [X3, X7,LSL #3]    [21]

0x44efcc CMP	X8, #1

0x44efd0 B.NE	44ef28

0x44efd4 STR	X1, [X27, X7,LSL #3]    [4]

0x44efd8 ADD	X4, X0, #2

0x44efdc STR	X7, [X9, X1,LSL #3]    [35]

0x44efe0 ADD	X1, X1, #1

0x44efe4 STR	XZR, [X20, X7,LSL #3]    [24]

0x44efe8 STR	X8, [X15, X7,LSL #3]    [37]

0x44efec STR	XZR, [X18, X7,LSL #3]    [16]

0x44eff0 LDR	X12, [X3, X4,LSL #3]    [43]

0x44eff4 CMP	X12, #1

0x44eff8 B.NE	44ef50

0x44effc STR	X1, [X27, X4,LSL #3]    [1]

0x44f000 ADD	X0, X0, #3

0x44f004 LDR	X13, [SP, #312]    [26]

0x44f008 STR	X4, [X9, X1,LSL #3]    [36]

0x44f00c ADD	X1, X1, #1

0x44f010 STR	XZR, [X20, X4,LSL #3]    [22]

0x44f014 STR	X12, [X15, X4,LSL #3]    [32]

0x44f018 STR	XZR, [X18, X4,LSL #3]    [13]

0x44f01c CMP	X13, X0

0x44f020 B.NE	44ef78

0x452a58 STR	X4, [X10, X5,LSL #3]    [20]

0x452a5c SUB	X5, X5, #1

0x452a60 STR	XZR, [X15, X4,LSL #3]    [33]

0x452a64 STR	XZR, [X18, X4,LSL #3]    [14]

0x452a68 STR	X12, [X20, X4,LSL #3]    [23]

0x452a6c STR	X12, [X27, X4,LSL #3]    [2]

0x452a70 B	44ef68

0x452a74 STR	X7, [X10, X5,LSL #3]    [19]

0x452a78 SUB	X5, X5, #1

0x452a7c STR	XZR, [X15, X7,LSL #3]    [38]

0x452a80 STR	XZR, [X18, X7,LSL #3]    [17]

0x452a84 STR	X8, [X20, X7,LSL #3]    [25]

0x452a88 STR	X8, [X27, X7,LSL #3]    [5]

0x452a8c B	44ef40

0x452a90 STR	X0, [X10, X5,LSL #3]    [18]

0x452a94 SUB	X5, X5, #1

0x452a98 STR	XZR, [X15, X0,LSL #3]    [40]

0x452a9c STR	XZR, [X18, X0,LSL #3]    [31]

0x452aa0 STR	X11, [X20, X0,LSL #3]    [42]

0x452aa4 STR	X11, [X27, X0,LSL #3]    [9]

0x452aa8 B	44ef18

0x452aac STR	X0, [X10, X5,LSL #3]    [3]

0x452ab0 SUB	X5, X5, #1

0x452ab4 STR	XZR, [X15, X0,LSL #3]    [12]

0x452ab8 STR	XZR, [X18, X0,LSL #3]    [6]

0x452abc STR	X6, [X20, X0,LSL #3]    [15]

0x452ac0 STR	X6, [X27, X0,LSL #3]    [27]

0x452ac4 B	44eef0

/home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 385 - 410

--------------------------------------------------------------------------------

385:    for (i = 0; i < n_fine; i++)

386:    {

387:       if (CF_marker[i] == 1)

388:       {

389:          fine_to_coarse[i] = cnt; /* this C point is assigned index

390:                                      coarse_counter on coarse grid,

391:                                      and in column of P */

392:          C_array[cnt++] = i;

393:          assigned[i] = 0;

394:          P_diag_i[i+1] = 1; /* one element in row i1 of P */

395:          P_offd_i[i+1] = 0;

396:       }

397:       else if (CF_marker[i] == -1)

398:       {

399:          pass_array[p_cnt--] = i;

400:          P_diag_i[i+1] = 0;

401:          P_offd_i[i+1] = 0;

402:          assigned[i] = -1;

403:          fine_to_coarse[i] = -1;

404:       }

405:       else

406:       {

407:          P_diag_i[i+1] = 0;

408:          P_offd_i[i+1] = 0;

409:          assigned[i] = -1;

410:          fine_to_coarse[i] = -1;

Coverage (%)	Name	Source Location	Module
►100.00+	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_main		libc-2.31.so
○	_start	amg.c:599	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	P10, P11, P13, P14,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:385-410
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	7.00
Front-end cycles	13.88
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	28.00
P10 cycles	28.00
P11 cycles	9.00
P12 cycles	28.00
P13 cycles	28.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	56.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.57
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	448.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.02
Bottlenecks	P10, P11, P13, P14,
Function	hypre_BoomerAMGBuildMultipass
Source	par_multi_interp.c:385-410
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	7.00
Front-end cycles	13.88
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	28.00
P10 cycles	28.00
P11 cycles	9.00
P12 cycles	28.00
P13 cycles	28.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	111.00
Nb uops	111.00
Nb loads	NA
Nb stores	56.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.57
Bytes prefetched	0.00
Bytes loaded	72.00
Bytes stored	448.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:385-410
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-817-3176/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:385-410.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 81 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 28.00 to 7.00 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00
cycles	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Overall L1	28.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

2% of peak load performance is reached (2.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44ef78

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMN X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452aac <hypre_BoomerAMGBuildMultipass+0x414c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44efac <hypre_BoomerAMGBuildMultipass+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a90 <hypre_BoomerAMGBuildMultipass+0x4130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X3, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44efd4 <hypre_BoomerAMGBuildMultipass+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a74 <hypre_BoomerAMGBuildMultipass+0x4114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44effc <hypre_BoomerAMGBuildMultipass+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a58 <hypre_BoomerAMGBuildMultipass+0x40f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44f024 <hypre_BoomerAMGBuildMultipass+0x6c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44eed8 <hypre_BoomerAMGBuildMultipass+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44ef00 <hypre_BoomerAMGBuildMultipass+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X3, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44ef28 <hypre_BoomerAMGBuildMultipass+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X7, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44ef50 <hypre_BoomerAMGBuildMultipass+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44ef78 <hypre_BoomerAMGBuildMultipass+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X4, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44ef68 <hypre_BoomerAMGBuildMultipass+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X7, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44ef40 <hypre_BoomerAMGBuildMultipass+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44ef18 <hypre_BoomerAMGBuildMultipass+0x5b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44eef0 <hypre_BoomerAMGBuildMultipass+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	hypre_BoomerAMGBuildMultipass
Source file and lines	par_multi_interp.c:385-410
Module	exec

Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 81 paths individually, rerun with max-paths=81
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 72 bytes. The binary loop is storing 448 bytes.

General properties

nb instructions	111
loop length	444
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00
cycles	8.50	8.50	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	28.00	28.00	9.00	28.00	28.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.88
Overall L1	28.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

2% of peak load performance is reached (2.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44ef78

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMN X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452aac <hypre_BoomerAMGBuildMultipass+0x414c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44efac <hypre_BoomerAMGBuildMultipass+0x64c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a90 <hypre_BoomerAMGBuildMultipass+0x4130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [X3, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44efd4 <hypre_BoomerAMGBuildMultipass+0x674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a74 <hypre_BoomerAMGBuildMultipass+0x4114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44effc <hypre_BoomerAMGBuildMultipass+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMN X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 452a58 <hypre_BoomerAMGBuildMultipass+0x40f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 44f024 <hypre_BoomerAMGBuildMultipass+0x6c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44eed8 <hypre_BoomerAMGBuildMultipass+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X11, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44ef00 <hypre_BoomerAMGBuildMultipass+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X3, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44ef28 <hypre_BoomerAMGBuildMultipass+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X7, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X3, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44ef50 <hypre_BoomerAMGBuildMultipass+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, X0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [SP, #312]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 44ef78 <hypre_BoomerAMGBuildMultipass+0x618>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X4, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [X27, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44ef68 <hypre_BoomerAMGBuildMultipass+0x608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X7, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X15, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X27, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44ef40 <hypre_BoomerAMGBuildMultipass+0x5e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X11, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44ef18 <hypre_BoomerAMGBuildMultipass+0x5b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [X27, X0,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44eef0 <hypre_BoomerAMGBuildMultipass+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code